git.rot13.org Git - simavr/blob - simavr/sim/sim_core.c

   1 /*
   2         sim_core.c
   3
   4         Copyright 2008, 2009 Michel Pollet <buserror@gmail.com>
   5
   6         This file is part of simavr.
   7
   8         simavr is free software: you can redistribute it and/or modify
   9         it under the terms of the GNU General Public License as published by
  10         the Free Software Foundation, either version 3 of the License, or
  11         (at your option) any later version.
  12
  13         simavr is distributed in the hope that it will be useful,
  14         but WITHOUT ANY WARRANTY; without even the implied warranty of
  15         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16         GNU General Public License for more details.
  17
  18         You should have received a copy of the GNU General Public License
  19         along with simavr.  If not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include <stdlib.h>
  23 #include <stdio.h>
  24 #include <string.h>
  25 #include <ctype.h>
  26 #include "sim_avr.h"
  27 #include "sim_core.h"
  28 #include "avr_flash.h"
  29 #include "avr_watchdog.h"
  30
  31 // SREG bit names
  32 const char * _sreg_bit_name = "cznvshti";
  33
  34 /*
  35  * Handle "touching" registers, marking them changed.
  36  * This is used only for debugging purposes to be able to
  37  * print the effects of each instructions on registers
  38  */
  39 #if CONFIG_SIMAVR_TRACE
  40
  41 #define T(w) w
  42
  43 #define REG_TOUCH(a, r) (a)->touched[(r) >> 5] |= (1 << ((r) & 0x1f))
  44 #define REG_ISTOUCHED(a, r) ((a)->touched[(r) >> 5] & (1 << ((r) & 0x1f)))
  45
  46 /*
  47  * This allows a "special case" to skip indtruction tracing when in these
  48  * symbols. since printf() is useful to have, but generates a lot of cycles
  49  */
  50 int dont_trace(const char * name)
  51 {
  52         return (
  53                 !strcmp(name, "uart_putchar") ||
  54                 !strcmp(name, "fputc") ||
  55                 !strcmp(name, "printf") ||
  56                 !strcmp(name, "vfprintf") ||
  57                 !strcmp(name, "__ultoa_invert") ||
  58                 !strcmp(name, "__prologue_saves__") ||
  59                 !strcmp(name, "__epilogue_restores__"));
  60 }
  61
  62 int donttrace = 0;
  63
  64 #define STATE(_f, args...) { \
  65         if (avr->trace) {\
  66                 if (avr->codeline && avr->codeline[avr->pc>>1]) {\
  67                         const char * symn = avr->codeline[avr->pc>>1]->symbol; \
  68                         int dont = 0 && dont_trace(symn);\
  69                         if (dont!=donttrace) { \
  70                                 donttrace = dont;\
  71                                 DUMP_REG();\
  72                         }\
  73                         if (donttrace==0)\
  74                                 printf("%04x: %-25s " _f, avr->pc, symn, ## args);\
  75                 } else \
  76                         printf("%s: %04x: " _f, __FUNCTION__, avr->pc, ## args);\
  77                 }\
  78         }
  79 #define SREG() if (avr->trace && donttrace == 0) {\
  80         printf("%04x: \t\t\t\t\t\t\t\t\tSREG = ", avr->pc); \
  81         for (int _sbi = 0; _sbi < 8; _sbi++)\
  82                 printf("%c", avr->sreg[_sbi] ? toupper(_sreg_bit_name[_sbi]) : '.');\
  83         printf("\n");\
  84 }
  85 #else
  86 #define T(w)
  87 #define REG_TOUCH(a, r)
  88 #define STATE(_f, args...)
  89 #define SREG()
  90 #endif
  91
  92 void avr_core_watch_write(avr_t *avr, uint16_t addr, uint8_t v)
  93 {
  94         if (addr > avr->ramend) {
  95                 printf("*** Invalid write address PC=%04x SP=%04x O=%04x Address %04x=%02x out of ram\n",
  96                                 avr->pc, _avr_sp_get(avr), avr->flash[avr->pc] | (avr->flash[avr->pc]<<8), addr, v);
  97                 CRASH();
  98         }
  99         if (addr < 32) {
 100                 printf("*** Invalid write address PC=%04x SP=%04x O=%04x Address %04x=%02x low registers\n",
 101                                 avr->pc, _avr_sp_get(avr), avr->flash[avr->pc] | (avr->flash[avr->pc]<<8), addr, v);
 102                 CRASH();
 103         }
 104 #if AVR_STACK_WATCH
 105         /*
 106          * this checks that the current "function" is not doctoring the stack frame that is located
 107          * higher on the stack than it should be. It's a sign of code that has overrun it's stack
 108          * frame and is munching on it's own return address.
 109          */
 110         if (avr->stack_frame_index > 1 && addr > avr->stack_frame[avr->stack_frame_index-2].sp) {
 111                 printf("\e[31m%04x : munching stack SP %04x, A=%04x <= %02x\e[0m\n", avr->pc, _avr_sp_get(avr), addr, v);
 112         }
 113 #endif
 114         avr->data[addr] = v;
 115 }
 116
 117 uint8_t avr_core_watch_read(avr_t *avr, uint16_t addr)
 118 {
 119         if (addr > avr->ramend) {
 120                 printf("*** Invalid read address PC=%04x SP=%04x O=%04x Address %04x out of ram (%04x)\n",
 121                                 avr->pc, _avr_sp_get(avr), avr->flash[avr->pc] | (avr->flash[avr->pc]<<8), addr, avr->ramend);
 122                 CRASH();
 123         }
 124         return avr->data[addr];
 125 }
 126
 127 /*
 128  * Set a register (r < 256)
 129  * if it's an IO regisrer (> 31) also (try to) call any callback that was
 130  * registered to track changes to that register.
 131  */
 132 static inline void _avr_set_r(avr_t * avr, uint8_t r, uint8_t v)
 133 {
 134         REG_TOUCH(avr, r);
 135
 136         if (r == R_SREG) {
 137                 avr->data[R_SREG] = v;
 138                 // unsplit the SREG
 139                 for (int i = 0; i < 8; i++)
 140                         avr->sreg[i] = (v & (1 << i)) != 0;
 141                 SREG();
 142         }
 143         if (r > 31) {
 144                 uint8_t io = AVR_DATA_TO_IO(r);
 145                 if (avr->io[io].w.c)
 146                         avr->io[io].w.c(avr, r, v, avr->io[io].w.param);
 147                 else
 148                         avr->data[r] = v;
 149                 if (avr->io[io].irq) {
 150                         avr_raise_irq(avr->io[io].irq + AVR_IOMEM_IRQ_ALL, v);
 151                         for (int i = 0; i < 8; i++)
 152                                 avr_raise_irq(avr->io[io].irq + i, (v >> i) & 1);
 153                 }
 154         } else
 155                 avr->data[r] = v;
 156 }
 157
 158 /*
 159  * Stack pointer access
 160  */
 161 inline uint16_t _avr_sp_get(avr_t * avr)
 162 {
 163         return avr->data[R_SPL] | (avr->data[R_SPH] << 8);
 164 }
 165
 166 inline void _avr_sp_set(avr_t * avr, uint16_t sp)
 167 {
 168         _avr_set_r(avr, R_SPL, sp);
 169         _avr_set_r(avr, R_SPH, sp >> 8);
 170 }
 171
 172 /*
 173  * Set any address to a value; split between registers and SRAM
 174  */
 175 static inline void _avr_set_ram(avr_t * avr, uint16_t addr, uint8_t v)
 176 {
 177         if (addr < 256)
 178                 _avr_set_r(avr, addr, v);
 179         else
 180                 avr_core_watch_write(avr, addr, v);
 181 }
 182
 183 /*
 184  * Get a value from SRAM.
 185  */
 186 static inline uint8_t _avr_get_ram(avr_t * avr, uint16_t addr)
 187 {
 188         if (addr == R_SREG) {
 189                 /*
 190                  * SREG is special it's reconstructed when read
 191                  * while the core itself uses the "shortcut" array
 192                  */
 193                 avr->data[R_SREG] = 0;
 194                 for (int i = 0; i < 8; i++)
 195                         if (avr->sreg[i] > 1) {
 196                                 printf("** Invalid SREG!!\n");
 197                                 CRASH();
 198                         } else if (avr->sreg[i])
 199                                 avr->data[R_SREG] |= (1 << i);
 200
 201         } else if (addr > 31 && addr < 256) {
 202                 uint8_t io = AVR_DATA_TO_IO(addr);
 203
 204                 if (avr->io[io].r.c)
 205                         avr->data[addr] = avr->io[io].r.c(avr, addr, avr->io[io].r.param);
 206
 207                 if (avr->io[io].irq) {
 208                         uint8_t v = avr->data[addr];
 209                         avr_raise_irq(avr->io[io].irq + AVR_IOMEM_IRQ_ALL, v);
 210                         for (int i = 0; i < 8; i++)
 211                                 avr_raise_irq(avr->io[io].irq + i, (v >> i) & 1);
 212                 }
 213         }
 214         return avr_core_watch_read(avr, addr);
 215 }
 216
 217 /*
 218  * Stack push accessors. Push/pop 8 and 16 bits
 219  */
 220 static inline void _avr_push8(avr_t * avr, uint16_t v)
 221 {
 222         uint16_t sp = _avr_sp_get(avr);
 223         _avr_set_ram(avr, sp, v);
 224         _avr_sp_set(avr, sp-1);
 225 }
 226
 227 static inline uint8_t _avr_pop8(avr_t * avr)
 228 {
 229         uint16_t sp = _avr_sp_get(avr) + 1;
 230         uint8_t res = _avr_get_ram(avr, sp);
 231         _avr_sp_set(avr, sp);
 232         return res;
 233 }
 234
 235 inline void _avr_push16(avr_t * avr, uint16_t v)
 236 {
 237         _avr_push8(avr, v);
 238         _avr_push8(avr, v >> 8);
 239 }
 240
 241 static inline uint16_t _avr_pop16(avr_t * avr)
 242 {
 243         uint16_t res = _avr_pop8(avr) << 8;
 244         res |= _avr_pop8(avr);
 245         return res;
 246 }
 247
 248 /*
 249  * "Pretty" register names
 250  */
 251 const char * reg_names[255] = {
 252                 [R_XH] = "XH", [R_XL] = "XL",
 253                 [R_YH] = "YH", [R_YL] = "YL",
 254                 [R_ZH] = "ZH", [R_ZL] = "ZL",
 255                 [R_SPH] = "SPH", [R_SPL] = "SPL",
 256                 [R_SREG] = "SREG",
 257 };
 258
 259
 260 const char * avr_regname(uint8_t reg)
 261 {
 262         if (!reg_names[reg]) {
 263                 char tt[16];
 264                 if (reg < 32)
 265                         sprintf(tt, "r%d", reg);
 266                 else
 267                         sprintf(tt, "io:%02x", reg);
 268                 reg_names[reg] = strdup(tt);
 269         }
 270         return reg_names[reg];
 271 }
 272
 273 /*
 274  * Called when an invalid opcode is decoded
 275  */
 276 static void _avr_invalid_opcode(avr_t * avr)
 277 {
 278 #if CONFIG_SIMAVR_TRACE
 279         printf("\e[31m*** %04x: %-25s Invalid Opcode SP=%04x O=%04x \e[0m\n",
 280                         avr->pc, avr->codeline[avr->pc>>1]->symbol, _avr_sp_get(avr), avr->flash[avr->pc] | (avr->flash[avr->pc+1]<<8));
 281 #else
 282         printf("\e[31m*** %04x: Invalid Opcode SP=%04x O=%04x \e[0m\n",
 283                         avr->pc, _avr_sp_get(avr), avr->flash[avr->pc] | (avr->flash[avr->pc+1]<<8));
 284 #endif
 285 }
 286
 287 #if CONFIG_SIMAVR_TRACE
 288 /*
 289  * Dump changed registers when tracing
 290  */
 291 void avr_dump_state(avr_t * avr)
 292 {
 293         if (!avr->trace || donttrace)
 294                 return;
 295
 296         int doit = 0;
 297
 298         for (int r = 0; r < 3 && !doit; r++)
 299                 if (avr->touched[r])
 300                         doit = 1;
 301         if (!doit)
 302                 return;
 303         printf("                                       ->> ");
 304         const int r16[] = { R_SPL, R_XL, R_YL, R_ZL };
 305         for (int i = 0; i < 4; i++)
 306                 if (REG_ISTOUCHED(avr, r16[i]) || REG_ISTOUCHED(avr, r16[i]+1)) {
 307                         REG_TOUCH(avr, r16[i]);
 308                         REG_TOUCH(avr, r16[i]+1);
 309                 }
 310
 311         for (int i = 0; i < 3*32; i++)
 312                 if (REG_ISTOUCHED(avr, i)) {
 313                         printf("%s=%02x ", avr_regname(i), avr->data[i]);
 314                 }
 315         printf("\n");
 316 }
 317 #endif
 318
 319 #define get_r_d_10(o) \
 320                 const uint8_t r = ((o >> 5) & 0x10) | (o & 0xf); \
 321                 const uint8_t d = (o >> 4) & 0x1f;\
 322                 const uint8_t vd = avr->data[d], vr = avr->data[r];
 323 #define get_k_r16(o) \
 324                 const uint8_t r = 16 + ((o >> 4) & 0xf); \
 325                 const uint8_t k = ((o & 0x0f00) >> 4) | (o & 0xf);
 326
 327 /*
 328  * Add a "jump" address to the jump trace buffer
 329  */
 330 #if CONFIG_SIMAVR_TRACE
 331 #define TRACE_JUMP()\
 332         avr->old[avr->old_pci].pc = avr->pc;\
 333         avr->old[avr->old_pci].sp = _avr_sp_get(avr);\
 334         avr->old_pci = (avr->old_pci + 1) & (OLD_PC_SIZE-1);\
 335
 336 #if AVR_STACK_WATCH
 337 #define STACK_FRAME_PUSH()\
 338         avr->stack_frame[avr->stack_frame_index].pc = avr->pc;\
 339         avr->stack_frame[avr->stack_frame_index].sp = _avr_sp_get(avr);\
 340         avr->stack_frame_index++;
 341 #define STACK_FRAME_POP()\
 342         if (avr->stack_frame_index > 0) \
 343                 avr->stack_frame_index--;
 344 #else
 345 #define STACK_FRAME_PUSH()
 346 #define STACK_FRAME_POP()
 347 #endif
 348 #else /* CONFIG_SIMAVR_TRACE */
 349
 350 #define TRACE_JUMP()
 351 #define STACK_FRAME_PUSH()
 352 #define STACK_FRAME_POP()
 353
 354 #endif
 355
 356 /****************************************************************************\
 357  *
 358  * Helper functions for calculating the status register bit values.
 359  * See the Atmel data sheet for the instruction set for more info.
 360  *
 361 \****************************************************************************/
 362
 363 static uint8_t
 364 get_add_carry (uint8_t res, uint8_t rd, uint8_t rr, int b)
 365 {
 366     uint8_t resb = res >> b & 0x1;
 367     uint8_t rdb = rd >> b & 0x1;
 368     uint8_t rrb = rr >> b & 0x1;
 369     return (rdb & rrb) | (rrb & ~resb) | (~resb & rdb);
 370 }
 371
 372 static  uint8_t
 373 get_add_overflow (uint8_t res, uint8_t rd, uint8_t rr)
 374 {
 375     uint8_t res7 = res >> 7 & 0x1;
 376     uint8_t rd7 = rd >> 7 & 0x1;
 377     uint8_t rr7 = rr >> 7 & 0x1;
 378     return (rd7 & rr7 & ~res7) | (~rd7 & ~rr7 & res7);
 379 }
 380
 381 static  uint8_t
 382 get_sub_carry (uint8_t res, uint8_t rd, uint8_t rr, int b)
 383 {
 384     uint8_t resb = res >> b & 0x1;
 385     uint8_t rdb = rd >> b & 0x1;
 386     uint8_t rrb = rr >> b & 0x1;
 387     return (~rdb & rrb) | (rrb & resb) | (resb & ~rdb);
 388 }
 389
 390 static  uint8_t
 391 get_sub_overflow (uint8_t res, uint8_t rd, uint8_t rr)
 392 {
 393     uint8_t res7 = res >> 7 & 0x1;
 394     uint8_t rd7 = rd >> 7 & 0x1;
 395     uint8_t rr7 = rr >> 7 & 0x1;
 396     return (rd7 & ~rr7 & ~res7) | (~rd7 & rr7 & res7);
 397 }
 398
 399 static  uint8_t
 400 get_compare_carry (uint8_t res, uint8_t rd, uint8_t rr, int b)
 401 {
 402     uint8_t resb = (res >> b) & 0x1;
 403     uint8_t rdb = (rd >> b) & 0x1;
 404     uint8_t rrb = (rr >> b) & 0x1;
 405     return (~rdb & rrb) | (rrb & resb) | (resb & ~rdb);
 406 }
 407
 408 static  uint8_t
 409 get_compare_overflow (uint8_t res, uint8_t rd, uint8_t rr)
 410 {
 411     res >>= 7; rd >>= 7; rr >>= 7;
 412     /* The atmel data sheet says the second term is ~rd7 for CP
 413      * but that doesn't make any sense. You be the judge. */
 414     return (rd & ~rr & ~res) | (~rd & rr & res);
 415 }
 416
 417 static inline int _avr_is_instruction_32_bits(avr_t * avr, uint32_t pc)
 418 {
 419         uint16_t o = (avr->flash[pc] | (avr->flash[pc+1] << 8)) & 0xfc0f;
 420         return  o == 0x9200 || // STS ! Store Direct to Data Space
 421                         o == 0x9000 || // LDS Load Direct from Data Space
 422                         o == 0x940c || // JMP Long Jump
 423                         o == 0x940d || // JMP Long Jump
 424                         o == 0x940e ||  // CALL Long Call to sub
 425                         o == 0x940f; // CALL Long Call to sub
 426 }
 427
 428 /*
 429  * Main opcode decoder
 430  *
 431  * The decoder was written by following the datasheet in no particular order.
 432  * As I went along, I noticed "bit patterns" that could be used to factor opcodes
 433  * However, a lot of these only became apparent later on, so SOME instructions
 434  * (skip of bit set etc) are compact, and some could use some refactoring (the ALU
 435  * ones scream to be factored).
 436  * I assume that the decoder could easily be 2/3 of it's current size.
 437  *
 438  * + It lacks the "extended" XMega jumps.
 439  * + It also doesn't check whether the core it's
 440  *   emulating is supposed to have the fancy instructions, like multiply and such.
 441  *
 442  * The nunber of cycles taken by instruction has been added, but might not be
 443  * entirely accurate.
 444  */
 445 uint16_t avr_run_one(avr_t * avr)
 446 {
 447 #if CONFIG_SIMAVR_TRACE
 448         /*
 449          * this traces spurious reset or bad jumps
 450          */
 451         if ((avr->pc == 0 && avr->cycle > 0) || avr->pc >= avr->codeend) {
 452                 avr->trace = 1;
 453                 STATE("RESET\n");
 454                 CRASH();
 455         }
 456         avr->touched[0] = avr->touched[1] = avr->touched[2] = 0;
 457 #endif
 458
 459         uint32_t        opcode = (avr->flash[avr->pc + 1] << 8) | avr->flash[avr->pc];
 460         uint32_t        new_pc = avr->pc + 2;   // future "default" pc
 461         int             cycle = 1;
 462
 463         switch (opcode & 0xf000) {
 464                 case 0x0000: {
 465                         switch (opcode) {
 466                                 case 0x0000: {  // NOP
 467                                         STATE("nop\n");
 468                                 }       break;
 469                                 default: {
 470                                         switch (opcode & 0xfc00) {
 471                                                 case 0x0400: {  // CPC compare with carry 0000 01rd dddd rrrr
 472                                                         get_r_d_10(opcode);
 473                                                         uint8_t res = vd - vr - avr->sreg[S_C];
 474                                                         STATE("cpc %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res);
 475                                                         if (res)
 476                                                                 avr->sreg[S_Z] = 0;
 477                                                         avr->sreg[S_H] = get_compare_carry(res, vd, vr, 3);
 478                                                         avr->sreg[S_V] = get_compare_overflow(res, vd, vr);
 479                                                         avr->sreg[S_N] = (res >> 7) & 1;
 480                                                         avr->sreg[S_C] = get_compare_carry(res, vd, vr, 7);
 481                                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 482                                                         SREG();
 483                                                 }       break;
 484                                                 case 0x0c00: {  // ADD without carry 0000 11 rd dddd rrrr
 485                                                         get_r_d_10(opcode);
 486                                                         uint8_t res = vd + vr;
 487                                                         if (r == d) {
 488                                                                 STATE("lsl %s[%02x] = %02x\n", avr_regname(d), vd, res & 0xff);
 489                                                         } else {
 490                                                                 STATE("add %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res);
 491                                                         }
 492                                                         _avr_set_r(avr, d, res);
 493                                                         avr->sreg[S_Z] = res == 0;
 494                                                         avr->sreg[S_H] = get_add_carry(res, vd, vr, 3);
 495                                                         avr->sreg[S_V] = get_add_overflow(res, vd, vr);
 496                                                         avr->sreg[S_N] = (res >> 7) & 1;
 497                                                         avr->sreg[S_C] = get_add_carry(res, vd, vr, 7);
 498                                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 499                                                         SREG();
 500                                                 }       break;
 501                                                 case 0x0800: {  // SBC substract with carry 0000 10rd dddd rrrr
 502                                                         get_r_d_10(opcode);
 503                                                         uint8_t res = vd - vr - avr->sreg[S_C];
 504                                                         STATE("sbc %s[%02x], %s[%02x] = %02x\n", avr_regname(d), avr->data[d], avr_regname(r), avr->data[r], res);
 505                                                         _avr_set_r(avr, d, res);
 506                                                         if (res)
 507                                                                 avr->sreg[S_Z] = 0;
 508                                                         avr->sreg[S_H] = get_sub_carry(res, vd, vr, 3);
 509                                                         avr->sreg[S_V] = get_sub_overflow(res, vd, vr);
 510                                                         avr->sreg[S_N] = (res >> 7) & 1;
 511                                                         avr->sreg[S_C] = get_sub_carry(res, vd, vr, 7);
 512                                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 513                                                         SREG();
 514                                                 }       break;
 515                                                 default:
 516                                                         switch (opcode & 0xff00) {
 517                                                                 case 0x0100: {  // MOVW – Copy Register Word 0000 0001 dddd rrrr
 518                                                                         uint8_t d = ((opcode >> 4) & 0xf) << 1;
 519                                                                         uint8_t r = ((opcode) & 0xf) << 1;
 520                                                                         STATE("movw %s:%s, %s:%s[%02x%02x]\n", avr_regname(d), avr_regname(d+1), avr_regname(r), avr_regname(r+1), avr->data[r+1], avr->data[r]);
 521                                                                         _avr_set_r(avr, d, avr->data[r]);
 522                                                                         _avr_set_r(avr, d+1, avr->data[r+1]);
 523                                                                 }       break;
 524                                                                 case 0x0200: {  // MULS – Multiply Signed 0000 0010 dddd rrrr
 525                                                                         int8_t r = 16 + (opcode & 0xf);
 526                                                                         int8_t d = 16 + ((opcode >> 4) & 0xf);
 527                                                                         int16_t res = ((int8_t)avr->data[r]) * ((int8_t)avr->data[d]);
 528                                                                         STATE("muls %s[%d], %s[%02x] = %d\n", avr_regname(d), ((int8_t)avr->data[d]), avr_regname(r), ((int8_t)avr->data[r]), res);
 529                                                                         _avr_set_r(avr, 0, res);
 530                                                                         _avr_set_r(avr, 1, res >> 8);
 531                                                                         avr->sreg[S_C] = (res >> 15) & 1;
 532                                                                         avr->sreg[S_Z] = res == 0;
 533                                                                         SREG();
 534                                                                 }       break;
 535                                                                 case 0x0300: {  // MUL Multiply 0000 0011 fddd frrr
 536                                                                         int8_t r = 16 + (opcode & 0x7);
 537                                                                         int8_t d = 16 + ((opcode >> 4) & 0x7);
 538                                                                         int16_t res = 0;
 539                                                                         uint8_t c = 0;
 540                                                                         T(const char * name = "";)
 541                                                                         switch (opcode & 0x88) {
 542                                                                                 case 0x00:      // MULSU – Multiply Signed Unsigned 0000 0011 0ddd 0rrr
 543                                                                                         res = ((uint8_t)avr->data[r]) * ((int8_t)avr->data[d]);
 544                                                                                         c = (res >> 15) & 1;
 545                                                                                         T(name = "mulsu";)
 546                                                                                         break;
 547                                                                                 case 0x08:      // FMUL Fractional Multiply Unsigned 0000 0011 0ddd 1rrr
 548                                                                                         res = ((uint8_t)avr->data[r]) * ((uint8_t)avr->data[d]);
 549                                                                                         c = (res >> 15) & 1;
 550                                                                                         res <<= 1;
 551                                                                                         T(name = "fmul";)
 552                                                                                         break;
 553                                                                                 case 0x80:      // FMULS – Multiply Signed  0000 0011 1ddd 0rrr
 554                                                                                         res = ((int8_t)avr->data[r]) * ((int8_t)avr->data[d]);
 555                                                                                         c = (res >> 15) & 1;
 556                                                                                         res <<= 1;
 557                                                                                         T(name = "fmuls";)
 558                                                                                         break;
 559                                                                                 case 0x88:      // FMULSU – Multiply Signed Unsigned 0000 0011 1ddd 1rrr
 560                                                                                         res = ((uint8_t)avr->data[r]) * ((int8_t)avr->data[d]);
 561                                                                                         c = (res >> 15) & 1;
 562                                                                                         res <<= 1;
 563                                                                                         T(name = "fmulsu";)
 564                                                                                         break;
 565                                                                         }
 566                                                                         cycle++;
 567                                                                         STATE("%s %s[%d], %s[%02x] = %d\n", name, avr_regname(d), ((int8_t)avr->data[d]), avr_regname(r), ((int8_t)avr->data[r]), res);
 568                                                                         _avr_set_r(avr, 0, res);
 569                                                                         _avr_set_r(avr, 1, res >> 8);
 570                                                                         avr->sreg[S_C] = c;
 571                                                                         avr->sreg[S_Z] = res == 0;
 572                                                                         SREG();
 573                                                                 }       break;
 574                                                                 default: _avr_invalid_opcode(avr);
 575                                                         }
 576                                         }
 577                                 }
 578                         }
 579                 }       break;
 580
 581                 case 0x1000: {
 582                         switch (opcode & 0xfc00) {
 583                                 case 0x1800: {  // SUB without carry 0000 10 rd dddd rrrr
 584                                         get_r_d_10(opcode);
 585                                         uint8_t res = vd - vr;
 586                                         STATE("sub %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res);
 587                                         _avr_set_r(avr, d, res);
 588                                         avr->sreg[S_Z] = res == 0;
 589                                         avr->sreg[S_H] = get_sub_carry(res, vd, vr, 3);
 590                                         avr->sreg[S_V] = get_sub_overflow(res, vd, vr);
 591                                         avr->sreg[S_N] = (res >> 7) & 1;
 592                                         avr->sreg[S_C] = get_sub_carry(res, vd, vr, 7);
 593                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 594                                         SREG();
 595                                 }       break;
 596                                 case 0x1000: {  // CPSE Compare, skip if equal 0000 00 rd dddd rrrr
 597                                         get_r_d_10(opcode);
 598                                         uint16_t res = vd == vr;
 599                                         STATE("cpse %s[%02x], %s[%02x]\t; Will%s skip\n", avr_regname(d), avr->data[d], avr_regname(r), avr->data[r], res ? "":" not");
 600                                         if (res) {
 601                                                 if (_avr_is_instruction_32_bits(avr, new_pc)) {
 602                                                         new_pc += 4; cycle += 2;
 603                                                 } else {
 604                                                         new_pc += 2; cycle++;
 605                                                 }
 606                                         }
 607                                 }       break;
 608                                 case 0x1400: {  // CP Compare 0000 01 rd dddd rrrr
 609                                         get_r_d_10(opcode);
 610                                         uint8_t res = vd - vr;
 611                                         STATE("cp %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res);
 612                                         avr->sreg[S_Z] = res == 0;
 613                                         avr->sreg[S_H] = get_compare_carry(res, vd, vr, 3);
 614                                         avr->sreg[S_V] = get_compare_overflow(res, vd, vr);
 615                                         avr->sreg[S_N] = res >> 7;
 616                                         avr->sreg[S_C] = get_compare_carry(res, vd, vr, 7);
 617                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 618                                         SREG();
 619                                 }       break;
 620                                 case 0x1c00: {  // ADD with carry 0001 11 rd dddd rrrr
 621                                         get_r_d_10(opcode);
 622                                         uint8_t res = vd + vr + avr->sreg[S_C];
 623                                         if (r == d) {
 624                                                 STATE("rol %s[%02x] = %02x\n", avr_regname(d), avr->data[d], res);
 625                                         } else {
 626                                                 STATE("addc %s[%02x], %s[%02x] = %02x\n", avr_regname(d), avr->data[d], avr_regname(r), avr->data[r], res);
 627                                         }
 628                                         _avr_set_r(avr, d, res);
 629                                         avr->sreg[S_Z] = res == 0;
 630                                         avr->sreg[S_H] = get_add_carry(res, vd, vr, 3);
 631                                         avr->sreg[S_V] = get_add_overflow(res, vd, vr);
 632                                         avr->sreg[S_N] = (res >> 7) & 1;
 633                                         avr->sreg[S_C] = get_add_carry(res, vd, vr, 7);
 634                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 635                                         SREG();
 636                                 }       break;
 637                                 default: _avr_invalid_opcode(avr);
 638                         }
 639                 }       break;
 640
 641                 case 0x2000: {
 642                         switch (opcode & 0xfc00) {
 643                                 case 0x2000: {  // AND  0010 00rd dddd rrrr
 644                                         get_r_d_10(opcode);
 645                                         uint8_t res = vd & vr;
 646                                         if (r == d) {
 647                                                 STATE("tst %s[%02x]\n", avr_regname(d), avr->data[d]);
 648                                         } else {
 649                                                 STATE("and %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res);
 650                                         }
 651                                         _avr_set_r(avr, d, res);
 652                                         avr->sreg[S_Z] = res == 0;
 653                                         avr->sreg[S_N] = (res >> 7) & 1;
 654                                         avr->sreg[S_V] = 0;
 655                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 656                                         SREG();
 657                                 }       break;
 658                                 case 0x2400: {  // EOR  0010 01rd dddd rrrr
 659                                         get_r_d_10(opcode);
 660                                         uint8_t res = vd ^ vr;
 661                                         if (r==d) {
 662                                                 STATE("clr %s[%02x]\n", avr_regname(d), avr->data[d]);
 663                                         } else {
 664                                                 STATE("eor %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res);
 665                                         }
 666                                         _avr_set_r(avr, d, res);
 667                                         avr->sreg[S_Z] = res == 0;
 668                                         avr->sreg[S_N] = (res >> 7) & 1;
 669                                         avr->sreg[S_V] = 0;
 670                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 671                                         SREG();
 672                                 }       break;
 673                                 case 0x2800: {  // OR Logical OR        0010 10rd dddd rrrr
 674                                         get_r_d_10(opcode);
 675                                         uint8_t res = vd | vr;
 676                                         STATE("or %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res);
 677                                         _avr_set_r(avr, d, res);
 678                                         avr->sreg[S_Z] = res == 0;
 679                                         avr->sreg[S_N] = (res >> 7) & 1;
 680                                         avr->sreg[S_V] = 0;
 681                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 682                                         SREG();
 683                                 }       break;
 684                                 case 0x2c00: {  // MOV  0010 11rd dddd rrrr
 685                                         get_r_d_10(opcode);
 686                                         uint8_t res = vr;
 687                                         STATE("mov %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res);
 688                                         _avr_set_r(avr, d, res);
 689                                 }       break;
 690                                 default: _avr_invalid_opcode(avr);
 691                         }
 692                 }       break;
 693
 694                 case 0x3000: {  // CPI 0011 KKKK rrrr KKKK
 695                         get_k_r16(opcode);
 696                         uint8_t vr = avr->data[r];
 697                         uint8_t res = vr - k;
 698                         STATE("cpi %s[%02x], 0x%02x\n", avr_regname(r), vr, k);
 699
 700                         avr->sreg[S_Z] = res == 0;
 701                         avr->sreg[S_H] = get_compare_carry(res, vr, k, 3);
 702                         avr->sreg[S_V] = get_compare_overflow(res, vr, k);
 703                         avr->sreg[S_N] = (res >> 7) & 1;
 704                         avr->sreg[S_C] = get_compare_carry(res, vr, k, 7);
 705                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 706                         SREG();
 707                 }       break;
 708
 709                 case 0x4000: {  // SBCI Subtract Immediate With Carry 0101 10 kkkk dddd kkkk
 710                         get_k_r16(opcode);
 711                         uint8_t vr = avr->data[r];
 712                         uint8_t res = vr - k - avr->sreg[S_C];
 713                         STATE("sbci %s[%02x], 0x%02x = %02x\n", avr_regname(r), avr->data[r], k, res);
 714                         _avr_set_r(avr, r, res);
 715                         if (res)
 716                                 avr->sreg[S_Z] = 0;
 717                         avr->sreg[S_N] = (res >> 7) & 1;
 718                         avr->sreg[S_C] = (k + avr->sreg[S_C]) > vr;
 719                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 720                         SREG();
 721                 }       break;
 722
 723                 case 0x5000: {  // SUB Subtract Immediate 0101 10 kkkk dddd kkkk
 724                         get_k_r16(opcode);
 725                         uint8_t vr = avr->data[r];
 726                         uint8_t res = vr - k;
 727                         STATE("subi %s[%02x], 0x%02x = %02x\n", avr_regname(r), avr->data[r], k, res);
 728                         _avr_set_r(avr, r, res);
 729                         avr->sreg[S_Z] = res  == 0;
 730                         avr->sreg[S_N] = (res >> 7) & 1;
 731                         avr->sreg[S_C] = k > vr;
 732                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 733                         SREG();
 734                 }       break;
 735
 736                 case 0x6000: {  // ORI aka SBR  Logical AND with Immediate      0110 kkkk dddd kkkk
 737                         get_k_r16(opcode);
 738                         uint8_t res = avr->data[r] | k;
 739                         STATE("ori %s[%02x], 0x%02x\n", avr_regname(r), avr->data[r], k);
 740                         _avr_set_r(avr, r, res);
 741                         avr->sreg[S_Z] = res == 0;
 742                         avr->sreg[S_N] = (res >> 7) & 1;
 743                         avr->sreg[S_V] = 0;
 744                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 745                         SREG();
 746                 }       break;
 747
 748                 case 0x7000: {  // ANDI Logical AND with Immediate      0111 kkkk dddd kkkk
 749                         get_k_r16(opcode);
 750                         uint8_t res = avr->data[r] & k;
 751                         STATE("andi %s[%02x], 0x%02x\n", avr_regname(r), avr->data[r], k);
 752                         _avr_set_r(avr, r, res);
 753                         avr->sreg[S_Z] = res == 0;
 754                         avr->sreg[S_N] = (res >> 7) & 1;
 755                         avr->sreg[S_V] = 0;
 756                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 757                         SREG();
 758                 }       break;
 759
 760                 case 0xa000:
 761                 case 0x8000: {
 762                         switch (opcode & 0xd008) {
 763                                 case 0xa000:
 764                                 case 0x8000: {  // LD (LDD) – Load Indirect using Z 10q0 qq0r rrrr 0qqq
 765                                         uint16_t v = avr->data[R_ZL] | (avr->data[R_ZH] << 8);
 766                                         uint8_t r = (opcode >> 4) & 0x1f;
 767                                         uint8_t q = ((opcode & 0x2000) >> 8) | ((opcode & 0x0c00) >> 7) | (opcode & 0x7);
 768
 769                                         if (opcode & 0x0200) {
 770                                                 STATE("st (Z+%d[%04x]), %s[%02x]\n", q, v+q, avr_regname(r), avr->data[r]);
 771                                                 _avr_set_ram(avr, v+q, avr->data[r]);
 772                                         } else {
 773                                                 STATE("ld %s, (Z+%d[%04x])=[%02x]\n", avr_regname(r), q, v+q, avr->data[v+q]);
 774                                                 _avr_set_r(avr, r, _avr_get_ram(avr, v+q));
 775                                         }
 776                                         cycle += 2;
 777                                 }       break;
 778                                 case 0xa008:
 779                                 case 0x8008: {  // LD (LDD) – Load Indirect using Y 10q0 qq0r rrrr 1qqq
 780                                         uint16_t v = avr->data[R_YL] | (avr->data[R_YH] << 8);
 781                                         uint8_t r = (opcode >> 4) & 0x1f;
 782                                         uint8_t q = ((opcode & 0x2000) >> 8) | ((opcode & 0x0c00) >> 7) | (opcode & 0x7);
 783
 784                                         if (opcode & 0x0200) {
 785                                                 STATE("st (Y+%d[%04x]), %s[%02x]\n", q, v+q, avr_regname(r), avr->data[r]);
 786                                                 _avr_set_ram(avr, v+q, avr->data[r]);
 787                                         } else {
 788                                                 STATE("ld %s, (Y+%d[%04x])=[%02x]\n", avr_regname(r), q, v+q, avr->data[v+q]);
 789                                                 _avr_set_r(avr, r, _avr_get_ram(avr, v+q));
 790                                         }
 791                                         cycle += 2;
 792                                 }       break;
 793                                 default: _avr_invalid_opcode(avr);
 794                         }
 795                 }       break;
 796
 797                 case 0x9000: {
 798                         /* this is an annoying special case, but at least these lines handle all the SREG set/clear opcodes */
 799                         if ((opcode & 0xff0f) == 0x9408) {
 800                                 uint8_t b = (opcode >> 4) & 7;
 801                                 STATE("%s%c\n", opcode & 0x0080 ? "cl" : "se", _sreg_bit_name[b]);
 802                                 avr->sreg[b] = (opcode & 0x0080) == 0;
 803                                 SREG();
 804                         } else switch (opcode) {
 805                                 case 0x9588: { // SLEEP
 806                                         STATE("sleep\n");
 807                                         avr->state = cpu_Sleeping;
 808                                 }       break;
 809                                 case 0x9598: { // BREAK
 810                                         STATE("break\n");
 811                                         if (avr->gdb) {
 812                                                 // if gdb is on, we break here as in here
 813                                                 // and we do so until gdb restores the instruction
 814                                                 // that was here before
 815                                                 avr->state = cpu_StepDone;
 816                                                 new_pc = avr->pc;
 817                                                 cycle = 0;
 818                                         }
 819                                 }       break;
 820                                 case 0x95a8: { // WDR
 821                                         STATE("wdr\n");
 822                                         avr_ioctl(avr, AVR_IOCTL_WATCHDOG_RESET, 0);
 823                                 }       break;
 824                                 case 0x95e8: { // SPM
 825                                         STATE("spm\n");
 826                                         avr_ioctl(avr, AVR_IOCTL_FLASH_SPM, 0);
 827                                 }       break;
 828                                 case 0x9409:   // IJMP Indirect jump                                    1001 0100 0000 1001
 829                                 case 0x9419:   // EIJMP Indirect jump                                   1001 0100 0001 1001   bit 4 is "indirect"
 830                                 case 0x9509:   // ICALL Indirect Call to Subroutine             1001 0101 0000 1001
 831                                 case 0x9519: { // EICALL Indirect Call to Subroutine    1001 0101 0001 1001   bit 8 is "push pc"
 832                                         int e = opcode & 0x10;
 833                                         int p = opcode & 0x100;
 834                                         if (e && !avr->eind)
 835                                                 _avr_invalid_opcode(avr);
 836                                         uint16_t z = avr->data[R_ZL] | (avr->data[R_ZH] << 8);
 837                                         if (e)
 838                                                 z |= avr->data[avr->eind] << 16;
 839                                         STATE("%si%s Z[%04x]\n", e?"e":"", p?"call":"jmp", z << 1);
 840                                         if (p) {
 841                                                 cycle++;
 842                                                 _avr_push16(avr, new_pc >> 1);
 843                                         }
 844                                         new_pc = z << 1;
 845                                         cycle++;
 846                                         TRACE_JUMP();
 847                                 }       break;
 848                                 case 0x9518:    // RETI
 849                                 case 0x9508: {  // RET
 850                                         new_pc = _avr_pop16(avr) << 1;
 851                                         if (opcode & 0x10)      // reti
 852                                                 avr->sreg[S_I] = 1;
 853                                         cycle += 3;
 854                                         STATE("ret%s\n", opcode & 0x10 ? "i" : "");
 855                                         TRACE_JUMP();
 856                                         STACK_FRAME_POP();
 857                                 }       break;
 858                                 case 0x95c8: {  // LPM Load Program Memory R0 <- (Z)
 859                                         uint16_t z = avr->data[R_ZL] | (avr->data[R_ZH] << 8);
 860                                         STATE("lpm %s, (Z[%04x])\n", avr_regname(0), z);
 861                                         _avr_set_r(avr, 0, avr->flash[z]);
 862                                 }       break;
 863                                 case 0x9408:case 0x9418:case 0x9428:case 0x9438:case 0x9448:case 0x9458:case 0x9468:
 864                                 case 0x9478:
 865                                 {       // BSET 1001 0100 0ddd 1000
 866                                         uint8_t b = (opcode >> 4) & 7;
 867                                         avr->sreg[b] = 1;
 868                                         STATE("bset %c\n", _sreg_bit_name[b]);
 869                                         SREG();
 870                                 }       break;
 871                                 case 0x9488:case 0x9498:case 0x94a8:case 0x94b8:case 0x94c8:case 0x94d8:case 0x94e8:
 872                                 case 0x94f8:    // bit 7 is 'clear vs set'
 873                                 {       // BCLR 1001 0100 1ddd 1000
 874                                         uint8_t b = (opcode >> 4) & 7;
 875                                         avr->sreg[b] = 0;
 876                                         STATE("bclr %c\n", _sreg_bit_name[b]);
 877                                         SREG();
 878                                 }       break;
 879                                 default:  {
 880                                         switch (opcode & 0xfe0f) {
 881                                                 case 0x9000: {  // LDS Load Direct from Data Space, 32 bits
 882                                                         uint8_t r = (opcode >> 4) & 0x1f;
 883                                                         uint16_t x = (avr->flash[new_pc+1] << 8) | avr->flash[new_pc];
 884                                                         new_pc += 2;
 885                                                         STATE("lds %s[%02x], 0x%04x\n", avr_regname(r), avr->data[r], x);
 886                                                         _avr_set_r(avr, r, _avr_get_ram(avr, x));
 887                                                         cycle++;
 888                                                 }       break;
 889                                                 case 0x9005:
 890                                                 case 0x9004: {  // LPM Load Program Memory 1001 000d dddd 01oo
 891                                                         uint16_t z = avr->data[R_ZL] | (avr->data[R_ZH] << 8);
 892                                                         uint8_t r = (opcode >> 4) & 0x1f;
 893                                                         int op = opcode & 3;
 894                                                         STATE("lpm %s, (Z[%04x]%s)\n", avr_regname(r), z, opcode?"+":"");
 895                                                         _avr_set_r(avr, r, avr->flash[z]);
 896                                                         if (op == 1) {
 897                                                                 z++;
 898                                                                 _avr_set_r(avr, R_ZH, z >> 8);
 899                                                                 _avr_set_r(avr, R_ZL, z);
 900                                                         }
 901                                                         cycle += 2;
 902                                                 }       break;
 903                                                 case 0x9006:
 904                                                 case 0x9007: {  // ELPM Extended Load Program Memory 1001 000d dddd 01oo
 905                                                         if (!avr->rampz)
 906                                                                 _avr_invalid_opcode(avr);
 907                                                         uint16_t z = avr->data[R_ZL] | (avr->data[R_ZH] << 8) | (avr->data[avr->rampz] << 16);
 908                                                         uint8_t r = (opcode >> 4) & 0x1f;
 909                                                         int op = opcode & 3;
 910                                                         STATE("elpm %s, (Z[%02x:%04x]%s)\n", avr_regname(r), z >> 16, z&0xffff, opcode?"+":"");
 911                                                         _avr_set_r(avr, r, avr->flash[z]);
 912                                                         if (op == 3) {
 913                                                                 z++;
 914                                                                 _avr_set_r(avr, avr->rampz, z >> 16);
 915                                                                 _avr_set_r(avr, R_ZH, z >> 8);
 916                                                                 _avr_set_r(avr, R_ZL, z);
 917                                                         }
 918                                                         cycle += 2;
 919                                                 }       break;
 920                                                 /*
 921                                                  * Load store instructions
 922                                                  *
 923                                                  * 1001 00sr rrrr iioo
 924                                                  * s = 0 = load, 1 = store
 925                                                  * ii = 16 bits register index, 11 = Z, 10 = Y, 00 = X
 926                                                  * oo = 1) post increment, 2) pre-decrement
 927                                                  */
 928                                                 case 0x900c:
 929                                                 case 0x900d:
 930                                                 case 0x900e: {  // LD Load Indirect from Data using X 1001 000r rrrr 11oo
 931                                                         int op = opcode & 3;
 932                                                         uint8_t r = (opcode >> 4) & 0x1f;
 933                                                         uint16_t x = (avr->data[R_XH] << 8) | avr->data[R_XL];
 934                                                         STATE("ld %s, %sX[%04x]%s\n", avr_regname(r), op == 2 ? "--" : "", x, op == 1 ? "++" : "");
 935
 936                                                         if (op == 2) x--;
 937                                                         _avr_set_r(avr, r, _avr_get_ram(avr, x));
 938                                                         if (op == 1) x++;
 939                                                         _avr_set_r(avr, R_XH, x >> 8);
 940                                                         _avr_set_r(avr, R_XL, x);
 941                                                 }       break;
 942                                                 case 0x920c:
 943                                                 case 0x920d:
 944                                                 case 0x920e: {  // ST Store Indirect Data Space X 1001 001r rrrr 11oo
 945                                                         int op = opcode & 3;
 946                                                         uint8_t r = (opcode >> 4) & 0x1f;
 947                                                         uint16_t x = (avr->data[R_XH] << 8) | avr->data[R_XL];
 948                                                         STATE("st %sX[%04x]%s, %s[%02x] \n", op == 2 ? "--" : "", x, op == 1 ? "++" : "", avr_regname(r), avr->data[r]);
 949                                                         cycle++;
 950                                                         if (op == 2) x--;
 951                                                         _avr_set_ram(avr, x, avr->data[r]);
 952                                                         if (op == 1) x++;
 953                                                         _avr_set_r(avr, R_XH, x >> 8);
 954                                                         _avr_set_r(avr, R_XL, x);
 955                                                 }       break;
 956                                                 case 0x9009:
 957                                                 case 0x900a: {  // LD Load Indirect from Data using Y 1001 000r rrrr 10oo
 958                                                         int op = opcode & 3;
 959                                                         uint8_t r = (opcode >> 4) & 0x1f;
 960                                                         uint16_t y = (avr->data[R_YH] << 8) | avr->data[R_YL];
 961                                                         STATE("ld %s, %sY[%04x]%s\n", avr_regname(r), op == 2 ? "--" : "", y, op == 1 ? "++" : "");
 962                                                         cycle++;
 963                                                         if (op == 2) y--;
 964                                                         _avr_set_r(avr, r, _avr_get_ram(avr, y));
 965                                                         if (op == 1) y++;
 966                                                         _avr_set_r(avr, R_YH, y >> 8);
 967                                                         _avr_set_r(avr, R_YL, y);
 968                                                 }       break;
 969                                                 case 0x9209:
 970                                                 case 0x920a: {  // ST Store Indirect Data Space Y 1001 001r rrrr 10oo
 971                                                         int op = opcode & 3;
 972                                                         uint8_t r = (opcode >> 4) & 0x1f;
 973                                                         uint16_t y = (avr->data[R_YH] << 8) | avr->data[R_YL];
 974                                                         STATE("st %sY[%04x]%s, %s[%02x] \n", op == 2 ? "--" : "", y, op == 1 ? "++" : "", avr_regname(r), avr->data[r]);
 975                                                         cycle++;
 976                                                         if (op == 2) y--;
 977                                                         _avr_set_ram(avr, y, avr->data[r]);
 978                                                         if (op == 1) y++;
 979                                                         _avr_set_r(avr, R_YH, y >> 8);
 980                                                         _avr_set_r(avr, R_YL, y);
 981                                                 }       break;
 982                                                 case 0x9200: {  // STS ! Store Direct to Data Space, 32 bits
 983                                                         uint8_t r = (opcode >> 4) & 0x1f;
 984                                                         uint16_t x = (avr->flash[new_pc+1] << 8) | avr->flash[new_pc];
 985                                                         new_pc += 2;
 986                                                         STATE("sts 0x%04x, %s[%02x]\n", x, avr_regname(r), avr->data[r]);
 987                                                         _avr_set_ram(avr, x, avr->data[r]);
 988                                                 }       break;
 989                                                 case 0x9001:
 990                                                 case 0x9002: {  // LD Load Indirect from Data using Z 1001 001r rrrr 00oo
 991                                                         int op = opcode & 3;
 992                                                         uint8_t r = (opcode >> 4) & 0x1f;
 993                                                         uint16_t z = (avr->data[R_ZH] << 8) | avr->data[R_ZL];
 994                                                         STATE("ld %s, %sZ[%04x]%s\n", avr_regname(r), op == 2 ? "--" : "", z, op == 1 ? "++" : "");
 995                                                         if (op == 2) z--;
 996                                                         _avr_set_r(avr, r, _avr_get_ram(avr, z));
 997                                                         if (op == 1) z++;
 998                                                         _avr_set_r(avr, R_ZH, z >> 8);
 999                                                         _avr_set_r(avr, R_ZL, z);
1000                                                 }       break;
1001                                                 case 0x9201:
1002                                                 case 0x9202: {  // ST Store Indirect Data Space Z 1001 001r rrrr 00oo
1003                                                         int op = opcode & 3;
1004                                                         uint8_t r = (opcode >> 4) & 0x1f;
1005                                                         uint16_t z = (avr->data[R_ZH] << 8) | avr->data[R_ZL];
1006                                                         STATE("st %sZ[%04x]%s, %s[%02x] \n", op == 2 ? "--" : "", z, op == 1 ? "++" : "", avr_regname(r), avr->data[r]);
1007                                                         if (op == 2) z--;
1008                                                         _avr_set_ram(avr, z, avr->data[r]);
1009                                                         if (op == 1) z++;
1010                                                         _avr_set_r(avr, R_ZH, z >> 8);
1011                                                         _avr_set_r(avr, R_ZL, z);
1012                                                 }       break;
1013                                                 case 0x900f: {  // POP 1001 000d dddd 1111
1014                                                         uint8_t r = (opcode >> 4) & 0x1f;
1015                                                         _avr_set_r(avr, r, _avr_pop8(avr));
1016                                                         T(uint16_t sp = _avr_sp_get(avr);)
1017                                                         STATE("pop %s (@%04x)[%02x]\n", avr_regname(r), sp, avr->data[sp]);
1018                                                         cycle++;
1019                                                 }       break;
1020                                                 case 0x920f: {  // PUSH 1001 001d dddd 1111
1021                                                         uint8_t r = (opcode >> 4) & 0x1f;
1022                                                         _avr_push8(avr, avr->data[r]);
1023                                                         T(uint16_t sp = _avr_sp_get(avr);)
1024                                                         STATE("push %s[%02x] (@%04x)\n", avr_regname(r), avr->data[r], sp);
1025                                                         cycle++;
1026                                                 }       break;
1027                                                 case 0x9400: {  // COM – One’s Complement
1028                                                         uint8_t r = (opcode >> 4) & 0x1f;
1029                                                         uint8_t res = 0xff - avr->data[r];
1030                                                         STATE("com %s[%02x] = %02x\n", avr_regname(r), avr->data[r], res);
1031                                                         _avr_set_r(avr, r, res);
1032                                                         avr->sreg[S_Z] = res == 0;
1033                                                         avr->sreg[S_N] = res >> 7;
1034                                                         avr->sreg[S_V] = 0;
1035                                                         avr->sreg[S_C] = 1;
1036                                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
1037                                                         SREG();
1038                                                 }       break;
1039                                                 case 0x9401: {  // NEG – One’s Complement
1040                                                         uint8_t r = (opcode >> 4) & 0x1f;
1041                                                         uint8_t rd = avr->data[r];
1042                                                         uint8_t res = 0x00 - rd;
1043                                                         STATE("neg %s[%02x] = %02x\n", avr_regname(r), rd, res);
1044                                                         _avr_set_r(avr, r, res);
1045                                                         avr->sreg[S_H] = ((res >> 3) | (rd >> 3)) & 1;
1046                                                         avr->sreg[S_Z] = res == 0;
1047                                                         avr->sreg[S_N] = res >> 7;
1048                                                         avr->sreg[S_V] = res == 0x80;
1049                                                         avr->sreg[S_C] = res != 0;
1050                                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
1051                                                         SREG();
1052                                                 }       break;
1053                                                 case 0x9402: {  // SWAP – Swap Nibbles
1054                                                         uint8_t r = (opcode >> 4) & 0x1f;
1055                                                         uint8_t res = (avr->data[r] >> 4) | (avr->data[r] << 4) ;
1056                                                         STATE("swap %s[%02x] = %02x\n", avr_regname(r), avr->data[r], res);
1057                                                         _avr_set_r(avr, r, res);
1058                                                 }       break;
1059                                                 case 0x9403: {  // INC – Increment
1060                                                         uint8_t r = (opcode >> 4) & 0x1f;
1061                                                         uint8_t res = avr->data[r] + 1;
1062                                                         STATE("inc %s[%02x] = %02x\n", avr_regname(r), avr->data[r], res);
1063                                                         _avr_set_r(avr, r, res);
1064                                                         avr->sreg[S_Z] = res == 0;
1065                                                         avr->sreg[S_N] = res >> 7;
1066                                                         avr->sreg[S_V] = res == 0x7f;
1067                                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
1068                                                         SREG();
1069                                                 }       break;
1070                                                 case 0x9405: {  // ASR – Arithmetic Shift Right 1001 010d dddd 0101
1071                                                         uint8_t r = (opcode >> 4) & 0x1f;
1072                                                         uint8_t vr = avr->data[r];
1073                                                         uint8_t res = (vr >> 1) | (vr & 0x80);
1074                                                         STATE("asr %s[%02x]\n", avr_regname(r), vr);
1075                                                         _avr_set_r(avr, r, res);
1076                                                         avr->sreg[S_Z] = res == 0;
1077                                                         avr->sreg[S_C] = vr & 1;
1078                                                         avr->sreg[S_N] = res >> 7;
1079                                                         avr->sreg[S_V] = avr->sreg[S_N] ^ avr->sreg[S_C];
1080                                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
1081                                                         SREG();
1082                                                 }       break;
1083                                                 case 0x9406: {  // LSR 1001 010d dddd 0110
1084                                                         uint8_t r = (opcode >> 4) & 0x1f;
1085                                                         uint8_t vr = avr->data[r];
1086                                                         uint8_t res = vr >> 1;
1087                                                         STATE("lsr %s[%02x]\n", avr_regname(r), vr);
1088                                                         _avr_set_r(avr, r, res);
1089                                                         avr->sreg[S_Z] = res == 0;
1090                                                         avr->sreg[S_C] = vr & 1;
1091                                                         avr->sreg[S_N] = 0;
1092                                                         avr->sreg[S_V] = avr->sreg[S_N] ^ avr->sreg[S_C];
1093                                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
1094                                                         SREG();
1095                                                 }       break;
1096                                                 case 0x9407: {  // ROR 1001 010d dddd 0111
1097                                                         uint8_t r = (opcode >> 4) & 0x1f;
1098                                                         uint8_t vr = avr->data[r];
1099                                                         uint8_t res = (avr->sreg[S_C] ? 0x80 : 0) | vr >> 1;
1100                                                         STATE("ror %s[%02x]\n", avr_regname(r), vr);
1101                                                         _avr_set_r(avr, r, res);
1102                                                         avr->sreg[S_Z] = res == 0;
1103                                                         avr->sreg[S_C] = vr & 1;
1104                                                         avr->sreg[S_N] = 0;
1105                                                         avr->sreg[S_V] = avr->sreg[S_N] ^ avr->sreg[S_C];
1106                                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
1107                                                         SREG();
1108                                                 }       break;
1109                                                 case 0x940a: {  // DEC – Decrement
1110                                                         uint8_t r = (opcode >> 4) & 0x1f;
1111                                                         uint8_t res = avr->data[r] - 1;
1112                                                         STATE("dec %s[%02x] = %02x\n", avr_regname(r), avr->data[r], res);
1113                                                         _avr_set_r(avr, r, res);
1114                                                         avr->sreg[S_Z] = res == 0;
1115                                                         avr->sreg[S_N] = res >> 7;
1116                                                         avr->sreg[S_V] = res == 0x80;
1117                                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
1118                                                         SREG();
1119                                                 }       break;
1120                                                 case 0x940c:
1121                                                 case 0x940d: {  // JMP Long Call to sub, 32 bits
1122                                                         uint32_t a = ((opcode & 0x01f0) >> 3) | (opcode & 1);
1123                                                         uint16_t x = (avr->flash[new_pc+1] << 8) | avr->flash[new_pc];
1124                                                         a = (a << 16) | x;
1125                                                         STATE("jmp 0x%06x\n", a);
1126                                                         new_pc = a << 1;
1127                                                         cycle += 2;
1128                                                         TRACE_JUMP();
1129                                                 }       break;
1130                                                 case 0x940e:
1131                                                 case 0x940f: {  // CALL Long Call to sub, 32 bits
1132                                                         uint32_t a = ((opcode & 0x01f0) >> 3) | (opcode & 1);
1133                                                         uint16_t x = (avr->flash[new_pc+1] << 8) | avr->flash[new_pc];
1134                                                         a = (a << 16) | x;
1135                                                         STATE("call 0x%06x\n", a);
1136                                                         new_pc += 2;
1137                                                         _avr_push16(avr, new_pc >> 1);
1138                                                         new_pc = a << 1;
1139                                                         cycle += 3;     // 4 cycles
1140                                                         TRACE_JUMP();
1141                                                         STACK_FRAME_PUSH();
1142                                                 }       break;
1143
1144                                                 default: {
1145                                                         switch (opcode & 0xff00) {
1146                                                                 case 0x9600: {  // ADIW - Add Immediate to Word 1001 0110 KKdd KKKK
1147                                                                         uint8_t r = 24 + ((opcode >> 3) & 0x6);
1148                                                                         uint8_t k = ((opcode & 0x00c0) >> 2) | (opcode & 0xf);
1149                                                                         uint8_t rdl = avr->data[r], rdh = avr->data[r+1];
1150                                                                         uint32_t res = rdl | (rdh << 8);
1151                                                                         STATE("adiw %s:%s[%04x], 0x%02x\n", avr_regname(r), avr_regname(r+1), res, k);
1152                                                                         res += k;
1153                                                                         _avr_set_r(avr, r + 1, res >> 8);
1154                                                                         _avr_set_r(avr, r, res);
1155                                                                         avr->sreg[S_V] = ~(rdh >> 7) & ((res >> 15) & 1);
1156                                                                         avr->sreg[S_Z] = (res & 0xffff) == 0;
1157                                                                         avr->sreg[S_N] = (res >> 15) & 1;
1158                                                                         avr->sreg[S_C] = ~((res >> 15) & 1) & (rdh >> 7);
1159                                                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
1160                                                                         SREG();
1161                                                                         cycle++;
1162                                                                 }       break;
1163                                                                 case 0x9700: {  // SBIW - Subtract Immediate from Word 1001 0110 KKdd KKKK
1164                                                                         uint8_t r = 24 + ((opcode >> 3) & 0x6);
1165                                                                         uint8_t k = ((opcode & 0x00c0) >> 2) | (opcode & 0xf);
1166                                                                         uint8_t rdl = avr->data[r], rdh = avr->data[r+1];
1167                                                                         uint32_t res = rdl | (rdh << 8);
1168                                                                         STATE("sbiw %s:%s[%04x], 0x%02x\n", avr_regname(r), avr_regname(r+1), res, k);
1169                                                                         res -= k;
1170                                                                         _avr_set_r(avr, r + 1, res >> 8);
1171                                                                         _avr_set_r(avr, r, res);
1172                                                                         avr->sreg[S_V] = (rdh >> 7) & (~(res >> 15) & 1);
1173                                                                         avr->sreg[S_Z] = (res & 0xffff) == 0;
1174                                                                         avr->sreg[S_N] = (res >> 15) & 1;
1175                                                                         avr->sreg[S_C] = ((res >> 15) & 1) & (~rdh >> 7);
1176                                                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
1177                                                                         SREG();
1178                                                                         cycle++;
1179                                                                 }       break;
1180                                                                 case 0x9800: {  // CBI - Clear Bit in I/O Register 1001 1000 AAAA Abbb
1181                                                                         uint8_t io = ((opcode >> 3) & 0x1f) + 32;
1182                                                                         uint8_t b = opcode & 0x7;
1183                                                                         uint8_t res = _avr_get_ram(avr, io) & ~(1 << b);
1184                                                                         STATE("cbi %s[%04x], 0x%02x = %02x\n", avr_regname(io), avr->data[io], 1<<b, res);
1185                                                                         _avr_set_ram(avr, io, res);
1186                                                                         cycle++;
1187                                                                 }       break;
1188                                                                 case 0x9900: {  // SBIC - Skip if Bit in I/O Register is Cleared 1001 0111 AAAA Abbb
1189                                                                         uint8_t io = ((opcode >> 3) & 0x1f) + 32;
1190                                                                         uint8_t b = opcode & 0x7;
1191                                                                         uint8_t res = _avr_get_ram(avr, io) & (1 << b);
1192                                                                         STATE("sbic %s[%04x], 0x%02x\t; Will%s branch\n", avr_regname(io), avr->data[io], 1<<b, !res?"":" not");
1193                                                                         if (!res) {
1194                                                                                 if (_avr_is_instruction_32_bits(avr, new_pc)) {
1195                                                                                         new_pc += 4; cycle += 2;
1196                                                                                 } else {
1197                                                                                         new_pc += 2; cycle++;
1198                                                                                 }
1199                                                                         }
1200                                                                 }       break;
1201                                                                 case 0x9a00: {  // SBI - Set Bit in I/O Register 1001 1000 AAAA Abbb
1202                                                                         uint8_t io = ((opcode >> 3) & 0x1f) + 32;
1203                                                                         uint8_t b = opcode & 0x7;
1204                                                                         uint8_t res = _avr_get_ram(avr, io) | (1 << b);
1205                                                                         STATE("sbi %s[%04x], 0x%02x = %02x\n", avr_regname(io), avr->data[io], 1<<b, res);
1206                                                                         _avr_set_ram(avr, io, res);
1207                                                                         cycle++;
1208                                                                 }       break;
1209                                                                 case 0x9b00: {  // SBIS - Skip if Bit in I/O Register is Set 1001 1011 AAAA Abbb
1210                                                                         uint8_t io = ((opcode >> 3) & 0x1f) + 32;
1211                                                                         uint8_t b = opcode & 0x7;
1212                                                                         uint8_t res = _avr_get_ram(avr, io) & (1 << b);
1213                                                                         STATE("sbis %s[%04x], 0x%02x\t; Will%s branch\n", avr_regname(io), avr->data[io], 1<<b, res?"":" not");
1214                                                                         if (res) {
1215                                                                                 if (_avr_is_instruction_32_bits(avr, new_pc)) {
1216                                                                                         new_pc += 4; cycle += 2;
1217                                                                                 } else {
1218                                                                                         new_pc += 2; cycle++;
1219                                                                                 }
1220                                                                         }
1221                                                                 }       break;
1222                                                                 default:
1223                                                                         switch (opcode & 0xfc00) {
1224                                                                                 case 0x9c00: {  // MUL - Multiply Unsigned 1001 11rd dddd rrrr
1225                                                                                         get_r_d_10(opcode);
1226                                                                                         uint16_t res = vd * vr;
1227                                                                                         STATE("mul %s[%02x], %s[%02x] = %04x\n", avr_regname(d), vd, avr_regname(r), vr, res);
1228                                                                                         _avr_set_r(avr, 0, res);
1229                                                                                         _avr_set_r(avr, 1, res >> 8);
1230                                                                                         avr->sreg[S_Z] = res == 0;
1231                                                                                         avr->sreg[S_C] = (res >> 15) & 1;
1232                                                                                         SREG();
1233                                                                                 }       break;
1234                                                                                 default: _avr_invalid_opcode(avr);
1235                                                                         }
1236                                                         }
1237                                                 }       break;
1238                                         }
1239                                 }       break;
1240                         }
1241                 }       break;
1242
1243                 case 0xb000: {
1244                         switch (opcode & 0xf800) {
1245                                 case 0xb800: {  // OUT A,Rr 1011 1AAr rrrr AAAA
1246                                         uint8_t r = (opcode >> 4) & 0x1f;
1247                                         uint8_t A = ((((opcode >> 9) & 3) << 4) | ((opcode) & 0xf)) + 32;
1248                                         STATE("out %s, %s[%02x]\n", avr_regname(A), avr_regname(r), avr->data[r]);
1249                                         _avr_set_ram(avr, A, avr->data[r]);
1250                                 }       break;
1251                                 case 0xb000: {  // IN Rd,A 1011 0AAr rrrr AAAA
1252                                         uint8_t r = (opcode >> 4) & 0x1f;
1253                                         uint8_t A = ((((opcode >> 9) & 3) << 4) | ((opcode) & 0xf)) + 32;
1254                                         STATE("in %s, %s[%02x]\n", avr_regname(r), avr_regname(A), avr->data[A]);
1255                                         _avr_set_r(avr, r, _avr_get_ram(avr, A));
1256                                 }       break;
1257                                 default: _avr_invalid_opcode(avr);
1258                         }
1259                 }       break;
1260
1261                 case 0xc000: {
1262                         // RJMP 1100 kkkk kkkk kkkk
1263                         short o = ((short)(opcode << 4)) >> 4;
1264                         STATE("rjmp .%d [%04x]\n", o, new_pc + (o << 1));
1265                         new_pc = new_pc + (o << 1);
1266                         cycle++;
1267                         TRACE_JUMP();
1268                 }       break;
1269
1270                 case 0xd000: {
1271                         // RCALL 1100 kkkk kkkk kkkk
1272                         short o = ((short)(opcode << 4)) >> 4;
1273                         STATE("rcall .%d [%04x]\n", o, new_pc + (o << 1));
1274                         _avr_push16(avr, new_pc >> 1);
1275                         new_pc = new_pc + (o << 1);
1276                         cycle += 2;
1277                         // 'rcall .1' is used as a cheap "push 16 bits of room on the stack"
1278                         if (o != 0) {
1279                                 TRACE_JUMP();
1280                                 STACK_FRAME_PUSH();
1281                         }
1282                 }       break;
1283
1284                 case 0xe000: {  // LDI Rd, K 1110 KKKK RRRR KKKK -- aka SER (LDI r, 0xff)
1285                         uint8_t d = 16 + ((opcode >> 4) & 0xf);
1286                         uint8_t k = ((opcode & 0x0f00) >> 4) | (opcode & 0xf);
1287                         STATE("ldi %s, 0x%02x\n", avr_regname(d), k);
1288                         _avr_set_r(avr, d, k);
1289                 }       break;
1290
1291                 case 0xf000: {
1292                         switch (opcode & 0xfe00) {
1293                                 case 0xf000:
1294                                 case 0xf200:
1295                                 case 0xf400:
1296                                 case 0xf600: {  // All the SREG branches
1297                                         short o = ((short)(opcode << 6)) >> 9; // offset
1298                                         uint8_t s = opcode & 7;
1299                                         int set = (opcode & 0x0400) == 0;               // this bit means BRXC otherwise BRXS
1300                                         int branch = (avr->sreg[s] && set) || (!avr->sreg[s] && !set);
1301                                         const char *names[2][8] = {
1302                                                         { "brcc", "brne", "brpl", "brvc", NULL, "brhc", "brtc", "brid"},
1303                                                         { "brcs", "breq", "brmi", "brvs", NULL, "brhs", "brts", "brie"},
1304                                         };
1305                                         if (names[set][s]) {
1306                                                 STATE("%s .%d [%04x]\t; Will%s branch\n", names[set][s], o, new_pc + (o << 1), branch ? "":" not");
1307                                         } else {
1308                                                 STATE("%s%c .%d [%04x]\t; Will%s branch\n", set ? "brbs" : "brbc", _sreg_bit_name[s], o, new_pc + (o << 1), branch ? "":" not");
1309                                         }
1310                                         if (branch) {
1311                                                 cycle++;
1312                                                 new_pc = new_pc + (o << 1);
1313                                         }
1314                                 }       break;
1315                                 case 0xf800:
1316                                 case 0xf900: {  // BLD – Bit Store from T into a Bit in Register 1111 100r rrrr 0bbb
1317                                         uint8_t r = (opcode >> 4) & 0x1f; // register index
1318                                         uint8_t s = opcode & 7;
1319                                         uint8_t v = avr->data[r] | (avr->sreg[S_T] ? (1 << s) : 0);
1320                                         STATE("bld %s[%02x], 0x%02x = %02x\n", avr_regname(r), avr->data[r], 1 << s, v);
1321                                         _avr_set_r(avr, r, v);
1322                                 }       break;
1323                                 case 0xfa00:
1324                                 case 0xfb00:{   // BST – Bit Store into T from bit in Register 1111 100r rrrr 0bbb
1325                                         uint8_t r = (opcode >> 4) & 0x1f; // register index
1326                                         uint8_t s = opcode & 7;
1327                                         STATE("bst %s[%02x], 0x%02x\n", avr_regname(r), avr->data[r], 1 << s);
1328                                         avr->sreg[S_T] = (avr->data[r] >> s) & 1;
1329                                         SREG();
1330                                 }       break;
1331                                 case 0xfc00:
1332                                 case 0xfe00: {  // SBRS/SBRC – Skip if Bit in Register is Set/Clear 1111 11sr rrrr 0bbb
1333                                         uint8_t r = (opcode >> 4) & 0x1f; // register index
1334                                         uint8_t s = opcode & 7;
1335                                         int set = (opcode & 0x0200) != 0;
1336                                         int branch = ((avr->data[r] & (1 << s)) && set) || (!(avr->data[r] & (1 << s)) && !set);
1337                                         STATE("%s %s[%02x], 0x%02x\t; Will%s branch\n", set ? "sbrs" : "sbrc", avr_regname(r), avr->data[r], 1 << s, branch ? "":" not");
1338                                         if (branch) {
1339                                                 if (_avr_is_instruction_32_bits(avr, new_pc)) {
1340                                                         new_pc += 4; cycle += 2;
1341                                                 } else {
1342                                                         new_pc += 2; cycle++;
1343                                                 }
1344                                         }
1345                                 }       break;
1346                                 default: _avr_invalid_opcode(avr);
1347                         }
1348                 }       break;
1349
1350                 default: _avr_invalid_opcode(avr);
1351
1352         }
1353         avr->cycle += cycle;
1354         return new_pc;
1355 }
1356
1357