1 /* ****************************************************************************
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2 -- Source file: mesa_core.v
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3 -- Date: October 4, 2015
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5 -- Description: Wrapper around a bunch of Mesa Bus Modules. This takes in the
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6 -- binary nibble stream from mesa_phy and takes care of slot
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7 -- enumeration and subslot bus decoding to local-bus.
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8 -- SubSlot-0 is 32bit user localbus.
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9 -- SubSlot-E is 32bit SPI PROM Interface localbus.
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10 -- SubSlot-F is power management,etc.
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11 -- Language: Verilog-2001 and VHDL-1993
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12 -- Simulation: Mentor-Modelsim
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13 -- Synthesis: Xilinst-XST
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14 -- License: This project is licensed with the CERN Open Hardware Licence
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15 -- v1.2. You may redistribute and modify this project under the
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16 -- terms of the CERN OHL v.1.2. (http://ohwr.org/cernohl).
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17 -- This project is distributed WITHOUT ANY EXPRESS OR IMPLIED
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18 -- WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
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19 -- AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN OHL
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20 -- v.1.2 for applicable Conditions.
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22 -- Revision History:
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23 -- Ver# When Who What
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24 -- ---- -------- -------- ---------------------------------------------------
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25 -- 0.1 10.04.15 khubbard Creation
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26 -- ***************************************************************************/
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27 `default_nettype none // Strictly enforce all nets to be declared
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31 parameter spi_prom_en = 1
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38 output wire [31:0] lb_addr,
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39 output wire [31:0] lb_wr_d,
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40 input wire [31:0] lb_rd_d,
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41 input wire lb_rd_rdy,
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43 output wire spi_sck,
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44 output wire spi_cs_l,
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45 output wire spi_mosi,
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46 input wire spi_miso,
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47 input wire [3:0] rx_in_d,
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48 input wire rx_in_rdy,
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49 output reg [7:0] tx_byte_d,
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50 output reg tx_byte_rdy,
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53 output wire [7:0] tx_wo_byte,
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54 output wire tx_wo_rdy,
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56 input wire oob_done,
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58 output wire [8:0] subslot_ctrl,
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59 output wire reconfig_req,
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60 output wire [31:0] reconfig_addr,
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61 output wire bist_req
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62 );// module mesa_core
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67 wire [7:0] rx_loc_d;
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69 wire [7:0] tx_spi_byte_d;
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70 wire tx_spi_byte_rdy;
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72 wire [7:0] tx_lb_byte_d;
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73 wire tx_lb_byte_rdy;
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76 reg [3:0] tx_busy_sr;
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80 wire [31:0] prom_addr;
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81 wire [31:0] prom_wr_d;
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82 wire [31:0] prom_rd_d;
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87 wire [31:0] slot_size;
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88 wire [31:0] time_stamp_d;
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91 //-----------------------------------------------------------------------------
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92 // Decode the 2 PROM Addresses at 0x20 and 0x24 using combo logic
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93 //-----------------------------------------------------------------------------
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94 always @ ( * ) begin : proc_prom_decode
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96 if ( prom_addr[15:0] == 16'h0020 ) begin
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97 prom_cs_c <= prom_wr | prom_rd;
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101 if ( prom_addr[15:0] == 16'h0024 ) begin
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102 prom_cs_d <= prom_wr | prom_rd;
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107 end // proc_prom_decode
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110 // ----------------------------------------------------------------------------
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111 // Ro Mux : Mux between multiple byte sources for Ro readback path.
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112 // Note: There is no arbitration - 1st come 1st service requires that only
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113 // one device will send readback data ( polled requests ).
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114 // ----------------------------------------------------------------------------
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115 always @ ( posedge clk ) begin : proc_tx
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116 tx_busy_sr[0] <= tx_lb_byte_rdy | tx_spi_byte_rdy | tx_busy;
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117 tx_busy_sr[3:1] <= tx_busy_sr[2:0];
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118 tx_byte_rdy <= tx_lb_byte_rdy | tx_spi_byte_rdy;
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119 tx_done <= tx_lb_done | tx_spi_done | oob_done;// Sends LF
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121 if ( tx_lb_byte_rdy == 1 ) begin
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122 tx_byte_d <= tx_lb_byte_d[7:0];
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124 tx_byte_d <= tx_spi_byte_d[7:0];
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127 // Support pipeling Ro byte path by asserting busy for 4 clocks after a byte
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128 assign tx_busy_loc = ( tx_busy_sr != 4'b0000 ) ? 1 : 0;
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131 //-----------------------------------------------------------------------------
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132 // Decode Slot Addresses : Take in the Wi path as nibbles and generate the Wo
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133 // paths for both internal and external devices.
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134 //-----------------------------------------------------------------------------
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135 mesa_decode u_mesa_decode
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139 .rx_in_d ( rx_in_d[3:0] ),
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140 .rx_in_rdy ( rx_in_rdy ),
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141 .rx_out_d ( tx_wo_byte[7:0] ),
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142 .rx_out_rdy ( tx_wo_rdy ),
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143 .rx_loc_d ( rx_loc_d[7:0] ),
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144 .rx_loc_rdy ( rx_loc_rdy ),
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145 .rx_loc_start ( rx_loc_start ),
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146 .rx_loc_stop ( rx_loc_stop )
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150 //-----------------------------------------------------------------------------
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151 // Convert Subslots 0x0 and 0xE to 32bit local bus for user logic and prom
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152 //-----------------------------------------------------------------------------
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157 .rx_byte_d ( rx_loc_d[7:0] ),
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158 .rx_byte_rdy ( rx_loc_rdy ),
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159 .rx_byte_start ( rx_loc_start ),
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160 .rx_byte_stop ( rx_loc_stop ),
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161 .tx_byte_d ( tx_lb_byte_d[7:0] ),
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162 .tx_byte_rdy ( tx_lb_byte_rdy ),
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163 .tx_done ( tx_lb_done ),
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164 .tx_busy ( tx_busy_loc ),
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167 .lb_wr_d ( lb_wr_d[31:0] ),
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168 .lb_addr ( lb_addr[31:0] ),
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169 .lb_rd_d ( lb_rd_d[31:0] ),
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170 .lb_rd_rdy ( lb_rd_rdy ),
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171 .oob_en ( oob_en ),
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172 .oob_rd_d ( lb_rd_d[31:0] ),
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173 .oob_rd_rdy ( lb_rd_rdy ),
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174 .prom_wr ( prom_wr ),
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175 .prom_rd ( prom_rd ),
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176 .prom_wr_d ( prom_wr_d[31:0] ),
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177 .prom_addr ( prom_addr[31:0] ),
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178 .prom_rd_d ( prom_rd_d[31:0] ),
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179 .prom_rd_rdy ( prom_rd_rdy )
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183 //-----------------------------------------------------------------------------
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184 // Convert Subslots 0x1 to SPI
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185 // Use spi_ck_div of 0x7 for div-8 of 24 MHz to 3 MHz for SPI of 1.5 MHz.
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186 //-----------------------------------------------------------------------------
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187 //mesa2spi u_mesa2spi
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190 // .reset ( reset ),
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191 // .subslot ( 4'd1 ),
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192 // .spi_ck_div ( 4'd7 ),
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193 // .rx_byte_d ( rx_loc_d[7:0] ),
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194 // .rx_byte_rdy ( rx_loc_rdy ),
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195 // .rx_byte_start ( rx_loc_start ),
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196 // .rx_byte_stop ( rx_loc_stop ),
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198 // .tx_byte_d ( tx_spi_byte_d[7:0] ),
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199 // .tx_byte_rdy ( tx_spi_byte_rdy ),
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200 // .tx_done ( tx_spi_done ),
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201 // .tx_busy ( tx_busy_loc ),
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207 assign tx_spi_byte_d[7:0] = 8'd0;
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208 assign tx_spi_byte_rdy = 1'b0;
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209 assign tx_spi_done = 1'b0;
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212 //-----------------------------------------------------------------------------
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213 // Decode Subslot Nibble Controls
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214 //-----------------------------------------------------------------------------
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215 mesa2ctrl u_mesa2ctrl
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219 .rx_byte_d ( rx_loc_d[7:0] ),
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220 .rx_byte_rdy ( rx_loc_rdy ),
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221 .rx_byte_start ( rx_loc_start ),
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222 .rx_byte_stop ( rx_loc_stop ),
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223 .subslot_ctrl ( subslot_ctrl[8:0] )
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227 //-----------------------------------------------------------------------------
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228 // 32bit UNIX TimeStamp of when the design was synthesized
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229 //-----------------------------------------------------------------------------
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230 time_stamp u_time_stamp
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232 .time_dout ( time_stamp_d )
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236 //-----------------------------------------------------------------------------
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237 // Interface to SPI PROM : Allow LB to program SPI PROM, request reconfig
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238 // ck_divisor 10 is for ( 80M / 10 ) for 2x SPI Clock Rate of 4 MHz
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239 // ck_divisor 3 is for ( 24M / 3 ) for 2x SPI Clock Rate of 4 MHz
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241 // slot_size 0x00020000 is 1Mbit Slot for ICE5LP4K
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242 // slot_size 0x00040000 is 2Mbit Slot for XC3S200A (Compressed, no BRAM ROMs)
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243 // slot_size 0x00080000 is 4Mbit Slot for XC6SLX9 (Compressed, no BRAM ROMs)
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244 //-----------------------------------------------------------------------------
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246 if ( spi_prom_en == 1 ) begin
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247 spi_prom u_spi_prom
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250 .prom_is_32b ( 1'b0 ),
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251 .ck_divisor ( 8'd3 ),
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252 .slot_size ( slot_size[31:0] ),
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253 .protect_1st_slot ( 1'b1 ),
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256 .lb_cs_prom_c ( prom_cs_c ),
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257 .lb_cs_prom_d ( prom_cs_d ),
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258 .lb_wr ( prom_wr ),
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259 .lb_rd ( prom_rd ),
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260 .lb_wr_d ( prom_wr_d[31:0] ),
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261 .lb_rd_d ( prom_rd_d[31:0] ),
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262 .lb_rd_rdy ( prom_rd_rdy ),
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264 .spi_ctrl ( 4'b0000 ),
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265 .spi_sck ( spi_sck ),
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266 .spi_cs_l ( spi_cs_l ),
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267 .spi_mosi ( spi_mosi ),
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268 .spi_miso ( spi_miso ),
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271 .bist_req ( bist_req ),
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272 .reconfig_2nd_slot ( 1'b0 ),
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273 .reconfig_req ( reconfig_req ),
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274 .reconfig_addr ( reconfig_addr[31:0] )
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277 assign spi_sck = 1;
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278 assign spi_cs_l = 1;
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279 assign spi_mosi = 1;
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280 assign bist_req = 0;
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281 assign reconfig_req = 0;
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282 assign reconfig_addr = 32'd0;
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283 assign prom_rd_d = 32'd0;
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284 assign prom_rd_rdy = 0;
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287 assign slot_size = 32'h00020000;
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290 endmodule // mesa_core
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projects / BML_sump2 / blob