1 /* ****************************************************************************
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2 -- Source file: mesa_id.v
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3 -- Date: October 2015
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5 -- Description: Simple state machine the reports chip ID over mesa-bus on
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6 -- request and muxes in the normal Ro byte path when idle.
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7 -- Language: Verilog-2001
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8 -- Simulation: Mentor-Modelsim
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9 -- Synthesis: Lattice
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10 -- License: This project is licensed with the CERN Open Hardware Licence
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11 -- v1.2. You may redistribute and modify this project under the
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12 -- terms of the CERN OHL v.1.2. (http://ohwr.org/cernohl).
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13 -- This project is distributed WITHOUT ANY EXPRESS OR IMPLIED
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14 -- WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
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15 -- AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN OHL
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16 -- v.1.2 for applicable Conditions.
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18 -- Revision History:
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19 -- Ver# When Who What
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20 -- ---- -------- -------- ---------------------------------------------------
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21 -- 0.1 10.04.15 khubbard Creation
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22 -- ***************************************************************************/
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23 `default_nettype none // Strictly enforce all nets to be declared
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29 input wire report_id,
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30 input wire [31:0] id_mfr,
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31 input wire [31:0] id_dev,
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32 input wire [31:0] id_snum,
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33 input wire [7:0] mesa_core_ro_byte_d,
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34 input wire mesa_core_ro_byte_en,
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35 input wire mesa_core_ro_done,
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36 input wire mesa_ro_busy,
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37 output reg [7:0] mesa_ro_byte_d,
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38 output reg mesa_ro_byte_en,
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39 output reg mesa_ro_done
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44 reg [4:0] report_cnt;
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45 reg mesa_ro_busy_p1;
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46 wire [31:0] time_stamp_d;
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49 //-----------------------------------------------------------------------------
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50 // Ro binary bytes are converted to 2 ASCII nibble chars for MesaBus Ro
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51 // This is also a report_id FSM that muxes into the ro byte path on request.
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52 //-----------------------------------------------------------------------------
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53 always @ ( posedge clk ) begin : proc_mesa_ro_byte
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54 report_id_p1 <= report_id;
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55 mesa_ro_byte_d[7:0] <= mesa_core_ro_byte_d[7:0];
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56 mesa_ro_byte_en <= mesa_core_ro_byte_en;
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57 mesa_ro_done <= mesa_core_ro_done;
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58 mesa_ro_busy_p1 <= mesa_ro_busy;
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60 // When report_id asserts ( SubSlot 0xFA command ) shift out
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61 // a unique 32bit ID of 16 bit Manufacture and 16bit Device
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62 if ( report_id == 1 ) begin
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63 report_jk <= 1;// Start FSM
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67 // State Machine for sending out device id when requested
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68 mesa_ro_busy_p1 <= mesa_ro_busy;
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69 if ( report_jk == 1 ) begin
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70 mesa_ro_byte_en <= 0;
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73 if ( report_id_p1==1 || ( mesa_ro_busy_p1==1 && mesa_ro_busy==0 )) begin
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74 report_cnt <= report_cnt[4:0] + 1;
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75 mesa_ro_byte_en <= 1;
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76 if ( report_cnt == 5'd0 ) begin
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77 mesa_ro_byte_d[7:0] <= 8'hF0;// Header : Preamble
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78 end else if ( report_cnt == 5'd1 ) begin
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79 mesa_ro_byte_d[7:0] <= 8'hFE;// Header : Ro Slot is 0xFE
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80 end else if ( report_cnt == 5'd2 ) begin
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81 mesa_ro_byte_d[7:0] <= 8'h00;// Header : Ro Subslot is 0x00
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82 end else if ( report_cnt == 5'd3 ) begin
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83 mesa_ro_byte_d[7:0] <= 8'h10;// Header : 16 Bytes in Payload
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85 end else if ( report_cnt == 5'd4 ) begin
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86 mesa_ro_byte_d[7:0] <= id_mfr[31:24];
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87 end else if ( report_cnt == 5'd5 ) begin
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88 mesa_ro_byte_d[7:0] <= id_mfr[23:16];
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89 end else if ( report_cnt == 5'd6 ) begin
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90 mesa_ro_byte_d[7:0] <= id_mfr[15:8];
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91 end else if ( report_cnt == 5'd7 ) begin
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92 mesa_ro_byte_d[7:0] <= id_mfr[7:0];
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94 end else if ( report_cnt == 5'd8 ) begin
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95 mesa_ro_byte_d[7:0] <= id_dev[31:24];
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96 end else if ( report_cnt == 5'd9 ) begin
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97 mesa_ro_byte_d[7:0] <= id_dev[23:16];
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98 end else if ( report_cnt == 5'd10) begin
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99 mesa_ro_byte_d[7:0] <= id_dev[15:8];
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100 end else if ( report_cnt == 5'd11) begin
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101 mesa_ro_byte_d[7:0] <= id_dev[7:0];
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103 end else if ( report_cnt == 5'd12) begin
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104 mesa_ro_byte_d[7:0] <= id_snum[31:24];
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105 end else if ( report_cnt == 5'd13) begin
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106 mesa_ro_byte_d[7:0] <= id_snum[23:16];
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107 end else if ( report_cnt == 5'd14) begin
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108 mesa_ro_byte_d[7:0] <= id_snum[15:8];
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109 end else if ( report_cnt == 5'd15) begin
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110 mesa_ro_byte_d[7:0] <= id_snum[7:0];
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112 end else if ( report_cnt == 5'd16) begin
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113 mesa_ro_byte_d[7:0] <= time_stamp_d[31:24];
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114 end else if ( report_cnt == 5'd17) begin
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115 mesa_ro_byte_d[7:0] <= time_stamp_d[23:16];
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116 end else if ( report_cnt == 5'd18) begin
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117 mesa_ro_byte_d[7:0] <= time_stamp_d[15:8];
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118 end else if ( report_cnt == 5'd19) begin
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119 mesa_ro_byte_d[7:0] <= time_stamp_d[7:0];
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120 mesa_ro_done <= 1;// Send LF
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121 report_jk <= 0;// All Done - stop FSM
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123 mesa_ro_byte_d[7:0] <= 8'h00;// 0x00 = NULL
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126 end // if ( report_jk == 1 ) begin
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128 end // proc_mesa_ro_byte
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130 //-----------------------------------------------------------------------------
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131 // 32bit UNIX TimeStamp of when the design was synthesized
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132 //-----------------------------------------------------------------------------
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133 time_stamp u_time_stamp
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135 .time_dout ( time_stamp_d[31:0] )
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139 endmodule // mesa_id.v
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projects / BML_sump2 / blob