--- /dev/null
+/* ****************************************************************************\r
+-- Source file: mesa_core.v \r
+-- Date: October 4, 2015 \r
+-- Author: khubbard\r
+-- Description: Wrapper around a bunch of Mesa Bus Modules. This takes in the\r
+-- binary nibble stream from mesa_phy and takes care of slot\r
+-- enumeration and subslot bus decoding to local-bus.\r
+-- SubSlot-0 is 32bit user localbus.\r
+-- SubSlot-E is 32bit SPI PROM Interface localbus.\r
+-- SubSlot-F is power management,etc.\r
+-- Language: Verilog-2001 and VHDL-1993\r
+-- Simulation: Mentor-Modelsim \r
+-- Synthesis: Xilinst-XST \r
+-- License: This project is licensed with the CERN Open Hardware Licence\r
+-- v1.2. You may redistribute and modify this project under the\r
+-- terms of the CERN OHL v.1.2. (http://ohwr.org/cernohl).\r
+-- This project is distributed WITHOUT ANY EXPRESS OR IMPLIED\r
+-- WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY\r
+-- AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN OHL\r
+-- v.1.2 for applicable Conditions.\r
+--\r
+-- Revision History:\r
+-- Ver# When Who What\r
+-- ---- -------- -------- ---------------------------------------------------\r
+-- 0.1 10.04.15 khubbard Creation\r
+-- ***************************************************************************/\r
+`default_nettype none // Strictly enforce all nets to be declared\r
+ \r
+module mesa_core #\r
+(\r
+ parameter spi_prom_en = 1\r
+)\r
+(\r
+ input wire clk, \r
+ input wire reset,\r
+ output wire lb_wr,\r
+ output wire lb_rd,\r
+ output wire [31:0] lb_addr,\r
+ output wire [31:0] lb_wr_d,\r
+ input wire [31:0] lb_rd_d,\r
+ input wire lb_rd_rdy,\r
+\r
+ output wire spi_sck,\r
+ output wire spi_cs_l,\r
+ output wire spi_mosi,\r
+ input wire spi_miso,\r
+ input wire [3:0] rx_in_d,\r
+ input wire rx_in_rdy,\r
+ output reg [7:0] tx_byte_d,\r
+ output reg tx_byte_rdy,\r
+ output reg tx_done,\r
+ input wire tx_busy,\r
+ output wire [7:0] tx_wo_byte,\r
+ output wire tx_wo_rdy,\r
+ input wire oob_en,\r
+ input wire oob_done,\r
+\r
+ output wire [8:0] subslot_ctrl,\r
+ output wire reconfig_req,\r
+ output wire [31:0] reconfig_addr,\r
+ output wire bist_req\r
+);// module mesa_core\r
+\r
+ wire rx_loc_rdy;\r
+ wire rx_loc_start;\r
+ wire rx_loc_stop;\r
+ wire [7:0] rx_loc_d;\r
+\r
+ wire [7:0] tx_spi_byte_d;\r
+ wire tx_spi_byte_rdy;\r
+ wire tx_spi_done;\r
+ wire [7:0] tx_lb_byte_d;\r
+ wire tx_lb_byte_rdy;\r
+ wire tx_lb_done;\r
+ wire tx_busy_loc;\r
+ reg [3:0] tx_busy_sr;\r
+\r
+ wire prom_wr;\r
+ wire prom_rd;\r
+ wire [31:0] prom_addr;\r
+ wire [31:0] prom_wr_d;\r
+ wire [31:0] prom_rd_d;\r
+ wire prom_rd_rdy;\r
+ reg prom_cs_c;\r
+ reg prom_cs_d;\r
+\r
+ wire [31:0] slot_size;\r
+ wire [31:0] time_stamp_d;\r
+\r
+\r
+//-----------------------------------------------------------------------------\r
+// Decode the 2 PROM Addresses at 0x20 and 0x24 using combo logic\r
+//-----------------------------------------------------------------------------\r
+always @ ( * ) begin : proc_prom_decode\r
+ begin\r
+ if ( prom_addr[15:0] == 16'h0020 ) begin\r
+ prom_cs_c <= prom_wr | prom_rd;\r
+ end else begin\r
+ prom_cs_c <= 0;\r
+ end \r
+ if ( prom_addr[15:0] == 16'h0024 ) begin\r
+ prom_cs_d <= prom_wr | prom_rd;\r
+ end else begin\r
+ prom_cs_d <= 0;\r
+ end \r
+ end\r
+end // proc_prom_decode\r
+\r
+\r
+// ----------------------------------------------------------------------------\r
+// Ro Mux : Mux between multiple byte sources for Ro readback path.\r
+// Note: There is no arbitration - 1st come 1st service requires that only\r
+// one device will send readback data ( polled requests ).\r
+// ----------------------------------------------------------------------------\r
+always @ ( posedge clk ) begin : proc_tx\r
+ tx_busy_sr[0] <= tx_lb_byte_rdy | tx_spi_byte_rdy | tx_busy;\r
+ tx_busy_sr[3:1] <= tx_busy_sr[2:0];\r
+ tx_byte_rdy <= tx_lb_byte_rdy | tx_spi_byte_rdy;\r
+ tx_done <= tx_lb_done | tx_spi_done | oob_done;// Sends LF\r
+\r
+ if ( tx_lb_byte_rdy == 1 ) begin\r
+ tx_byte_d <= tx_lb_byte_d[7:0];\r
+ end else begin\r
+ tx_byte_d <= tx_spi_byte_d[7:0];\r
+ end \r
+end // proc_tx\r
+ // Support pipeling Ro byte path by asserting busy for 4 clocks after a byte\r
+ assign tx_busy_loc = ( tx_busy_sr != 4'b0000 ) ? 1 : 0;\r
+\r
+\r
+//-----------------------------------------------------------------------------\r
+// Decode Slot Addresses : Take in the Wi path as nibbles and generate the Wo\r
+// paths for both internal and external devices.\r
+//-----------------------------------------------------------------------------\r
+mesa_decode u_mesa_decode\r
+(\r
+ .clk ( clk ),\r
+ .reset ( reset ),\r
+ .rx_in_d ( rx_in_d[3:0] ),\r
+ .rx_in_rdy ( rx_in_rdy ),\r
+ .rx_out_d ( tx_wo_byte[7:0] ),\r
+ .rx_out_rdy ( tx_wo_rdy ),\r
+ .rx_loc_d ( rx_loc_d[7:0] ),\r
+ .rx_loc_rdy ( rx_loc_rdy ),\r
+ .rx_loc_start ( rx_loc_start ),\r
+ .rx_loc_stop ( rx_loc_stop )\r
+);\r
+\r
+\r
+//-----------------------------------------------------------------------------\r
+// Convert Subslots 0x0 and 0xE to 32bit local bus for user logic and prom \r
+//-----------------------------------------------------------------------------\r
+mesa2lb u_mesa2lb\r
+(\r
+ .clk ( clk ),\r
+ .reset ( reset ),\r
+ .rx_byte_d ( rx_loc_d[7:0] ),\r
+ .rx_byte_rdy ( rx_loc_rdy ),\r
+ .rx_byte_start ( rx_loc_start ),\r
+ .rx_byte_stop ( rx_loc_stop ),\r
+ .tx_byte_d ( tx_lb_byte_d[7:0] ),\r
+ .tx_byte_rdy ( tx_lb_byte_rdy ),\r
+ .tx_done ( tx_lb_done ),\r
+ .tx_busy ( tx_busy_loc ),\r
+ .lb_wr ( lb_wr ),\r
+ .lb_rd ( lb_rd ),\r
+ .lb_wr_d ( lb_wr_d[31:0] ),\r
+ .lb_addr ( lb_addr[31:0] ),\r
+ .lb_rd_d ( lb_rd_d[31:0] ),\r
+ .lb_rd_rdy ( lb_rd_rdy ),\r
+ .oob_en ( oob_en ),\r
+ .oob_rd_d ( lb_rd_d[31:0] ),\r
+ .oob_rd_rdy ( lb_rd_rdy ),\r
+ .prom_wr ( prom_wr ),\r
+ .prom_rd ( prom_rd ),\r
+ .prom_wr_d ( prom_wr_d[31:0] ),\r
+ .prom_addr ( prom_addr[31:0] ),\r
+ .prom_rd_d ( prom_rd_d[31:0] ),\r
+ .prom_rd_rdy ( prom_rd_rdy )\r
+);\r
+\r
+\r
+//-----------------------------------------------------------------------------\r
+// Convert Subslots 0x1 to SPI\r
+// Use spi_ck_div of 0x7 for div-8 of 24 MHz to 3 MHz for SPI of 1.5 MHz.\r
+//-----------------------------------------------------------------------------\r
+//mesa2spi u_mesa2spi\r
+//(\r
+// .clk ( clk ),\r
+// .reset ( reset ),\r
+// .subslot ( 4'd1 ),\r
+// .spi_ck_div ( 4'd7 ),\r
+// .rx_byte_d ( rx_loc_d[7:0] ),\r
+// .rx_byte_rdy ( rx_loc_rdy ),\r
+// .rx_byte_start ( rx_loc_start ),\r
+// .rx_byte_stop ( rx_loc_stop ),\r
+//\r
+// .tx_byte_d ( tx_spi_byte_d[7:0] ),\r
+// .tx_byte_rdy ( tx_spi_byte_rdy ),\r
+// .tx_done ( tx_spi_done ),\r
+// .tx_busy ( tx_busy_loc ),\r
+// .spi_sck ( ),\r
+// .spi_ss_l ( ),\r
+// .spi_mosi ( ),\r
+// .spi_miso ( )\r
+//);\r
+ assign tx_spi_byte_d[7:0] = 8'd0;\r
+ assign tx_spi_byte_rdy = 1'b0;\r
+ assign tx_spi_done = 1'b0;\r
+\r
+\r
+//-----------------------------------------------------------------------------\r
+// Decode Subslot Nibble Controls\r
+//-----------------------------------------------------------------------------\r
+mesa2ctrl u_mesa2ctrl\r
+(\r
+ .clk ( clk ),\r
+ .reset ( reset ),\r
+ .rx_byte_d ( rx_loc_d[7:0] ),\r
+ .rx_byte_rdy ( rx_loc_rdy ),\r
+ .rx_byte_start ( rx_loc_start ),\r
+ .rx_byte_stop ( rx_loc_stop ),\r
+ .subslot_ctrl ( subslot_ctrl[8:0] )\r
+);\r
+\r
+\r
+//-----------------------------------------------------------------------------\r
+// 32bit UNIX TimeStamp of when the design was synthesized\r
+//-----------------------------------------------------------------------------\r
+time_stamp u_time_stamp\r
+(\r
+ .time_dout ( time_stamp_d )\r
+);\r
+\r
+\r
+//-----------------------------------------------------------------------------\r
+// Interface to SPI PROM : Allow LB to program SPI PROM, request reconfig\r
+// ck_divisor 10 is for ( 80M / 10 ) for 2x SPI Clock Rate of 4 MHz\r
+// ck_divisor 3 is for ( 24M / 3 ) for 2x SPI Clock Rate of 4 MHz\r
+// PROM Slot Size\r
+// slot_size 0x00020000 is 1Mbit Slot for ICE5LP4K\r
+// slot_size 0x00040000 is 2Mbit Slot for XC3S200A (Compressed, no BRAM ROMs)\r
+// slot_size 0x00080000 is 4Mbit Slot for XC6SLX9 (Compressed, no BRAM ROMs)\r
+//-----------------------------------------------------------------------------\r
+generate\r
+if ( spi_prom_en == 1 ) begin\r
+spi_prom u_spi_prom\r
+(\r
+ .reset ( reset ),\r
+ .prom_is_32b ( 1'b0 ),\r
+ .ck_divisor ( 8'd3 ),\r
+ .slot_size ( slot_size[31:0] ),\r
+ .protect_1st_slot ( 1'b1 ),\r
+ .clk_lb ( clk ),\r
+\r
+ .lb_cs_prom_c ( prom_cs_c ),\r
+ .lb_cs_prom_d ( prom_cs_d ),\r
+ .lb_wr ( prom_wr ),\r
+ .lb_rd ( prom_rd ),\r
+ .lb_wr_d ( prom_wr_d[31:0] ),\r
+ .lb_rd_d ( prom_rd_d[31:0] ),\r
+ .lb_rd_rdy ( prom_rd_rdy ),\r
+\r
+ .spi_ctrl ( 4'b0000 ),\r
+ .spi_sck ( spi_sck ),\r
+ .spi_cs_l ( spi_cs_l ),\r
+ .spi_mosi ( spi_mosi ),\r
+ .spi_miso ( spi_miso ),\r
+\r
+ .flag_wip ( ),\r
+ .bist_req ( bist_req ),\r
+ .reconfig_2nd_slot ( 1'b0 ),\r
+ .reconfig_req ( reconfig_req ),\r
+ .reconfig_addr ( reconfig_addr[31:0] )\r
+);// spi_prom\r
+end else begin\r
+ assign spi_sck = 1;\r
+ assign spi_cs_l = 1;\r
+ assign spi_mosi = 1;\r
+ assign bist_req = 0;\r
+ assign reconfig_req = 0;\r
+ assign reconfig_addr = 32'd0;\r
+ assign prom_rd_d = 32'd0;\r
+ assign prom_rd_rdy = 0;\r
+end\r
+endgenerate\r
+ assign slot_size = 32'h00020000;\r
+\r
+\r
+endmodule // mesa_core\r
projects / BML_sump2 / blobdiff