--- /dev/null
+/* ****************************************************************************\r
+-- Source file: mesa_id.v \r
+-- Date: October 2015 \r
+-- Author: khubbard\r
+-- Description: Simple state machine the reports chip ID over mesa-bus on \r
+-- request and muxes in the normal Ro byte path when idle.\r
+-- Language: Verilog-2001\r
+-- Simulation: Mentor-Modelsim \r
+-- Synthesis: Lattice \r
+-- License: This project is licensed with the CERN Open Hardware Licence\r
+-- v1.2. You may redistribute and modify this project under the\r
+-- terms of the CERN OHL v.1.2. (http://ohwr.org/cernohl).\r
+-- This project is distributed WITHOUT ANY EXPRESS OR IMPLIED\r
+-- WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY\r
+-- AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN OHL\r
+-- v.1.2 for applicable Conditions.\r
+--\r
+-- Revision History:\r
+-- Ver# When Who What\r
+-- ---- -------- -------- ---------------------------------------------------\r
+-- 0.1 10.04.15 khubbard Creation\r
+-- ***************************************************************************/\r
+`default_nettype none // Strictly enforce all nets to be declared\r
+\r
+module mesa_id\r
+(\r
+ input wire clk,\r
+ input wire reset,\r
+ input wire report_id,\r
+ input wire [31:0] id_mfr,\r
+ input wire [31:0] id_dev,\r
+ input wire [31:0] id_snum,\r
+ input wire [7:0] mesa_core_ro_byte_d,\r
+ input wire mesa_core_ro_byte_en,\r
+ input wire mesa_core_ro_done,\r
+ input wire mesa_ro_busy,\r
+ output reg [7:0] mesa_ro_byte_d,\r
+ output reg mesa_ro_byte_en,\r
+ output reg mesa_ro_done\r
+);// module mesa_id\r
+\r
+ reg report_jk;\r
+ reg report_id_p1;\r
+ reg [4:0] report_cnt;\r
+ reg mesa_ro_busy_p1;\r
+ wire [31:0] time_stamp_d;\r
+\r
+\r
+//-----------------------------------------------------------------------------\r
+// Ro binary bytes are converted to 2 ASCII nibble chars for MesaBus Ro\r
+// This is also a report_id FSM that muxes into the ro byte path on request.\r
+//-----------------------------------------------------------------------------\r
+always @ ( posedge clk ) begin : proc_mesa_ro_byte\r
+ report_id_p1 <= report_id;\r
+ mesa_ro_byte_d[7:0] <= mesa_core_ro_byte_d[7:0];\r
+ mesa_ro_byte_en <= mesa_core_ro_byte_en;\r
+ mesa_ro_done <= mesa_core_ro_done;\r
+ mesa_ro_busy_p1 <= mesa_ro_busy;\r
+\r
+ // When report_id asserts ( SubSlot 0xFA command ) shift out\r
+ // a unique 32bit ID of 16 bit Manufacture and 16bit Device\r
+ if ( report_id == 1 ) begin\r
+ report_jk <= 1;// Start FSM\r
+ report_cnt <= 5'd0;\r
+ end\r
+\r
+ // State Machine for sending out device id when requested\r
+ mesa_ro_busy_p1 <= mesa_ro_busy;\r
+ if ( report_jk == 1 ) begin\r
+ mesa_ro_byte_en <= 0;\r
+ mesa_ro_done <= 0;\r
+ \r
+ if ( report_id_p1==1 || ( mesa_ro_busy_p1==1 && mesa_ro_busy==0 )) begin\r
+ report_cnt <= report_cnt[4:0] + 1;\r
+ mesa_ro_byte_en <= 1;\r
+ if ( report_cnt == 5'd0 ) begin\r
+ mesa_ro_byte_d[7:0] <= 8'hF0;// Header : Preamble\r
+ end else if ( report_cnt == 5'd1 ) begin\r
+ mesa_ro_byte_d[7:0] <= 8'hFE;// Header : Ro Slot is 0xFE\r
+ end else if ( report_cnt == 5'd2 ) begin\r
+ mesa_ro_byte_d[7:0] <= 8'h00;// Header : Ro Subslot is 0x00\r
+ end else if ( report_cnt == 5'd3 ) begin\r
+ mesa_ro_byte_d[7:0] <= 8'h10;// Header : 16 Bytes in Payload\r
+\r
+ end else if ( report_cnt == 5'd4 ) begin\r
+ mesa_ro_byte_d[7:0] <= id_mfr[31:24];\r
+ end else if ( report_cnt == 5'd5 ) begin\r
+ mesa_ro_byte_d[7:0] <= id_mfr[23:16];\r
+ end else if ( report_cnt == 5'd6 ) begin\r
+ mesa_ro_byte_d[7:0] <= id_mfr[15:8];\r
+ end else if ( report_cnt == 5'd7 ) begin\r
+ mesa_ro_byte_d[7:0] <= id_mfr[7:0];\r
+\r
+ end else if ( report_cnt == 5'd8 ) begin\r
+ mesa_ro_byte_d[7:0] <= id_dev[31:24];\r
+ end else if ( report_cnt == 5'd9 ) begin\r
+ mesa_ro_byte_d[7:0] <= id_dev[23:16];\r
+ end else if ( report_cnt == 5'd10) begin\r
+ mesa_ro_byte_d[7:0] <= id_dev[15:8];\r
+ end else if ( report_cnt == 5'd11) begin\r
+ mesa_ro_byte_d[7:0] <= id_dev[7:0];\r
+\r
+ end else if ( report_cnt == 5'd12) begin\r
+ mesa_ro_byte_d[7:0] <= id_snum[31:24];\r
+ end else if ( report_cnt == 5'd13) begin\r
+ mesa_ro_byte_d[7:0] <= id_snum[23:16];\r
+ end else if ( report_cnt == 5'd14) begin\r
+ mesa_ro_byte_d[7:0] <= id_snum[15:8];\r
+ end else if ( report_cnt == 5'd15) begin\r
+ mesa_ro_byte_d[7:0] <= id_snum[7:0];\r
+\r
+ end else if ( report_cnt == 5'd16) begin\r
+ mesa_ro_byte_d[7:0] <= time_stamp_d[31:24];\r
+ end else if ( report_cnt == 5'd17) begin\r
+ mesa_ro_byte_d[7:0] <= time_stamp_d[23:16];\r
+ end else if ( report_cnt == 5'd18) begin\r
+ mesa_ro_byte_d[7:0] <= time_stamp_d[15:8];\r
+ end else if ( report_cnt == 5'd19) begin\r
+ mesa_ro_byte_d[7:0] <= time_stamp_d[7:0];\r
+ mesa_ro_done <= 1;// Send LF\r
+ report_jk <= 0;// All Done - stop FSM\r
+ end else begin\r
+ mesa_ro_byte_d[7:0] <= 8'h00;// 0x00 = NULL\r
+ end\r
+ end\r
+ end // if ( report_jk == 1 ) begin\r
+\r
+end // proc_mesa_ro_byte\r
+\r
+//-----------------------------------------------------------------------------\r
+// 32bit UNIX TimeStamp of when the design was synthesized\r
+//-----------------------------------------------------------------------------\r
+time_stamp u_time_stamp\r
+(\r
+ .time_dout ( time_stamp_d[31:0] )\r
+);\r
+\r
+\r
+endmodule // mesa_id.v\r
projects / BML_sump2 / blobdiff