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fix based on https://gist.github.com/timbrom/1942280
[DSO138]
/
Libraries
/
CMSIS
/
CM3
/
CoreSupport
/
core_cm3.c
diff --git
a/Libraries/CMSIS/CM3/CoreSupport/core_cm3.c
b/Libraries/CMSIS/CM3/CoreSupport/core_cm3.c
index
56fddc5
..
0e8c3c4
100644
(file)
--- a/
Libraries/CMSIS/CM3/CoreSupport/core_cm3.c
+++ b/
Libraries/CMSIS/CM3/CoreSupport/core_cm3.c
@@
-733,7
+733,7
@@
uint32_t __STREXB(uint8_t value, uint8_t *addr)
{
\r
uint32_t result=0;
\r
\r
{
\r
uint32_t result=0;
\r
\r
- __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
\r
+ __ASM volatile ("strexb %0, %2, [%1]" : "=
&
r" (result) : "r" (addr), "r" (value) );
\r
return(result);
\r
}
\r
\r
return(result);
\r
}
\r
\r
@@
-750,7
+750,7
@@
uint32_t __STREXH(uint16_t value, uint16_t *addr)
{
\r
uint32_t result=0;
\r
\r
{
\r
uint32_t result=0;
\r
\r
- __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
\r
+ __ASM volatile ("strexh %0, %2, [%1]" : "=
&
r" (result) : "r" (addr), "r" (value) );
\r
return(result);
\r
}
\r
\r
return(result);
\r
}
\r
\r