www.usr.com/support/gpl/USR9107_release.1.4.tar.gz

[bcm963xx.git] / bcmdrivers / opensource / include / bcm963xx / 6345_map_part.h

diff --git a/bcmdrivers/opensource/include/bcm963xx/6345_map_part.h b/bcmdrivers/opensource/include/bcm963xx/6345_map_part.h
index 4da2358..2a18859 100755 (executable)
--- a/bcmdrivers/opensource/include/bcm963xx/6345_map_part.h
+++ b/bcmdrivers/opensource/include/bcm963xx/6345_map_part.h
@@ -31,7 +31,10 @@ typedef struct IntControl {
   uint32        RevID;
   uint16        testControl;
   uint16        blkEnables;
+#define USB_CLK_EN      0x0100
+#define EMAC_CLK_EN     0x0080
 #define UART_CLK_EN     0x0008
+#define CPU_CLK_EN      0x0001
 
   uint32        pll_control;
 #define SOFT_RESET     0x00000001
@@ -51,6 +54,40 @@ typedef struct IntControl {
 #define INTC_BASE     0xfffe0000
 #define PERF ((volatile IntControl * const) INTC_BASE)
 
+#define TIMR_BASE     0xfffe0200    
+typedef struct Timer {
+  uint16        unused0;
+  byte          TimerMask;
+#define TIMER0EN        0x01
+#define TIMER1EN        0x02
+#define TIMER2EN        0x04
+  byte          TimerInts;
+#define TIMER0          0x01
+#define TIMER1          0x02
+#define TIMER2          0x04
+#define WATCHDOG        0x08
+  uint32        TimerCtl0;
+  uint32        TimerCtl1;
+  uint32        TimerCtl2;
+#define TIMERENABLE     0x80000000
+#define RSTCNTCLR       0x40000000      
+  uint32        TimerCnt0;
+  uint32        TimerCnt1;
+  uint32        TimerCnt2;
+  uint32        WatchDogDefCount;
+
+  /* Write 0xff00 0x00ff to Start timer
+   * Write 0xee00 0x00ee to Stop and re-load default count
+   * Read from this register returns current watch dog count
+   */
+  uint32        WatchDogCtl;
+
+  /* Number of 40-MHz ticks for WD Reset pulse to last */
+  uint32        WDResetCount;
+} Timer;
+
+#define TIMER ((volatile Timer * const) TIMR_BASE)
+
 typedef struct UartChannel {
   byte          unused0;
   byte          control;