+ // set the CPU clock to 48MHz, enable clock output to FPGA\r
+ CPUCS = bmCLKOE | bmCLKSPD1;\r
+\r
+ // put the system in FIFO mode by default\r
+ // internal clock source at 48Mhz, drive output pin, synchronous mode\r
+ // NOTE: Altera USB-Blaster does not work in another mode\r
+ IFCONFIG = bmIFCLKSRC | bm3048MHZ | bmIFCLKOE;\r
+ IFCONFIG |= bmASYNC | bmIFCFG1 | bmIFCFG0;\r
+\r