2 \author Travis Goodspeed
3 \brief Chipcon 8051 debugging.
7 //This is like SPI, except that you read or write, not both.
9 /* N.B. The READ verb performs a write of all (any) supplied data,
10 then reads a single byte reply from the target. The WRITE verb
18 //! Handles a chipcon command.
19 void cc_handle_fn( uint8_t const app,
23 // define the jtag app's app_t
24 app_t const chipcon_app = {
36 "\tThe CHIPCON app adds support for debugging the chipcon\n"
40 /* Concerning clock rates, the maximimum clock rates are defined on
41 page 4 of the spec. They vary, but are roughly 30MHz. Raising
42 this clock rate might allow for clock glitching, but the GoodFET
43 isn't sufficient fast for that. Perhaps a 200MHz ARM or an FPGA in
48 //MISO and MOSI are the same pin, direction changes.
50 #if (platform == tilaunchpad)
52 * The Launchpad has only pins easily available
53 * P5.3 TCK SCK (labeled TEST J3-10 J2-17) DC closest to antenna (blue)
54 * P5.2 IO MISO MOSI (labeled RST J3-8 J2-16) DD next to closer to USB (yellow)
55 * P3.6 txd1 RST (labeled RXD J3-6 J1-4) next to GND, which is closest to USB (orange)
56 * P3.7 rxd1 RST (labeled TXD J3-4 J1-3) connect to led1 J1-2
58 * for a permanent marriage between a TI-Launchpad, move RST to pin48 P5.4
59 * (requeries soldering) and use rxd/txd for direct communication with IM-ME dongle.
62 #define RST BIT6 // P3.7
63 #include <msp430_serial.h>
67 #endif // ! tilaunchad
74 //This could be more accurate.
75 //Does it ever need to be?
78 //#define CCDELAY(x) delay(x)
81 #define SETMOSI SPIOUT|=MOSI
82 #define CLRMOSI SPIOUT&=~MOSI
83 #define SETCLK SPIOUT|=SCK
84 #define CLRCLK SPIOUT&=~SCK
85 #define READMISO (SPIIN&MISO?1:0)
87 #if (platform == tilaunchpad)
88 # if (SPIDIR != P5DIR)
89 # error "SPIDIR != P5DIR"
91 # if (SPIOUT != P5OUT)
92 # error "SPIOUT != P5OUT"
94 # define SETRST P3OUT|=RST
95 # define CLRRST P3OUT&=~RST
97 # define SETRST P3OUT|=RST
98 # define CLRRST P3OUT&=~RST
101 #define CCWRITE SPIDIR|=MOSI
102 #define CCREAD SPIDIR&=~MISO
104 //! Set up the pins for CC mode. Does not init debugger.
106 #if (platform == tilaunchpad)
112 dputs("done ccsetup");
114 SPIOUT|=MOSI+SCK+RST;
115 SPIDIR|=MOSI+SCK+RST;
121 /* 33 cycle critical region
122 0000000e <ccdebuginit>:
123 e: f2 d0 0d 00 bis.b #13, &0x0031 ;5 cycles
125 14: f2 c2 31 00 bic.b #8, &0x0031 ;4 cycles
126 18: d2 c3 31 00 bic.b #1, &0x0031 ;4
127 1c: f2 e2 31 00 xor.b #8, &0x0031 ;4
128 20: f2 e2 31 00 xor.b #8, &0x0031 ;4
129 24: f2 e2 31 00 xor.b #8, &0x0031 ;4
130 28: f2 e2 31 00 xor.b #8, &0x0031 ;4
131 2c: d2 d3 31 00 bis.b #1, &0x0031 ;4
136 //! Initialize the debugger
138 //Port output BUT NOT DIRECTION is set at start.
139 #if (platform == tilaunchpad)
140 dputs("ccdebuginit");
144 SPIOUT|=MOSI+SCK+RST;
147 delay(30); //So the beginning is ready for glitching.
149 //Two positive debug clock pulses while !RST is low.
150 //Take RST low, pulse twice, then high.
164 SPIOUT^=SCK; //Unnecessary.
172 //! Read and write a CC bit.
173 unsigned char cctrans8(unsigned char byte){
175 //This function came from the SPI Wikipedia article.
178 for (bit = 0; bit < 8; bit++) {
179 /* write MOSI on trailing edge of previous clock */
186 /* half a clock cycle before leading/rising edge */
190 /* half a clock cycle before trailing/falling edge */
193 /* read MISO on trailing edge */
201 //! Send a command from txbytes.
202 void cccmd(unsigned char len){
206 cctrans8(cmddata[i]);
209 //! Fetch a reply, usually 1 byte.
210 void ccread(unsigned char len){
214 cmddata[i]=cctrans8(0);
217 //! Handles a chipcon command.
218 void cc_handle_fn( uint8_t const app,
222 //Always init. Might help with buggy lines.
226 int blocklen, blockadr;
229 //CC_PEEK and CC_POKE will come later.
231 cmddata[0]=cc_peekirambyte(cmddata[0]);
235 cmddata[0]=cc_pokeirambyte(cmddata[0],cmddata[1]);
238 case READ: //Write a command and return 1-byte reply.
244 case WRITE: //Write a command with no reply.
248 case START://enter debugger
252 case STOP://exit debugger
253 //Take RST low, then high.
266 case CC_MASS_ERASE_FLASH:
271 cc_wr_config(cmddata[0]);
284 //no break, return status
289 case CC_SET_HW_BRKPNT:
290 cc_set_hw_brkpnt(cmddataword[0]);
309 case CC_STEP_REPLACE:
310 txdata(app,NOK,0);//Don't add this; it's non-standard.
313 cmddataword[0]=cc_get_chip_id();
319 case CC_READ_CODE_MEMORY:
320 cmddata[0]=cc_peekcodebyte(cmddataword[0]);
323 case CC_READ_XDATA_MEMORY:
327 blocklen=cmddataword[1];
328 blockadr=cmddataword[0];
330 //Return that many bytes.
331 for(i=0;i<blocklen;i++)
332 cmddata[i]=cc_peekdatabyte(blockadr+i);
333 txdata(app,verb,blocklen);
336 case CC_WRITE_XDATA_MEMORY:
337 cmddata[0]=cc_pokedatabyte(cmddataword[0], cmddata[2]);
341 cc_set_pc(cmddatalong[0]);
344 case CC_WRITE_FLASH_PAGE:
345 cc_write_flash_page(cmddatalong[0]);
348 case CC_WIPEFLASHBUFFER:
349 for(i=0xf000;i<0xf800;i++)
350 cc_pokedatabyte(i,0xFF);
355 case CC_PROGRAM_FLASH:
357 debugstr("This Chipcon command is not yet implemented.");
358 txdata(app,NOK,0);//TODO implement me.
363 //! Set the Chipcon's Program Counter
364 void cc_set_pc(u32 adr){
365 cmddata[0]=0x02; //SetPC
366 cmddata[1]=((adr>>8)&0xff); //HIBYTE
367 cmddata[2]=adr&0xff; //LOBYTE
372 //! Erase all of a Chipcon's memory.
373 void cc_chip_erase(){
374 cmddata[0]=CCCMD_CHIP_ERASE; //0x14
378 //! Write the configuration byte.
379 void cc_wr_config(unsigned char config){
380 cmddata[0]=CCCMD_WR_CONFIG; //0x1D
390 //debugstr("Locking chip.");
391 cc_wr_config(1);//Select Info Flash
392 if(!(cc_rd_config()&1))
393 debugstr("Config forgotten!");
397 cc_pokedatabyte(0xf000+i,0);
398 cc_write_flash_page(0);
399 if(cc_peekcodebyte(0))
400 debugstr("Failed to clear info flash byte.");
404 debugstr("Stuck in info flash mode!");
407 //! Read the configuration byte.
408 unsigned char cc_rd_config(){
409 cmddata[0]=CCCMD_RD_CONFIG; //0x24
416 //! Read the status register
417 unsigned char cc_read_status(){
418 cmddata[0]=CCCMD_READ_STATUS; //0x3f
424 //! Read the CHIP ID bytes.
425 unsigned short cc_get_chip_id(){
426 cmddata[0]=CCCMD_GET_CHIP_ID; //0x68
431 //Find the flash word size.
437 //debugstr("2 bytes/flash word");
438 flash_word_size=0x02;
441 //debugstr("Warning: Guessing flash word size.");
446 //debugstr("4 bytes/flash word");
447 flash_word_size=0x04;
452 return cmddataword[0];
455 //! Populates flash buffer in xdata.
456 void cc_write_flash_buffer(u8 *data, u16 len){
457 cc_write_xdata(0xf000, data, len);
459 //! Populates flash buffer in xdata.
460 void cc_write_xdata(u16 adr, u8 *data, u16 len){
462 for(i=0; i<len; i++){
463 cc_pokedatabyte(adr+i,
469 //32-bit words, 2KB pages
470 //0x20 0x00 for CC2430, CC1110
471 #define HIBYTE_WORDS_PER_FLASH_PAGE 0x02
472 #define LOBYTE_WORDS_PER_FLASH_PAGE 0x00
474 /** Ugh, this varies by chip.
478 //#define FLASHPAGE_SIZE 0x400
479 #define MAXFLASHPAGE_SIZE 0x800
480 #define MINFLASHPAGE_SIZE 0x400
483 //32 bit words on CC2430
484 //16 bit words on CC1110
485 //#define FLASH_WORD_SIZE 0x2
486 u8 flash_word_size = 0; //0x02;
489 /* Flash Write Timing
496 32 | 0x2A (Modula.si)
500 const u8 flash_routine[] = {
504 0x00,//#imm=((address >> 8) / FLASH_WORD_SIZE) & 0x7E,
506 //0x75, 0xAB, 0x23, //Set FWT per clock
507 0x75, 0xAC, 0x00, // MOV FADDRL, #00;
509 0x75, 0xAE, 0x01, // MOV FLC, #01H; // ERASE
510 // ; Wait for flash erase to complete
511 0xE5, 0xAE, // eraseWaitLoop: MOV A, FLC;
512 0x20, 0xE7, 0xFB, // JB ACC_BUSY, eraseWaitLoop;
514 /* End erase page. */
515 // ; Initialize the data pointer
516 0x90, 0xF0, 0x00, // MOV DPTR, #0F000H;
518 0x7F, HIBYTE_WORDS_PER_FLASH_PAGE, // MOV R7, #imm;
519 0x7E, LOBYTE_WORDS_PER_FLASH_PAGE, // MOV R6, #imm;
520 0x75, 0xAE, 0x02, // MOV FLC, #02H; // WRITE
523 0x7D, 0xde /*FLASH_WORD_SIZE*/, // writeLoop: MOV R5, #imm;
524 0xE0, // writeWordLoop: MOVX A, @DPTR;
526 0xF5, 0xAF, // MOV FWDATA, A;
527 0xDD, 0xFA, // DJNZ R5, writeWordLoop;
528 // ; Wait for completion
529 0xE5, 0xAE, // writeWaitLoop: MOV A, FLC;
530 0x20, 0xE6, 0xFB, // JB ACC_SWBSY, writeWaitLoop;
531 0xDE, 0xF1, // DJNZ R6, writeLoop;
532 0xDF, 0xEF, // DJNZ R7, writeLoop;
533 // ; Done, fake a breakpoint
538 //! Copies flash buffer to flash.
539 void cc_write_flash_page(u32 adr){
540 //Assumes that page has already been written to XDATA 0xF000
541 //debugstr("Flashing 2kb at 0xF000 to given adr.");
543 if(adr&(MINFLASHPAGE_SIZE-1)){
544 debugstr("Flash page address is not on a page boundary. Aborting.");
548 if(flash_word_size!=2 && flash_word_size!=4){
549 debugstr("Flash word size is wrong, aborting write to");
555 //WRITE_XDATA_MEMORY(IN: 0xF000 + FLASH_PAGE_SIZE, sizeof(routine), routine);
556 cc_write_xdata(0xF000+MAXFLASHPAGE_SIZE,
557 (u8*) flash_routine, sizeof(flash_routine));
558 //Patch routine's third byte with
559 //((address >> 8) / FLASH_WORD_SIZE) & 0x7E
560 cc_pokedatabyte(0xF000+MAXFLASHPAGE_SIZE+2,
561 ((adr>>8)/flash_word_size)&0x7E);
562 //Patch routine to define FLASH_WORD_SIZE
563 if(flash_routine[25]!=0xde)
564 debugstr("Ugly patching code failing in chipcon.c");
565 cc_pokedatabyte(0xF000+MAXFLASHPAGE_SIZE+25,
568 //debugstr("Wrote flash routine.");
570 //MOV MEMCTR, (bank * 16) + 1;
575 //debugstr("Loaded bank info.");
577 cc_set_pc(0xf000+MAXFLASHPAGE_SIZE);//execute code fragment
580 //debugstr("Executing.");
583 while(!(cc_read_status()&CC_STATUS_CPUHALTED)){
584 led_toggle();//blink LED while flashing
588 //debugstr("Done flashing.");
594 unsigned short cc_get_pc(){
595 cmddata[0]=CCCMD_GET_PC; //0x28
600 return cmddataword[0];
603 //! Set a hardware breakpoint.
604 void cc_set_hw_brkpnt(unsigned short adr){
605 debugstr("FIXME: This certainly won't work.");
615 cmddata[0]=CCCMD_HALT; //0x44
622 cmddata[0]=CCCMD_RESUME; //0x4C
629 //! Step an instruction
630 void cc_step_instr(){
631 cmddata[0]=CCCMD_STEP_INSTR; //0x5C
637 //! Debug an instruction.
638 void cc_debug_instr(unsigned char len){
639 //Bottom two bits of command indicate length.
640 unsigned char cmd=CCCMD_DEBUG_INSTR+(len&0x3); //0x54+len
642 cctrans8(cmd); //Second command code
643 cccmd(len&0x3); //Command itself.
648 //! Debug an instruction, for local use.
649 unsigned char cc_debug(unsigned char len,
653 unsigned char cmd=CCCMD_DEBUG_INSTR+(len&0x3);//0x54+len
663 return cctrans8(0x00);
666 //! Fetch a byte of code memory.
667 unsigned char cc_peekcodebyte(unsigned long adr){
668 /** See page 9 of SWRA124 */
669 unsigned char bank=adr>>15,
675 //MOV MEMCTR, (bank*16)+1
676 cc_debug(3, 0x75, 0xC7, (bank<<4) + 1);
678 cc_debug(3, 0x90, hb, lb);
682 cc_debug(2, 0xE4, 0, 0);
684 toret=cc_debug(3, 0x93, 0, 0);
686 //cc_debug(1, 0xA3, 0, 0);
692 //! Set a byte of data memory.
693 unsigned char cc_pokedatabyte(unsigned int adr,
700 cc_debug(3, 0x90, hb, lb);
702 cc_debug(2, 0x74, val, 0);
704 cc_debug(1, 0xF0, 0, 0);
708 DEBUG_INSTR(IN: 0x90, HIBYTE(address), LOBYTE(address), OUT: Discard);
709 for (n = 0; n < count; n++) {
710 DEBUG_INSTR(IN: 0x74, inputArray[n], OUT: Discard);
711 DEBUG_INSTR(IN: 0xF0, OUT: Discard);
712 DEBUG_INSTR(IN: 0xA3, OUT: Discard);
717 //! Fetch a byte of data memory.
718 unsigned char cc_peekdatabyte(unsigned int adr){
724 cc_debug(3, 0x90, hb, lb);
726 //Must be 2, perhaps for clocking?
727 return cc_debug(3, 0xE0, 0, 0);
731 //! Fetch a byte of IRAM.
732 u8 cc_peekirambyte(u8 adr){
734 cc_debug(2, 0xE4, 0, 0);
736 return cc_debug(3, 0xE5, adr, 0);
739 //! Write a byte of IRAM.
740 u8 cc_pokeirambyte(u8 adr, u8 val){
742 cc_debug(2, 0xE4, 0, 0);
744 return cc_debug(3, 0x75, adr, val);
745 //return cc_debug(3, 0x75, val, adr);