2 \author Travis Goodspeed
3 \brief Chipcon 8051 debugging.
7 //This is like SPI, except that you read or write, not both.
9 /* N.B. The READ verb performs a write of all (any) supplied data,
10 then reads a single byte reply from the target. The WRITE verb
18 //! Handles a chipcon command.
19 void cc_handle_fn( uint8_t const app,
23 // define the jtag app's app_t
24 app_t const chipcon_app = {
36 "\tThe CHIPCON app adds support for debugging the chipcon\n"
40 /* Concerning clock rates, the maximimum clock rates are defined on
41 page 4 of the spec. They vary, but are roughly 30MHz. Raising
42 this clock rate might allow for clock glitching, but the GoodFET
43 isn't sufficient fast for that. Perhaps a 200MHz ARM or an FPGA in
48 //MISO and MOSI are the same pin, direction changes.
50 #if (platform == tilaunchpad)
52 * The Launchpad has only pins easily available
53 * P5.3 TCK SCK (labeled TEST J3-10 J2-17) DC closest to antenna (blue)
54 * P5.2 IO MISO MOSI (labeled RST J3-8 J2-16) DD next to closer to USB (yellow)
55 * P3.6 txd1 RST (labeled RXD J3-6 J1-4) next to GND, which is closest to USB (orange)
56 * P3.7 rxd1 RST (labeled TXD J3-4 J1-3) connect to led1 J1-2
58 * for a permanent marriage between a TI-Launchpad, move RST to pin48 P5.4
59 * (requeries soldering) and use rxd/txd for direct communication with IM-ME dongle.
62 #define RST BIT6 // P3.7
63 #include <msp430_serial.h>
68 #define RST BIT0 // P5.0
77 //This could be more accurate.
78 //Does it ever need to be?
81 //#define CCDELAY(x) delay_ms(x)
84 #define SETMOSI SPIOUT|=MOSI
85 #define CLRMOSI SPIOUT&=~MOSI
86 #define SETCLK SPIOUT|=SCK
87 #define CLRCLK SPIOUT&=~SCK
88 #define READMISO (SPIIN&MISO?1:0)
90 #if (platform == tilaunchpad)
91 # if (SPIDIR != P5DIR)
92 # error "SPIDIR != P5DIR"
94 # if (SPIOUT != P5OUT)
95 # error "SPIOUT != P5OUT"
97 # define SETRST P3OUT|=RST
98 # define CLRRST P3OUT&=~RST
100 # define SETRST P5OUT|=RST
101 # define CLRRST P5OUT&=~RST
104 #define CCWRITE SPIDIR|=MOSI
105 #define CCREAD SPIDIR&=~MISO
107 //! Set up the pins for CC mode. Does not init debugger.
109 #if (platform == tilaunchpad)
115 dputs("done ccsetup");
117 SPIOUT|=MOSI+SCK+RST;
118 SPIDIR|=MOSI+SCK+RST;
124 /* 33 cycle critical region
125 0000000e <ccdebuginit>:
126 e: f2 d0 0d 00 bis.b #13, &0x0031 ;5 cycles
128 14: f2 c2 31 00 bic.b #8, &0x0031 ;4 cycles
129 18: d2 c3 31 00 bic.b #1, &0x0031 ;4
130 1c: f2 e2 31 00 xor.b #8, &0x0031 ;4
131 20: f2 e2 31 00 xor.b #8, &0x0031 ;4
132 24: f2 e2 31 00 xor.b #8, &0x0031 ;4
133 28: f2 e2 31 00 xor.b #8, &0x0031 ;4
134 2c: d2 d3 31 00 bis.b #1, &0x0031 ;4
139 //! Initialize the debugger
141 //Port output BUT NOT DIRECTION is set at start.
142 #if (platform == tilaunchpad)
143 dputs("ccdebuginit");
147 SPIOUT|=MOSI+SCK+RST;
150 delay(30); //So the beginning is ready for glitching.
152 //Two positive debug clock pulses while !RST is low.
153 //Take RST low, pulse twice, then high.
167 SPIOUT^=SCK; //Unnecessary.
175 //! Read and write a CC bit.
176 unsigned char cctrans8(unsigned char byte){
178 //This function came from the SPI Wikipedia article.
181 for (bit = 0; bit < 8; bit++) {
183 /* write MOSI on trailing edge of previous clock */
190 /* half a clock cycle before leading/rising edge */
194 /* half a clock cycle before trailing/falling edge */
197 /* read MISO on trailing edge */
205 //! Send a command from txbytes.
206 void cccmd(unsigned char len){
210 cctrans8(cmddata[i]);
213 //! Fetch a reply, usually 1 byte.
214 void ccread(unsigned char len){
218 cmddata[i]=cctrans8(0);
221 //! Handles a chipcon command.
222 void cc_handle_fn( uint8_t const app,
226 //Always init. Might help with buggy lines.
230 int blocklen, blockadr;
233 //CC_PEEK and CC_POKE will come later.
235 cmddata[0]=cc_peekirambyte(cmddata[0]);
239 cmddata[0]=cc_pokeirambyte(cmddata[0],cmddata[1]);
242 case READ: //Write a command and return 1-byte reply.
248 case WRITE: //Write a command with no reply.
252 case START://enter debugger
256 case STOP://exit debugger
257 //Take RST low, then high.
270 case CC_MASS_ERASE_FLASH:
275 cc_wr_config(cmddata[0]);
288 //no break, return status
293 case CC_SET_HW_BRKPNT:
294 cc_set_hw_brkpnt(cmddataword[0]);
313 case CC_STEP_REPLACE:
314 txdata(app,NOK,0);//Don't add this; it's non-standard.
317 cmddataword[0]=cc_get_chip_id();
323 case CC_READ_CODE_MEMORY:
324 cmddata[0]=cc_peekcodebyte(cmddataword[0]);
327 case CC_READ_XDATA_MEMORY:
331 blocklen=cmddataword[1];
332 blockadr=cmddataword[0];
334 //Return that many bytes.
335 for(i=0;i<blocklen;i++)
336 cmddata[i]=cc_peekdatabyte(blockadr+i);
337 txdata(app,verb,blocklen);
340 case CC_WRITE_XDATA_MEMORY:
341 cmddata[0]=cc_pokedatabyte(cmddataword[0], cmddata[2]);
345 cc_set_pc(cmddatalong[0]);
348 case CC_WRITE_FLASH_PAGE:
349 cc_write_flash_page(cmddatalong[0]);
352 case CC_WIPEFLASHBUFFER:
353 for(i=0xf000;i<0xf800;i++)
354 cc_pokedatabyte(i,0xFF);
359 case CC_PROGRAM_FLASH:
361 debugstr("This Chipcon command is not yet implemented.");
362 txdata(app,NOK,0);//TODO implement me.
367 //! Set the Chipcon's Program Counter
368 void cc_set_pc(u32 adr){
369 cmddata[0]=0x02; //SetPC
370 cmddata[1]=((adr>>8)&0xff); //HIBYTE
371 cmddata[2]=adr&0xff; //LOBYTE
376 //! Erase all of a Chipcon's memory.
377 void cc_chip_erase(){
378 cmddata[0]=CCCMD_CHIP_ERASE; //0x14
382 //! Write the configuration byte.
383 void cc_wr_config(unsigned char config){
384 cmddata[0]=CCCMD_WR_CONFIG; //0x1D
394 //debugstr("Locking chip.");
395 cc_wr_config(1);//Select Info Flash
396 if(!(cc_rd_config()&1))
397 debugstr("Config forgotten!");
401 cc_pokedatabyte(0xf000+i,0);
402 cc_write_flash_page(0);
403 if(cc_peekcodebyte(0))
404 debugstr("Failed to clear info flash byte.");
408 debugstr("Stuck in info flash mode!");
411 //! Read the configuration byte.
412 unsigned char cc_rd_config(){
413 cmddata[0]=CCCMD_RD_CONFIG; //0x24
420 //! Read the status register
421 unsigned char cc_read_status(){
422 cmddata[0]=CCCMD_READ_STATUS; //0x3f
428 //! Read the CHIP ID bytes.
429 unsigned short cc_get_chip_id(){
430 cmddata[0]=CCCMD_GET_CHIP_ID; //0x68
435 //Find the flash word size.
441 //debugstr("2 bytes/flash word");
442 flash_word_size=0x02;
445 //debugstr("Warning: Guessing flash word size.");
450 //debugstr("4 bytes/flash word");
451 flash_word_size=0x04;
456 return cmddataword[0];
459 //! Populates flash buffer in xdata.
460 void cc_write_flash_buffer(u8 *data, u16 len){
461 cc_write_xdata(0xf000, data, len);
463 //! Populates flash buffer in xdata.
464 void cc_write_xdata(u16 adr, u8 *data, u16 len){
466 for(i=0; i<len; i++){
467 cc_pokedatabyte(adr+i,
473 //32-bit words, 2KB pages
474 //0x20 0x00 for CC2430, CC1110
475 #define HIBYTE_WORDS_PER_FLASH_PAGE 0x02
476 #define LOBYTE_WORDS_PER_FLASH_PAGE 0x00
478 /** Ugh, this varies by chip.
482 //#define FLASHPAGE_SIZE 0x400
483 #define MAXFLASHPAGE_SIZE 0x800
484 #define MINFLASHPAGE_SIZE 0x400
487 //32 bit words on CC2430
488 //16 bit words on CC1110
489 //#define FLASH_WORD_SIZE 0x2
490 u8 flash_word_size = 0; //0x02;
493 /* Flash Write Timing
500 32 | 0x2A (Modula.si)
504 const u8 flash_routine[] = {
508 0x00,//#imm=((address >> 8) / FLASH_WORD_SIZE) & 0x7E,
510 //0x75, 0xAB, 0x23, //Set FWT per clock
511 0x75, 0xAC, 0x00, // MOV FADDRL, #00;
513 0x75, 0xAE, 0x01, // MOV FLC, #01H; // ERASE
514 // ; Wait for flash erase to complete
515 0xE5, 0xAE, // eraseWaitLoop: MOV A, FLC;
516 0x20, 0xE7, 0xFB, // JB ACC_BUSY, eraseWaitLoop;
518 /* End erase page. */
519 // ; Initialize the data pointer
520 0x90, 0xF0, 0x00, // MOV DPTR, #0F000H;
522 0x7F, HIBYTE_WORDS_PER_FLASH_PAGE, // MOV R7, #imm;
523 0x7E, LOBYTE_WORDS_PER_FLASH_PAGE, // MOV R6, #imm;
524 0x75, 0xAE, 0x02, // MOV FLC, #02H; // WRITE
527 0x7D, 0xde /*FLASH_WORD_SIZE*/, // writeLoop: MOV R5, #imm;
528 0xE0, // writeWordLoop: MOVX A, @DPTR;
530 0xF5, 0xAF, // MOV FWDATA, A;
531 0xDD, 0xFA, // DJNZ R5, writeWordLoop;
532 // ; Wait for completion
533 0xE5, 0xAE, // writeWaitLoop: MOV A, FLC;
534 0x20, 0xE6, 0xFB, // JB ACC_SWBSY, writeWaitLoop;
535 0xDE, 0xF1, // DJNZ R6, writeLoop;
536 0xDF, 0xEF, // DJNZ R7, writeLoop;
537 // ; Done, fake a breakpoint
542 //! Copies flash buffer to flash.
543 void cc_write_flash_page(u32 adr){
544 //Assumes that page has already been written to XDATA 0xF000
545 //debugstr("Flashing 2kb at 0xF000 to given adr.");
547 if(adr&(MINFLASHPAGE_SIZE-1)){
548 debugstr("Flash page address is not on a page boundary. Aborting.");
552 if(flash_word_size!=2 && flash_word_size!=4){
553 debugstr("Flash word size is wrong, aborting write to");
559 //WRITE_XDATA_MEMORY(IN: 0xF000 + FLASH_PAGE_SIZE, sizeof(routine), routine);
560 cc_write_xdata(0xF000+MAXFLASHPAGE_SIZE,
561 (u8*) flash_routine, sizeof(flash_routine));
562 //Patch routine's third byte with
563 //((address >> 8) / FLASH_WORD_SIZE) & 0x7E
564 cc_pokedatabyte(0xF000+MAXFLASHPAGE_SIZE+2,
565 ((adr>>8)/flash_word_size)&0x7E);
566 //Patch routine to define FLASH_WORD_SIZE
567 if(flash_routine[25]!=0xde)
568 debugstr("Ugly patching code failing in chipcon.c");
569 cc_pokedatabyte(0xF000+MAXFLASHPAGE_SIZE+25,
572 //debugstr("Wrote flash routine.");
574 //MOV MEMCTR, (bank * 16) + 1;
579 //debugstr("Loaded bank info.");
581 cc_set_pc(0xf000+MAXFLASHPAGE_SIZE);//execute code fragment
584 //debugstr("Executing.");
587 while(!(cc_read_status()&CC_STATUS_CPUHALTED)){
588 led_toggle();//blink LED while flashing
592 //debugstr("Done flashing.");
598 unsigned short cc_get_pc(){
599 cmddata[0]=CCCMD_GET_PC; //0x28
604 return cmddataword[0];
607 //! Set a hardware breakpoint.
608 void cc_set_hw_brkpnt(unsigned short adr){
609 debugstr("FIXME: This certainly won't work.");
619 cmddata[0]=CCCMD_HALT; //0x44
626 cmddata[0]=CCCMD_RESUME; //0x4C
633 //! Step an instruction
634 void cc_step_instr(){
635 cmddata[0]=CCCMD_STEP_INSTR; //0x5C
641 //! Debug an instruction.
642 void cc_debug_instr(unsigned char len){
643 //Bottom two bits of command indicate length.
644 unsigned char cmd=CCCMD_DEBUG_INSTR+(len&0x3); //0x54+len
646 cctrans8(cmd); //Second command code
647 cccmd(len&0x3); //Command itself.
652 //! Debug an instruction, for local use.
653 unsigned char cc_debug(unsigned char len,
657 unsigned char cmd=CCCMD_DEBUG_INSTR+(len&0x3);//0x54+len
667 return cctrans8(0x00);
670 //! Fetch a byte of code memory.
671 unsigned char cc_peekcodebyte(unsigned long adr){
672 /** See page 9 of SWRA124 */
673 unsigned char bank=adr>>15,
679 //MOV MEMCTR, (bank*16)+1
680 cc_debug(3, 0x75, 0xC7, (bank<<4) + 1);
682 cc_debug(3, 0x90, hb, lb);
686 cc_debug(2, 0xE4, 0, 0);
688 toret=cc_debug(3, 0x93, 0, 0);
690 //cc_debug(1, 0xA3, 0, 0);
696 //! Set a byte of data memory.
697 unsigned char cc_pokedatabyte(unsigned int adr,
704 cc_debug(3, 0x90, hb, lb);
706 cc_debug(2, 0x74, val, 0);
708 cc_debug(1, 0xF0, 0, 0);
712 DEBUG_INSTR(IN: 0x90, HIBYTE(address), LOBYTE(address), OUT: Discard);
713 for (n = 0; n < count; n++) {
714 DEBUG_INSTR(IN: 0x74, inputArray[n], OUT: Discard);
715 DEBUG_INSTR(IN: 0xF0, OUT: Discard);
716 DEBUG_INSTR(IN: 0xA3, OUT: Discard);
721 //! Fetch a byte of data memory.
722 unsigned char cc_peekdatabyte(unsigned int adr){
728 cc_debug(3, 0x90, hb, lb);
730 //Must be 2, perhaps for clocking?
731 return cc_debug(3, 0xE0, 0, 0);
735 //! Fetch a byte of IRAM.
736 u8 cc_peekirambyte(u8 adr){
738 cc_debug(2, 0xE4, 0, 0);
740 return cc_debug(3, 0xE5, adr, 0);
743 //! Write a byte of IRAM.
744 u8 cc_pokeirambyte(u8 adr, u8 val){
746 cc_debug(2, 0xE4, 0, 0);
748 return cc_debug(3, 0x75, adr, val);
749 //return cc_debug(3, 0x75, val, adr);