2 \author Travis Goodspeed
3 \brief Chipcon 8051 debugging.
7 //This is like SPI, except that you read or write, not both.
9 /* N.B. The READ verb performs a write of all (any) supplied data,
10 then reads a single byte reply from the target. The WRITE verb
23 /* Concerning clock rates, the maximimum clock rates are defined on
24 page 4 of the spec. They vary, but are roughly 30MHz. Raising
25 this clock rate might allow for clock glitching, but the GoodFET
26 isn't sufficient fast for that. Perhaps a 200MHz ARM or an FPGA in
31 //MISO and MOSI are the same pin, direction changes.
38 //This could be more accurate.
39 //Does it ever need to be?
41 #define CCDELAY(x) delay(x)
44 #define SETMOSI P5OUT|=MOSI
45 #define CLRMOSI P5OUT&=~MOSI
46 #define SETCLK P5OUT|=SCK
47 #define CLRCLK P5OUT&=~SCK
48 #define READMISO (P5IN&MISO?1:0)
50 #define CCWRITE P5DIR|=MOSI
51 #define CCREAD P5DIR&=~MISO
53 //! Set up the pins for CC mode. Does not init debugger.
61 /* 33 cycle critical region
62 0000000e <ccdebuginit>:
63 e: f2 d0 0d 00 bis.b #13, &0x0031 ;5 cycles
65 14: f2 c2 31 00 bic.b #8, &0x0031 ;4 cycles
66 18: d2 c3 31 00 bic.b #1, &0x0031 ;4
67 1c: f2 e2 31 00 xor.b #8, &0x0031 ;4
68 20: f2 e2 31 00 xor.b #8, &0x0031 ;4
69 24: f2 e2 31 00 xor.b #8, &0x0031 ;4
70 28: f2 e2 31 00 xor.b #8, &0x0031 ;4
71 2c: d2 d3 31 00 bis.b #1, &0x0031 ;4
76 //! Initialize the debugger
78 //Port output BUT NOT DIRECTION is set at start.
81 //delay(30); //So the beginning is ready for glitching.
83 //Two positive debug clock pulses while !RST is low.
84 //Take RST low, pulse twice, then high.
98 P5OUT^=SCK; //Unnecessary.
106 //! Read and write a CC bit.
107 unsigned char cctrans8(unsigned char byte){
109 //This function came from the SPI Wikipedia article.
112 for (bit = 0; bit < 8; bit++) {
113 /* write MOSI on trailing edge of previous clock */
120 /* half a clock cycle before leading/rising edge */
124 /* half a clock cycle before trailing/falling edge */
127 /* read MISO on trailing edge */
135 //! Send a command from txbytes.
136 void cccmd(unsigned char len){
140 cctrans8(cmddata[i]);
143 //! Fetch a reply, usually 1 byte.
144 void ccread(unsigned char len){
148 cmddata[i]=cctrans8(0);
151 //! Handles a monitor command.
152 void cchandle(unsigned char app,
155 //Always init. Might help with buggy lines.
159 int blocklen, blockadr;
162 //CC_PEEK and CC_POKE will come later.
164 cmddata[0]=cc_peekirambyte(cmddata[0]);
168 cmddata[0]=cc_pokeirambyte(cmddata[0],cmddata[1]);
171 case READ: //Write a command and return 1-byte reply.
177 case WRITE: //Write a command with no reply.
181 case START://enter debugger
185 case STOP://exit debugger
186 //Take RST low, then high.
199 case CC_MASS_ERASE_FLASH:
204 cc_wr_config(cmddata[0]);
217 //no break, return status
222 case CC_SET_HW_BRKPNT:
223 cc_set_hw_brkpnt(cmddataword[0]);
242 case CC_STEP_REPLACE:
243 txdata(app,NOK,0);//TODO add me
246 cmddataword[0]=cc_get_chip_id();
252 case CC_READ_CODE_MEMORY:
253 cmddata[0]=cc_peekcodebyte(cmddataword[0]);
256 case CC_READ_XDATA_MEMORY:
260 blocklen=cmddataword[1];
261 blockadr=cmddataword[0];
263 //Return that many bytes.
264 for(i=0;i<blocklen;i++)
265 cmddata[i]=cc_peekdatabyte(blockadr+i);
266 txdata(app,verb,blocklen);
269 case CC_WRITE_XDATA_MEMORY:
270 cmddata[0]=cc_pokedatabyte(cmddataword[0], cmddata[2]);
274 cc_set_pc(cmddatalong[0]);
277 case CC_WRITE_FLASH_PAGE:
278 cc_write_flash_page(cmddatalong[0]);
281 case CC_WIPEFLASHBUFFER:
282 for(i=0xf000;i<0xf800;i++)
283 cc_pokedatabyte(i,0xFF);
288 case CC_PROGRAM_FLASH:
290 debugstr("This Chipcon command is not yet implemented.");
291 txdata(app,NOK,0);//TODO implement me.
296 //! Set the Chipcon's Program Counter
297 void cc_set_pc(u32 adr){
298 cmddata[0]=0x02; //SetPC
299 cmddata[1]=((adr>>8)&0xff); //HIBYTE
300 cmddata[2]=adr&0xff; //LOBYTE
305 //! Erase all of a Chipcon's memory.
306 void cc_chip_erase(){
307 cmddata[0]=CCCMD_CHIP_ERASE; //0x14
311 //! Write the configuration byte.
312 void cc_wr_config(unsigned char config){
313 cmddata[0]=CCCMD_WR_CONFIG; //0x1D
323 //debugstr("Locking chip.");
324 cc_wr_config(1);//Select Info Flash
325 if(!(cc_rd_config()&1))
326 debugstr("Config forgotten!");
330 cc_pokedatabyte(0xf000+i,0);
331 cc_write_flash_page(0);
332 if(cc_peekcodebyte(0))
333 debugstr("Failed to clear info flash byte.");
337 debugstr("Stuck in info flash mode!");
340 //! Read the configuration byte.
341 unsigned char cc_rd_config(){
342 cmddata[0]=CCCMD_RD_CONFIG; //0x24
349 //! Read the status register
350 unsigned char cc_read_status(){
351 cmddata[0]=CCCMD_READ_STATUS; //0x3f
357 //! Read the CHIP ID bytes.
358 unsigned short cc_get_chip_id(){
359 cmddata[0]=CCCMD_GET_CHIP_ID; //0x68
364 //Find the flash word size.
370 //debugstr("2 bytes/flash word");
371 flash_word_size=0x02;
374 //debugstr("Warning: Guessing flash word size.");
379 //debugstr("4 bytes/flash word");
380 flash_word_size=0x04;
385 return cmddataword[0];
388 //! Populates flash buffer in xdata.
389 void cc_write_flash_buffer(u8 *data, u16 len){
390 cc_write_xdata(0xf000, data, len);
392 //! Populates flash buffer in xdata.
393 void cc_write_xdata(u16 adr, u8 *data, u16 len){
395 for(i=0; i<len; i++){
396 cc_pokedatabyte(adr+i,
402 //32-bit words, 2KB pages
403 //0x20 0x00 for CC2430, CC1110
404 #define HIBYTE_WORDS_PER_FLASH_PAGE 0x02
405 #define LOBYTE_WORDS_PER_FLASH_PAGE 0x00
407 /** Ugh, this varies by chip.
411 //#define FLASHPAGE_SIZE 0x400
412 #define MAXFLASHPAGE_SIZE 0x800
413 #define MINFLASHPAGE_SIZE 0x400
416 //32 bit words on CC2430
417 //16 bit words on CC1110
418 //#define FLASH_WORD_SIZE 0x2
419 u8 flash_word_size = 0; //0x02;
422 /* Flash Write Timing
429 32 | 0x2A (Modula.si)
433 const u8 flash_routine[] = {
437 0x00,//#imm=((address >> 8) / FLASH_WORD_SIZE) & 0x7E,
439 //0x75, 0xAB, 0x23, //Set FWT per clock
440 0x75, 0xAC, 0x00, // MOV FADDRL, #00;
442 0x75, 0xAE, 0x01, // MOV FLC, #01H; // ERASE
443 // ; Wait for flash erase to complete
444 0xE5, 0xAE, // eraseWaitLoop: MOV A, FLC;
445 0x20, 0xE7, 0xFB, // JB ACC_BUSY, eraseWaitLoop;
447 /* End erase page. */
448 // ; Initialize the data pointer
449 0x90, 0xF0, 0x00, // MOV DPTR, #0F000H;
451 0x7F, HIBYTE_WORDS_PER_FLASH_PAGE, // MOV R7, #imm;
452 0x7E, LOBYTE_WORDS_PER_FLASH_PAGE, // MOV R6, #imm;
453 0x75, 0xAE, 0x02, // MOV FLC, #02H; // WRITE
456 0x7D, 0xde /*FLASH_WORD_SIZE*/, // writeLoop: MOV R5, #imm;
457 0xE0, // writeWordLoop: MOVX A, @DPTR;
459 0xF5, 0xAF, // MOV FWDATA, A;
460 0xDD, 0xFA, // DJNZ R5, writeWordLoop;
461 // ; Wait for completion
462 0xE5, 0xAE, // writeWaitLoop: MOV A, FLC;
463 0x20, 0xE6, 0xFB, // JB ACC_SWBSY, writeWaitLoop;
464 0xDE, 0xF1, // DJNZ R6, writeLoop;
465 0xDF, 0xEF, // DJNZ R7, writeLoop;
466 // ; Done, fake a breakpoint
471 //! Copies flash buffer to flash.
472 void cc_write_flash_page(u32 adr){
473 //Assumes that page has already been written to XDATA 0xF000
474 //debugstr("Flashing 2kb at 0xF000 to given adr.");
476 if(adr&(MINFLASHPAGE_SIZE-1)){
477 debugstr("Flash page address is not on a page boundary. Aborting.");
481 if(flash_word_size!=2 && flash_word_size!=4){
482 debugstr("Flash word size is wrong, aborting write to");
488 //WRITE_XDATA_MEMORY(IN: 0xF000 + FLASH_PAGE_SIZE, sizeof(routine), routine);
489 cc_write_xdata(0xF000+MAXFLASHPAGE_SIZE,
490 (u8*) flash_routine, sizeof(flash_routine));
491 //Patch routine's third byte with
492 //((address >> 8) / FLASH_WORD_SIZE) & 0x7E
493 cc_pokedatabyte(0xF000+MAXFLASHPAGE_SIZE+2,
494 ((adr>>8)/flash_word_size)&0x7E);
495 //Patch routine to define FLASH_WORD_SIZE
496 if(flash_routine[25]!=0xde)
497 debugstr("Ugly patching code failing in chipcon.c");
498 cc_pokedatabyte(0xF000+MAXFLASHPAGE_SIZE+25,
501 //debugstr("Wrote flash routine.");
503 //MOV MEMCTR, (bank * 16) + 1;
508 //debugstr("Loaded bank info.");
510 cc_set_pc(0xf000+MAXFLASHPAGE_SIZE);//execute code fragment
513 //debugstr("Executing.");
516 while(!(cc_read_status()&CC_STATUS_CPUHALTED)){
517 PLEDOUT^=PLEDPIN;//blink LED while flashing
521 //debugstr("Done flashing.");
523 PLEDOUT&=~PLEDPIN;//clear LED
527 unsigned short cc_get_pc(){
528 cmddata[0]=CCCMD_GET_PC; //0x28
533 return cmddataword[0];
536 //! Set a hardware breakpoint.
537 void cc_set_hw_brkpnt(unsigned short adr){
538 debugstr("FIXME: This certainly won't work.");
548 cmddata[0]=CCCMD_HALT; //0x44
555 cmddata[0]=CCCMD_RESUME; //0x4C
562 //! Step an instruction
563 void cc_step_instr(){
564 cmddata[0]=CCCMD_STEP_INSTR; //0x5C
570 //! Debug an instruction.
571 void cc_debug_instr(unsigned char len){
572 //Bottom two bits of command indicate length.
573 unsigned char cmd=CCCMD_DEBUG_INSTR+(len&0x3); //0x54+len
575 cctrans8(cmd); //Second command code
576 cccmd(len&0x3); //Command itself.
581 //! Debug an instruction, for local use.
582 unsigned char cc_debug(unsigned char len,
586 unsigned char cmd=CCCMD_DEBUG_INSTR+(len&0x3);//0x54+len
596 return cctrans8(0x00);
599 //! Fetch a byte of code memory.
600 unsigned char cc_peekcodebyte(unsigned long adr){
601 /** See page 9 of SWRA124 */
602 unsigned char bank=adr>>15,
608 //MOV MEMCTR, (bank*16)+1
609 cc_debug(3, 0x75, 0xC7, (bank<<4) + 1);
611 cc_debug(3, 0x90, hb, lb);
615 cc_debug(2, 0xE4, 0, 0);
617 toret=cc_debug(3, 0x93, 0, 0);
619 //cc_debug(1, 0xA3, 0, 0);
625 //! Set a byte of data memory.
626 unsigned char cc_pokedatabyte(unsigned int adr,
633 cc_debug(3, 0x90, hb, lb);
635 cc_debug(2, 0x74, val, 0);
637 cc_debug(1, 0xF0, 0, 0);
641 DEBUG_INSTR(IN: 0x90, HIBYTE(address), LOBYTE(address), OUT: Discard);
642 for (n = 0; n < count; n++) {
643 DEBUG_INSTR(IN: 0x74, inputArray[n], OUT: Discard);
644 DEBUG_INSTR(IN: 0xF0, OUT: Discard);
645 DEBUG_INSTR(IN: 0xA3, OUT: Discard);
650 //! Fetch a byte of data memory.
651 unsigned char cc_peekdatabyte(unsigned int adr){
657 cc_debug(3, 0x90, hb, lb);
659 //Must be 2, perhaps for clocking?
660 return cc_debug(3, 0xE0, 0, 0);
664 //! Fetch a byte of IRAM.
665 u8 cc_peekirambyte(u8 adr){
667 cc_debug(2, 0xE4, 0, 0);
669 return cc_debug(3, 0xE5, adr, 0);
672 //! Write a byte of IRAM.
673 u8 cc_pokeirambyte(u8 adr, u8 val){
675 cc_debug(2, 0xE4, 0, 0);
677 return cc_debug(3, 0x75, adr, val);
678 //return cc_debug(3, 0x75, val, adr);