git.rot13.org Git - goodfet/blob - firmware/apps/jtag/jtag430.c

   1 /*! \file jtag430.c
   2   \author Travis Goodspeed <travis at radiantmachines.com>
   3   \brief MSP430 JTAG (16-bit)
   4 */
   5
   6 #include "platform.h"
   7 #include "command.h"
   8 #include "jtag.h"
   9
  10
  11 unsigned int jtag430mode=MSP430X2MODE;
  12
  13 //! Set the program counter.
  14 void jtag430_setpc(unsigned int adr){
  15   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
  16   jtag_dr_shift16(0x3401);// release low byte
  17   jtag_ir_shift8(IR_DATA_16BIT);
  18   jtag_dr_shift16(0x4030);//Instruction to load PC
  19   CLRTCLK;
  20   SETTCLK;
  21   jtag_dr_shift16(adr);// Value for PC
  22   CLRTCLK;
  23   jtag_ir_shift8(IR_ADDR_CAPTURE);
  24   SETTCLK;
  25   CLRTCLK ;// Now PC is set to "PC_Value"
  26   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
  27   jtag_dr_shift16(0x2401);// low byte controlled by JTAG
  28 }
  29
  30 //! Halt the CPU
  31 void jtag430_haltcpu(){
  32   //jtag430_setinstrfetch();
  33
  34   jtag_ir_shift8(IR_DATA_16BIT);
  35   jtag_dr_shift16(0x3FFF);//JMP $+0
  36
  37   CLRTCLK;
  38   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
  39   jtag_dr_shift16(0x2409);//set JTAG_HALT bit
  40   SETTCLK;
  41 }
  42
  43 //! Release the CPU
  44 void jtag430_releasecpu(){
  45   CLRTCLK;
  46   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
  47   jtag_dr_shift16(0x2401);
  48   jtag_ir_shift8(IR_ADDR_CAPTURE);
  49   SETTCLK;
  50 }
  51
  52 //! Read data from address
  53 unsigned int jtag430_readmem(unsigned int adr){
  54   unsigned int toret;
  55   jtag430_haltcpu();
  56
  57   CLRTCLK;
  58   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
  59
  60   if(adr>0xFF)
  61     jtag_dr_shift16(0x2409);//word read
  62   else
  63     jtag_dr_shift16(0x2419);//byte read
  64   jtag_ir_shift8(IR_ADDR_16BIT);
  65   jtag_dr_shift16(adr);//address
  66   jtag_ir_shift8(IR_DATA_TO_ADDR);
  67   SETTCLK;
  68
  69   CLRTCLK;
  70   toret=jtag_dr_shift16(0x0000);//16 bit return
  71
  72   return toret;
  73 }
  74
  75 //! Write data to address.
  76 void jtag430_writemem(unsigned int adr, unsigned int data){
  77   CLRTCLK;
  78   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
  79   if(adr>0xFF)
  80     jtag_dr_shift16(0x2408);//word write
  81   else
  82     jtag_dr_shift16(0x2418);//byte write
  83   jtag_ir_shift8(IR_ADDR_16BIT);
  84   jtag_dr_shift16(adr);
  85   jtag_ir_shift8(IR_DATA_TO_ADDR);
  86   jtag_dr_shift16(data);
  87   SETTCLK;
  88 }
  89
  90 //! Write data to flash memory.  Must be preconfigured.
  91 void jtag430_writeflashword(unsigned int adr, unsigned int data){
  92
  93   CLRTCLK;
  94   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
  95   jtag_dr_shift16(0x2408);//word write
  96   jtag_ir_shift8(IR_ADDR_16BIT);
  97   jtag_dr_shift16(adr);
  98   jtag_ir_shift8(IR_DATA_TO_ADDR);
  99   jtag_dr_shift16(data);
 100   SETTCLK;
 101
 102   //Return to read mode.
 103   CLRTCLK;
 104   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
 105   jtag_dr_shift16(0x2409);
 106
 107   /*
 108   jtag430_writemem(adr,data);
 109   CLRTCLK;
 110   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
 111   jtag_dr_shift16(0x2409);
 112   */
 113
 114   //Pulse TCLK
 115   jtag430_tclk_flashpulses(35); //35 standard
 116 }
 117
 118 //! Configure flash, then write a word.
 119 void jtag430_writeflash(unsigned int adr, unsigned int data){
 120   jtag430_haltcpu();
 121
 122   //FCTL1=0xA540, enabling flash write
 123   jtag430_writemem(0x0128, 0xA540);
 124   //FCTL2=0xA540, selecting MCLK as source, DIV=1
 125   jtag430_writemem(0x012A, 0xA540);
 126   //FCTL3=0xA500, should be 0xA540 for Info Seg A on 2xx chips.
 127   jtag430_writemem(0x012C, 0xA500); //all but info flash.
 128
 129   //Write the word itself.
 130   jtag430_writeflashword(adr,data);
 131
 132   //FCTL1=0xA500, disabling flash write
 133   jtag430_writemem(0x0128, 0xA500);
 134
 135   //jtag430_releasecpu();
 136 }
 137
 138
 139
 140 //! Power-On Reset
 141 void jtag430_por(){
 142   unsigned int jtagid;
 143
 144   // Perform Reset
 145   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
 146   jtag_dr_shift16(0x2C01); // apply
 147   jtag_dr_shift16(0x2401); // remove
 148   CLRTCLK;
 149   SETTCLK;
 150   CLRTCLK;
 151   SETTCLK;
 152   CLRTCLK;
 153   jtagid = jtag_ir_shift8(IR_ADDR_CAPTURE); // get JTAG identifier
 154   SETTCLK;
 155
 156   jtag430_writemem(0x0120, 0x5A80);   // Diabled Watchdog
 157 }
 158
 159
 160
 161 #define ERASE_GLOB 0xA50E
 162 #define ERASE_ALLMAIN 0xA50C
 163 #define ERASE_MASS 0xA506
 164 #define ERASE_MAIN 0xA504
 165 #define ERASE_SGMT 0xA502
 166
 167 //! Configure flash, then write a word.
 168 void jtag430_eraseflash(unsigned int mode, unsigned int adr, unsigned int count){
 169   jtag430_haltcpu();
 170
 171   //FCTL1= erase mode
 172   jtag430_writemem(0x0128, mode);
 173   //FCTL2=0xA540, selecting MCLK as source, DIV=1
 174   jtag430_writemem(0x012A, 0xA540);
 175   //FCTL3=0xA500, should be 0xA540 for Info Seg A on 2xx chips.
 176   jtag430_writemem(0x012C, 0xA500);
 177
 178   //Write the erase word.
 179   jtag430_writemem(adr, 0x55AA);
 180   //Return to read mode.
 181   CLRTCLK;
 182   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
 183   jtag_dr_shift16(0x2409);
 184
 185   //Send the pulses.
 186   jtag430_tclk_flashpulses(count);
 187
 188   //FCTL1=0xA500, disabling flash write
 189   jtag430_writemem(0x0128, 0xA500);
 190
 191   //jtag430_releasecpu();
 192 }
 193
 194
 195 //! Reset the TAP state machine.
 196 void jtag430_resettap(){
 197   int i;
 198   // Settle output
 199   SETTDI; //430X2
 200   SETTMS;
 201   //SETTDI; //classic
 202   SETTCK;
 203
 204   // Navigate to reset state.
 205   // Should be at least six.
 206   for(i=0;i<4;i++){
 207     CLRTCK;
 208     SETTCK;
 209   }
 210
 211   // test-logic-reset
 212   CLRTCK;
 213   CLRTMS;
 214   SETTCK;
 215   SETTMS;
 216   // idle
 217
 218
 219   /* sacred, by spec.
 220      Sometimes this isn't necessary.  */
 221   // fuse check
 222   CLRTMS;
 223   delay(50);
 224   SETTMS;
 225   CLRTMS;
 226   delay(50);
 227   SETTMS;
 228   /**/
 229
 230 }
 231
 232 //! Start JTAG, take pins
 233 void jtag430_start(){
 234   jtagsetup();
 235
 236   //Known-good starting position.
 237   //Might be unnecessary.
 238   SETTST;
 239   SETRST;
 240   delay(0xFFFF);
 241
 242   //Entry sequence from Page 67 of SLAU265A for 4-wire MSP430 JTAG
 243   CLRRST;
 244   delay(100); //100
 245   CLRTST;
 246   delay(50);  //50
 247   SETTST;
 248   delay(50);  //50
 249   SETRST;
 250   P5DIR&=~RST;
 251   delay(0xFFFF);
 252
 253   //Perform a reset and disable watchdog.
 254   jtag430_por();
 255   jtag430_writemem(0x120,0x5a80);//disable watchdog
 256
 257   jtag430_haltcpu();
 258 }
 259
 260 //! Set CPU to Instruction Fetch
 261 void jtag430_setinstrfetch(){
 262
 263   jtag_ir_shift8(IR_CNTRL_SIG_CAPTURE);
 264
 265   // Wait until instruction fetch state.
 266   while(1){
 267     if (jtag_dr_shift16(0x0000) & 0x0080)
 268       return;
 269     CLRTCLK;
 270     SETTCLK;
 271   }
 272 }
 273
 274
 275 //! Handles classic MSP430 JTAG commands.  Forwards others to JTAG.
 276 void jtag430handle(unsigned char app,
 277                    unsigned char verb,
 278                    unsigned long len){
 279   unsigned long at;
 280   unsigned int i, val;
 281
 282   //debugstr("Classic MSP430 handler.");
 283
 284   switch(verb){
 285   case START:
 286     //Enter JTAG mode.
 287     jtag430_start();
 288     //TAP setup, fuse check
 289     jtag430_resettap();
 290
 291     txdata(app,verb,0);
 292     break;
 293   case JTAG430_HALTCPU:
 294     jtag430_haltcpu();
 295     txdata(app,verb,0);
 296     break;
 297   case JTAG430_RELEASECPU:
 298     jtag430_releasecpu();
 299     txdata(app,verb,0);
 300     break;
 301   case JTAG430_SETINSTRFETCH:
 302     jtag430_setinstrfetch();
 303     txdata(app,verb,0);
 304     break;
 305
 306   case JTAG430_READMEM:
 307   case PEEK:
 308     at=cmddatalong[0];
 309
 310     //Fetch large blocks for bulk fetches,
 311     //small blocks for individual peeks.
 312     if(len>5)
 313       len=(cmddataword[2]);//always even.
 314     else
 315       len=2;
 316     len&=~1;//clue lsbit
 317
 318     txhead(app,verb,len);
 319     for(i=0;i<len;i+=2){
 320       jtag430_resettap();
 321       val=jtag430_readmem(at);
 322
 323       at+=2;
 324       serial_tx(val&0xFF);
 325       serial_tx((val&0xFF00)>>8);
 326     }
 327     break;
 328   case JTAG430_WRITEMEM:
 329   case POKE:
 330     jtag430_haltcpu();
 331     jtag430_writemem(cmddataword[0],cmddataword[2]);
 332     cmddataword[0]=jtag430_readmem(cmddataword[0]);
 333     txdata(app,verb,2);
 334     break;
 335   case JTAG430_WRITEFLASH:
 336     //debugstr("Poking flash memory.");
 337     jtag430_writeflash(cmddataword[0],cmddataword[2]);
 338
 339     //Try again if failure.
 340     if(cmddataword[0]!=jtag430_readmem(cmddataword[0]))
 341       jtag430_writeflash(cmddataword[0],cmddataword[2]);
 342
 343     //Return result.
 344     cmddataword[0]=jtag430_readmem(cmddataword[0]);
 345
 346     txdata(app,verb,2);
 347     break;
 348   case JTAG430_ERASEFLASH:
 349     jtag430_eraseflash(ERASE_MASS,0xFFFE,0x3000);
 350     txdata(app,verb,0);
 351     break;
 352   case JTAG430_SETPC:
 353     jtag430_haltcpu();
 354     jtag430_setpc(cmddataword[0]);
 355     txdata(app,verb,0);
 356     break;
 357
 358   case JTAG430_COREIP_ID:
 359   case JTAG430_DEVICE_ID:
 360     cmddataword[0]=0;
 361     cmddataword[1]=0;
 362     txdata(app,verb,4);
 363     break;
 364
 365   default:
 366     jtaghandle(app,verb,len);
 367   }
 368   //jtag430_resettap();  //DO NOT UNCOMMENT
 369 }