1 //! MSP430F1612/1611 clock and I/O definitions
10 unsigned char serial0_rx(){
13 while(!(IFG1&URXIFG0));//wait for a byte
22 unsigned char serial1_rx(){
25 while(!(IFG2&URXIFG1));//wait for a byte
34 void serial0_tx(unsigned char x){
35 while ((IFG1 & UTXIFG0) == 0); //loop until buffer is free
39 //! Transmit a byte on the second UART.
40 void serial1_tx(unsigned char x){
41 while ((IFG2 & UTXIFG1) == 0); //loop until buffer is free
45 /** Later, add support for the EZ430/FETUIF with 12MHz crystal
46 UBR00=0xE2; UBR10=0x04; UMCTL0=0x00; // uart0 12000000Hz 9600bps
47 UBR00=0x71; UBR10=0x02; UMCTL0=0x00; // uart0 12000000Hz 19200bps
48 UBR00=0x38; UBR10=0x01; UMCTL0=0x55; // uart0 12000000Hz 38400bps
49 UBR00=0xD0; UBR10=0x00; UMCTL0=0x4A; // uart0 12000000Hz 57581bps
50 UBR00=0x68; UBR10=0x00; UMCTL0=0x04; // uart0 12000000Hz 115273bps
53 //! Set the baud rate.
54 void setbaud0(unsigned char rate){
56 //http://mspgcc.sourceforge.net/baudrate.html
59 UBR00=0x7F; UBR10=0x01; UMCTL0=0x5B; /* uart0 3683400Hz 9599bps */
62 UBR00=0xBF; UBR10=0x00; UMCTL0=0xF7; /* uart0 3683400Hz 19194bps */
65 UBR00=0x5F; UBR10=0x00; UMCTL0=0xBF; /* uart0 3683400Hz 38408bps */
68 UBR00=0x40; UBR10=0x00; UMCTL0=0x00; /* uart0 3683400Hz 57553bps */
72 UBR00=0x20; UBR10=0x00; UMCTL0=0x00; /* uart0 3683400Hz 115106bps */
77 //! Set the baud rate of the second uart.
78 void setbaud1(unsigned char rate){
79 //http://mspgcc.sourceforge.net/baudrate.html
82 UBR01=0x7F; UBR11=0x01; UMCTL1=0x5B; /* uart0 3683400Hz 9599bps */
85 UBR01=0xBF; UBR11=0x00; UMCTL1=0xF7; /* uart0 3683400Hz 19194bps */
88 UBR01=0x5F; UBR11=0x00; UMCTL1=0xBF; /* uart0 3683400Hz 38408bps */
91 UBR01=0x40; UBR11=0x00; UMCTL1=0x00; /* uart0 3683400Hz 57553bps */
95 UBR01=0x20; UBR11=0x00; UMCTL1=0x00; /* uart0 3683400Hz 115106bps */
101 void msp430_init_uart0(){
104 P3SEL |= BIT4|BIT5; // P3.4,5 = USART0 TXD/RXD
107 UCTL0 = SWRST | CHAR; /* 8-bit character, UART mode */
108 UTCTL0 = SSEL1; /* UCLK = MCLK */
112 ME1 &= ~USPIE0; /* USART1 SPI module disable */
113 ME1 |= (UTXE0 | URXE0); /* Enable USART1 TXD/RXD */
117 /* XXX Clear pending interrupts before enable!!! */
121 //IE1 |= URXIE1; /* Enable USART1 RX interrupt */
125 void msp430_init_uart1(){
128 P3DIR &= ~0x80; /* Select P37 for input (UART1RX) */
129 P3DIR |= 0x40; /* Select P36 for output (UART1TX) */
130 P3SEL |= 0xC0; /* Select P36,P37 for UART1{TX,RX} */
132 UCTL1 = SWRST | CHAR; /* 8-bit character, UART mode */
133 UTCTL1 = SSEL1; /* UCLK = MCLK */
137 ME2 &= ~USPIE1; /* USART1 SPI module disable */
138 ME2 |= (UTXE1 | URXE1); /* Enable USART1 TXD/RXD */
142 /* XXX Clear pending interrupts before enable!!! */
145 //IE2 |= URXIE1; /* Enable USART1 RX interrupt */
150 void msp430_init_dco() {
151 WDTCTL = WDTPW + WDTHOLD; //stop WDT
158 for (i=0; i<1000; i++);
160 } while (IFG1 & OFIFG);
162 BCSCTL2 = SELM1 | DIVM1 | SELS;
168 //! Initialization is correct.
169 void msp430_init_dco_done(){
170 //Nothing to do for the 1612.
174 void msp430_init_dco() {
175 /* This code taken from the FU Berlin sources and reformatted. */
179 //#define MSP430_CPU_SPEED 2457600UL
181 //Too fast for internal resistor.
182 //#define MSP430_CPU_SPEED 4915200UL
185 //#define MSP430_CPU_SPEED 4500000UL
188 #define MSP430_CPU_SPEED 3683400UL
189 #define DELTA ((MSP430_CPU_SPEED) / (32768 / 8))
190 unsigned int compare, oldcapture = 0;
193 WDTCTL = WDTPW + WDTHOLD; //stop WDT
200 /* ACLK is devided by 4. RSEL=6 no division for MCLK
201 and SSMCLK. XT2 is off. */
204 BCSCTL2 = 0x00; /* Init FLL to desired frequency using the 32762Hz
205 crystal DCO frquenzy = 2,4576 MHz */
209 BCSCTL1 |= DIVA1 + DIVA0; /* ACLK = LFXT1CLK/8 */
210 for(i = 0xffff; i > 0; i--) { /* Delay for XTAL to settle */
214 CCTL2 = CCIS0 + CM0 + CAP; // Define CCR2, CAP, ACLK
215 TACTL = TASSEL1 + TACLR + MC1; // SMCLK, continous mode
220 while((CCTL2 & CCIFG) != CCIFG); /* Wait until capture occured! */
221 CCTL2 &= ~CCIFG; /* Capture occured, clear flag */
222 compare = CCR2; /* Get current captured SMCLK */
223 compare = compare - oldcapture; /* SMCLK difference */
224 oldcapture = CCR2; /* Save current captured SMCLK */
226 if(DELTA == compare) {
227 break; /* if equal, leave "while(1)" */
228 } else if(DELTA < compare) { /* DCO is too fast, slow it down */
230 if(DCOCTL == 0xFF) { /* Did DCO role under? */
233 } else { /* -> Select next lower RSEL */
235 if(DCOCTL == 0x00) { /* Did DCO role over? */
238 /* -> Select next higher RSEL */
242 CCTL2 = 0; /* Stop CCR2 function */
243 TACTL = 0; /* Stop Timer_A */
245 BCSCTL1 &= ~(DIVA1 + DIVA0); /* remove /8 divisor from ACLK again */