3 \author Dave Huseby <dave@linuxprogrammer.org>
4 \brief Intel XScale JTAG
10 #include "jtagxscale.h"
12 #define JTAGXSCALE_APP
14 /* Handles XScale JTAG commands. Forwards others to JTAG. */
15 void jtag_xscale_handle_fn( uint8_t const app,
19 // define the jtag xscale app's app_t
20 app_t const jtagxscale_app = {
26 jtag_xscale_handle_fn,
32 "\tThe JTAG Xscale app extends the JTAG app adding support\n"
33 "\tfor JTAG'ing Intel XScale devices.\n"
37 /* From the Intel XScale Core Developer's Manual:
39 * The Intel XScale® core provides test features compatible with IEEE Standard
40 * Test Access Port and Boundary Scan Architecture (IEEE Std. 1149.1). These
41 * features include a TAP controller, a 5 or 7 bit instruction register, and
42 * test data registers to support software debug. The size of the instruction
43 * register depends on which variant of the Intel XScale® core is being used.
44 * This can be found out by examining the CoreGen field of Coprocessor 15, ID
45 * Register (bits 15:13). (See Table 7-4, "ID Register" on page 7-81 for more
46 * details.) A CoreGen value of 0x1 means the JTAG instruction register size
47 * is 5 bits and a CoreGen value of 0x2 means the JTAG instruction register
52 /* NOTE: I heavily cribbed from the ARM7TDMI jtag implementation. Credit where
55 void jtag_xscale_reset_cpu(void)
65 /* Handles XScale JTAG commands. Forwards others to JTAG. */
66 void jtag_xscale_handle_fn( uint8_t const app,
73 /* set up the pin I/O for JTAG */
75 /* reset to run-test-idle state */
97 case JTAG_RESET_TARGET:
98 jtag_xscale_reset_cpu();
103 (*(jtag_app.handle))(app,verb,len);