1 /******************************************************************************
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2 Filename: ioCCxx10_bitdef.h
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4 This file contains the bit definitions of registers in CCxx10
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6 Copyright 2008 Texas Instruments, Inc.
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7 ******************************************************************************/
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8 #ifndef _IOCCXX10_BITDEF_H
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9 #define _IOCCXX10_BITDEF_H
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13 /* SEE DATA SHEET FOR DETAILS ABOUT THE FOLLOWING BIT MASKS */
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17 /*******************************************************************************
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18 * Memory Control Registers
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21 // MPAGE (0x93) - Memory Page Select
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23 // MEMCTR (0xC7) - Memory Arbiter Control
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24 #define MEMCTR_CACHD 0x02
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25 #define MEMCTR_PREFD 0x01
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28 /*******************************************************************************
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32 // DPH0 (0x83) - Data Pointer 0 High Byte
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34 // DPL0 (0x82) - Data Pointer 0 Low Byte
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36 // DPH1 (0x85) - Data Pointer 1 High Byte
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38 // DPL1 (0x84) - Data Pointer 1 Low Byte
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40 // DPS (0x92) - Data Pointer Select
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41 #define DPS_VDPS 0x01
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44 // PSW (0xD0) - Progrttus Word - bit accessible SFR register
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46 // ACC (0xE0) - Accumulator - bit accessible SFR register
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48 // B (0xF0) - B Register - bit accessible SFR register
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50 // SP (0x81) - Stack Pointer
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53 /*******************************************************************************
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54 * Interrupt Control Registers
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57 // IEN0 (0xA8) - Interrupt Enable 0 Register - bit accessible SFR register
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59 // IEN1 (0xB8) - Interrupt Enable 1 Register - bit accessible SFR register
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61 // IEN2 (0x9A) - Interrupt Enable 2 Register
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62 #define IEN2_WDTIE 0x20
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63 #define IEN2_P1IE 0x10
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64 #define IEN2_UTX1IE 0x08
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65 #define IEN2_I2STXIE 0x08
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66 #define IEN2_UTX0IE 0x04
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67 #define IEN2_P2IE 0x02
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68 #define IEN2_USBIE 0x02
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69 #define IEN2_RFIE 0x01
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72 // TCON (0x88) - CPU Interrupt Flag 1 - bit accessible SFR register
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74 // S0CON (0x98) - CPU Interrupt Flag 2 - bit accessible SFR register
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76 // S1CON (0x9B) - CPU Interrupt Flag 3
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77 #define S1CON_RFIF_1 0x02
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78 #define S1CON_RFIF_0 0x01
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81 // IRCON (0xC0) - CPU Interrupt Flag 4 - bit accessible SFR register
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83 // IRCON2 (0xE8) - CPU Interrupt Flag 5 - bit accessible SFR register
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85 // IP1 (0xB9) - Interrupt Priority 1
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86 #define IP1_IPG5 0x20
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87 #define IP1_IPG4 0x10
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88 #define IP1_IPG3 0x08
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89 #define IP1_IPG2 0x04
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90 #define IP1_IPG1 0x02
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91 #define IP1_IPG0 0x01
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93 // IP0 (0xA9) - Interrupt Priority 0
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94 #define IP0_IPG5 0x20
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95 #define IP0_IPG4 0x10
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96 #define IP0_IPG3 0x08
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97 #define IP0_IPG2 0x04
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98 #define IP0_IPG1 0x02
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99 #define IP0_IPG0 0x01
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103 /*******************************************************************************
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104 * Power Management and Clocks
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107 // PCON (0x87) - Power Mode Control
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108 #define PCON_IDLE 0x01
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111 // SLEEP (0xBE) - Sleep Mode Control
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112 #define SLEEP_USB_EN 0x80
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113 #define SLEEP_XOSC_S 0x40
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114 #define SLEEP_HFRC_S 0x20
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115 #define SLEEP_RST 0x18
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116 #define SLEEP_RST0 0x08
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117 #define SLEEP_RST1 0x10
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118 #define SLEEP_OSC_PD 0x04
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119 #define SLEEP_MODE 0x03
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120 #define SLEEP_MODE1 0x02
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121 #define SLEEP_MODE0 0x01
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123 #define SLEEP_RST_POR_BOD (0x00 << 3)
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124 #define SLEEP_RST_EXT (0x01 << 3)
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125 #define SLEEP_RST_WDT (0x02 << 3)
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127 #define SLEEP_MODE_PM0 (0x00)
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128 #define SLEEP_MODE_PM1 (0x01)
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129 #define SLEEP_MODE_PM2 (0x02)
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130 #define SLEEP_MODE_PM3 (0x03)
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133 // CLKCON (0xC6) - Clock Control
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134 #define CLKCON_OSC32 0x80 // bit mask, for the slow 32k clock oscillator
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135 #define CLKCON_OSC 0x40 // bit mask, for the system clock oscillator
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136 #define CLKCON_TICKSPD 0x38 // bit mask, for timer ticks output setting
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137 #define CLKCON_TICKSPD0 0x08 // bit mask, for timer ticks output setting
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138 #define CLKCON_TICKSPD1 0x10 // bit mask, for timer ticks output setting
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139 #define CLKCON_TICKSPD2 0x20 // bit mask, for timer ticks output setting
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140 #define CLKCON_CLKSPD 0x07 // bit mask, for the clock speed
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141 #define CLKCON_CLKSPD0 0x01 // bit mask, for the clock speed
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142 #define CLKCON_CLKSPD1 0x02 // bit mask, for the clock speed
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143 #define CLKCON_CLKSPD2 0x04 // bit mask, for the clock speed
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145 #define TICKSPD_DIV_1 (0x00 << 3)
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146 #define TICKSPD_DIV_2 (0x01 << 3)
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147 #define TICKSPD_DIV_4 (0x02 << 3)
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148 #define TICKSPD_DIV_8 (0x03 << 3)
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149 #define TICKSPD_DIV_16 (0x04 << 3)
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150 #define TICKSPD_DIV_32 (0x05 << 3)
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151 #define TICKSPD_DIV_64 (0x06 << 3)
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152 #define TICKSPD_DIV_128 (0x07 << 3)
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154 #define CLKSPD_DIV_1 (0x00)
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155 #define CLKSPD_DIV_2 (0x01)
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156 #define CLKSPD_DIV_4 (0x02)
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157 #define CLKSPD_DIV_8 (0x03)
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158 #define CLKSPD_DIV_16 (0x04)
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159 #define CLKSPD_DIV_32 (0x05)
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160 #define CLKSPD_DIV_64 (0x06)
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161 #define CLKSPD_DIV_128 (0x07)
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165 /*******************************************************************************
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169 // FCTL (0xAE) - Flash Control
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170 #define FCTL_BUSY 0x80
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171 #define FCTL_SWBSY 0x40
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172 #define FCTL_CONTRD 0x10
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173 #define FCTL_WRITE 0x02
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174 #define FCTL_ERASE 0x01
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177 // FWDATA (0xAF) - Flash Write Data
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179 // FADDRH (0xAD) - Flash Address High Byte
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181 // FADDRL (0xAC) - Flash Address Low Byte
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183 // FWT (0xAB) - Flash Write Timing (Only bit 0-5 R/W)
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186 /*******************************************************************************
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190 // P0 (0x80) - Port 0 - bit accessible SFR register
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192 // P1 (0x90) - Port 1 - bit accessible SFR register
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194 // P2 (0xA0) - Port 2 - bit accessible SFR register
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196 // PERCFG (0xF1) - Peripheral Control
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197 #define PERCFG_T1CFG 0x40
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198 #define PERCFG_T3CFG 0x20
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199 #define PERCFG_T4CFG 0x10
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200 #define PERCFG_U1CFG 0x02
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201 #define PERCFG_U0CFG 0x01
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205 // ADCCFG (0xF2) - ADC input Configuration
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206 #define ADCCFG_7 0x80
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207 #define ADCCFG_6 0x40
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208 #define ADCCFG_5 0x20
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209 #define ADCCFG_4 0x10
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210 #define ADCCFG_3 0x08
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211 #define ADCCFG_2 0x04
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212 #define ADCCFG_1 0x02
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213 #define ADCCFG_0 0x01
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216 // P0SEL (0xF3) - Port 0 Function Select (bit 7 not used)
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218 // P1SEL (0xF4) - Port 1 Function Select
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220 // P2SEL (0xF5) - Port 2 Function Select
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221 #define P2SEL_PRI3P1 0x40
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222 #define P2SEL_PRI2P1 0x20
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223 #define P2SEL_PRI1P1 0x10
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224 #define P2SEL_PRI0P1 0x08
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225 #define P2SEL_SELP2_4 0x04
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226 #define P2SEL_SELP2_3 0x02
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227 #define P2SEL_SELP2_0 0x01
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230 // P0DIR (0xFD) - Port 0 Direction Select
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232 // P1DIR (0xFE) - Port 1 Direction Select
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234 // P2DIR (0xFF) - Port 2 Direction
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235 #define P2DIR_PRIP0 0xC0
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236 #define P2DIR_0PRIP0 0x40
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237 #define P2DIR_1PRIP0 0x80
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238 #define P2DIR_DIRP2 0x1F
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240 #define P2DIR_PRIP0_0 (0x00 << 6)
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241 #define P2DIR_PRIP0_1 (0x01 << 6)
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242 #define P2DIR_PRIP0_2 (0x02 << 6)
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243 #define P2DIR_PRIP0_3 (0x03 << 6)
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245 #define P2DIR_DIRP2_4 (0x10)
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246 #define P2DIR_DIRP2_3 (0x08)
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247 #define P2DIR_DIRP2_2 (0x04)
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248 #define P2DIR_DIRP2_1 (0x02)
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249 #define P2DIR_DIRP2_0 (0x01)
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253 // P0INP (0x8F) - Port 0 Input Mode (bit 0 & 1 not used)
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255 // P1INP (0xF6) - Port 1 Input Mode (bit 0 & 1 not used)
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257 // P2INP (0xF7) - Port 2 Input Mode
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258 #define P2INP_PDUP2 0x80
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259 #define P2INP_PDUP1 0x40
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260 #define P2INP_PDUP0 0x20
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261 #define P2INP_MDP2 0x1F
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263 #define P2INP_MDP2_0 (0x01)
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264 #define P2INP_MDP2_1 (0x02)
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265 #define P2INP_MDP2_2 (0x04)
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266 #define P2INP_MDP2_3 (0x08)
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267 #define P2INP_MDP2_4 (0x10)
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271 // P0IFG (0x89) - Port 0 Interrupt Status Flag
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273 // P1IFG (0x8A) - Port 1 Interrupt Status Flag
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275 // P2IFG (0x8B) - Port 2 Interrupt Status Flag (bit 7 - 5 not used)
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277 // PICTL (0x8C) - Port Interrupt Control
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278 #define PICTL_PADSC 0x40
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279 #define PICTL_P2IEN 0x20
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280 #define PICTL_P0IENH 0x10
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281 #define PICTL_P0IENL 0x08
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282 #define PICTL_P2ICON 0x04
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283 #define PICTL_P1ICON 0x02
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284 #define PICTL_P0ICON 0x01
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287 // P1IEN (0x8D) - Port 1 Interrupt Mask
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291 /*******************************************************************************
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295 // DMAARM (0xD6) - DMA Channel Arm
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296 #define DMAARM_ABORT 0x80
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297 #define DMAARM4 0x10
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298 #define DMAARM3 0x08
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299 #define DMAARM2 0x04
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300 #define DMAARM1 0x02
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301 #define DMAARM0 0x01
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304 // DMAREQ (0xD7) - DMA Channel Start Request and Status
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305 #define DMAREQ4 0x10
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306 #define DMAREQ3 0x08
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307 #define DMAREQ2 0x04
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308 #define DMAREQ1 0x02
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309 #define DMAREQ0 0x01
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312 // DMA0CFGH (0xD5) - DMA Channel 0 Configuration Address High Byte
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314 // DMA0CFGL (0xD4) - DMA Channel 0 Configuration Address Low Byte
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316 // DMA1CFGH (0xD3) - DMA Channel 1 - 4 Configuration Address High By
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318 // DMA1CFGL (0xD2) - DMA Channel 1 - 4 Configuration Address Low Byte
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320 // DMAIRQ (0xD1) - DMA Interrupt Flag
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321 #define DMAIRQ_DMAIF4 0x10
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322 #define DMAIRQ_DMAIF3 0x08
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323 #define DMAIRQ_DMAIF2 0x04
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324 #define DMAIRQ_DMAIF1 0x02
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325 #define DMAIRQ_DMAIF0 0x01
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328 // T1CNTH (0xE3) - Timer 1 Counter High
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330 // T1CNTL (0xE2) - Timer 1 Counter Low
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332 // T1CTL (0xE4) - Timer 1 Control and Status
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333 #define T1CTL_CH2IF 0x80 // Timer 1 channel 2 interrupt flag
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334 #define T1CTL_CH1IF 0x40 // Timer 1 channel 1 interrupt flag
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335 #define T1CTL_CH0IF 0x20 // Timer 1 channel 0 interrupt flag
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336 #define T1CTL_OVFIF 0x10 // Timer 1 counter overflow interrupt flag
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337 #define T1CTL_DIV 0x0C
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338 #define T1CTL_DIV0 0x04
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339 #define T1CTL_DIV1 0x08
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340 #define T1CTL_MODE 0x03
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341 #define T1CTL_MODE0 0x01
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342 #define T1CTL_MODE1 0x02
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344 #define T1CTL_DIV_1 (0x00 << 2) // Divide tick frequency by 1
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345 #define T1CTL_DIV_8 (0x01 << 2) // Divide tick frequency by 8
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346 #define T1CTL_DIV_32 (0x02 << 2) // Divide tick frequency by 32
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347 #define T1CTL_DIV_128 (0x03 << 2) // Divide tick frequency by 128
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349 #define T1CTL_MODE_SUSPEND (0x00) // Operation is suspended (halt)
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350 #define T1CTL_MODE_FREERUN (0x01) // Free Running mode
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351 #define T1CTL_MODE_MODULO (0x02) // Modulo
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352 #define T1CTL_MODE_UPDOWN (0x03) // Up/down
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355 // T1CCTL0 (0xE5) - Timer 1 Channel 0 Capture/Compare Control
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356 #define T1CCTL0_CPSEL 0x80 // Timer 1 channel 0 capture select
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357 #define T1CCTL0_IM 0x40 // Channel 0 Interrupt mask
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358 #define T1CCTL0_CMP 0x38
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359 #define T1CCTL0_CMP0 0x08
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360 #define T1CCTL0_CMP1 0x10
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361 #define T1CCTL0_CMP2 0x20
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362 #define T1CCTL0_MODE 0x04 // Capture or compare mode
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363 #define T1CCTL0_CAP 0x03
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364 #define T1CCTL0_CAP0 0x01
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365 #define T1CCTL0_CAP1 0x02
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367 #define T1C0_SET_ON_CMP (0x00 << 3) // Clear output on compare-up set on 0
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368 #define T1C0_CLR_ON_CMP (0x01 << 3) // Set output on compare-up clear on 0
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369 #define T1C0_TOG_ON_CMP (0x02 << 3) // Toggle output on compare
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370 #define T1C0_SET_CMP_UP_CLR_0 (0x03 << 3) // Clear output on compare
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371 #define T1C0_CLR_CMP_UP_SET_0 (0x04 << 3) // Set output on compare
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373 #define T1C0_NO_CAP (0x00) // No capture
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374 #define T1C0_RISE_EDGE (0x01) // Capture on rising edge
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375 #define T1C0_FALL_EDGE (0x02) // Capture on falling edge
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376 #define T1C0_BOTH_EDGE (0x03) // Capture on both edges
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379 // T1CC0H (0xDB) - Timer 1 Channel 0 Capture/Compare Value High
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381 // T1CC0L (0xDA) - Timer 1 Channel 0 Capture/Compare Value Low
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383 // T1CCTL1 (0xE6) - Timer 1 Channel 1 Capture/Compare Control
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384 #define T1CCTL1_CPSEL 0x80 // Timer 1 channel 1 capture select
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385 #define T1CCTL1_IM 0x40 // Channel 1 Interrupt mask
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386 #define T1CCTL1_CMP 0x38
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387 #define T1CCTL1_CMP0 0x08
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388 #define T1CCTL1_CMP1 0x10
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389 #define T1CCTL1_CMP2 0x20
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390 #define T1CCTL1_MODE 0x04 // Capture or compare mode
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391 #define T1CCTL1_DSM_SPD 0x04
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392 #define T1CCTL1_CAP 0x03
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393 #define T1CCTL1_CAP0 0x01
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394 #define T1CCTL1_CAP1 0x02
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396 #define T1C1_SET_ON_CMP (0x00 << 3) // Set output on compare
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397 #define T1C1_CLR_ON_CMP (0x01 << 3) // Clear output on compare
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398 #define T1C1_TOG_ON_CMP (0x02 << 3) // Toggle output on compare
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399 #define T1C1_SET_CMP_UP_CLR_0 (0x03 << 3) // Set output on compare-up clear on 0
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400 #define T1C1_CLR_CMP_UP_SET_0 (0x04 << 3) // Clear output on compare-up set on 0
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401 #define T1C1_SET_C1_CLR_C0 (0x05 << 3) // Set when equal to T1CC1, clear when equal to T1CC0
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402 #define T1C1_CLR_C1_SET_C0 (0x06 << 3) // Clear when equal to T1CC1, set when equal to T1CC0
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403 #define T1C1_DSM_MODE (0x07 << 3) // DSM mode
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405 #define T1C1_NO_CAP (0x00) // No capture
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406 #define T1C1_RISE_EDGE (0x01) // Capture on rising edge
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407 #define T1C1_FALL_EDGE (0x02) // Capture on falling edge
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408 #define T1C1_BOTH_EDGE (0x03) // Capture on both edges
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410 #define DSM_IP_ON_OS_ON (0x00) // Interpolator & output shaping enabled
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411 #define DSM_IP_ON_OS_OFF (0x01) // Interpolator enabled & output shaping disabled
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412 #define DSM_IP_OFF_OS_ON (0x02) // Interpolator disabled & output shaping enabled
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413 #define DSM_IP_OFF_OS_OFF (0x03) // Interpolator & output shaping disabled
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417 // T1CC1H (0xDD) - Timer 1 Channel 1 Capture/Compare Value High
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419 // T1CC1L (0xDC) - Timer 1 Channel 1 Capture/Compare Value Low
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421 // T1CCTL2 (0xE7) - Timer 1 Channel 2 Capture/Compare Control
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422 #define T1CCTL2_CPSEL 0x80 // Timer 1 channel 2 capture select
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423 #define T1CCTL2_IM 0x40 // Channel 2 Interrupt mask
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424 #define T1CCTL2_CMP 0x38
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425 #define T1CCTL2_CMP0 0x08
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426 #define T1CCTL2_CMP1 0x10
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427 #define T1CCTL2_CMP2 0x20
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428 #define T1CCTL2_MODE 0x04 // Capture or compare mode
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429 #define T1CCTL2_CAP 0x03
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430 #define T1CCTL2_CAP0 0x01
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431 #define T1CCTL2_CAP1 0x02
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433 #define T1C2_SET_ON_CMP (0x00 << 3) // Set output on compare
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434 #define T1C2_CLR_ON_CMP (0x01 << 3) // Clear output on compare
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435 #define T1C2_TOG_ON_CMP (0x02 << 3) // Toggle output on compare
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436 #define T1C2_SET_CMP_UP_CLR_0 (0x03 << 3) // Set output on compare-up clear on 0
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437 #define T1C2_CLR_CMP_UP_SET_0 (0x04 << 3) // Clear output on compare-up set on 0
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438 #define T1C2_SET_C2_CLR_C0 (0x05 << 3) // Set when equal to T1CC2, clear when equal to T1CC0
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439 #define T1C2_CLR_C2_SET_C0 (0x06 << 3) // Clear when equal to T1CC2, set when equal to T1CC0
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441 #define T1C2_NO_CAP (0x00) // No capture
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442 #define T1C2_RISE_EDGE (0x01) // Capture on rising edge
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443 #define T1C2_FALL_EDGE (0x02) // Capture on falling edge
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444 #define T1C2_BOTH_EDGE (0x03) // Capture on both edges
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447 // T1CC2H (0xDF) - Timer 1 Channel 2 Capture/Compare Value High
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449 // T1CC2L (0xDE) - Timer 1 Channel 2 Capture/Compare Value Low
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451 // T2CTL (0x9E) - Timer 2 Control
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452 #define T2CTL_TEX 0x40
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453 #define T2CTL_INT 0x10 // Enable Timer 2 interrupt
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454 #define T2CTL_TIG 0x04 // Tick generator mode
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455 #define T2CTL_TIP 0x03
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456 #define T2CTL_TIP0 0x01
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457 #define T2CTL_TIP1 0x02
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459 #define T2CTL_TIP_64 (0x00)
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460 #define T2CTL_TIP_128 (0x01)
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461 #define T2CTL_TIP_256 (0x02)
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462 #define T2CTL_TIP_1024 (0x03)
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465 // T2CT (0x9C) - Timer 2 Count
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467 // T2PR (0x9D) - Timer 2 Prescaler
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469 // WORTIME0 (0xA5) - Sleep Timer Low Byte
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471 // WORTIME1 (0xA6) - Sleep Timer High Byte
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473 // WOREVT1 (0xA4) - Sleep Timer Event0 Timeout High
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475 // WOREVT0 (0xA3) - Sleep Timer Event0 Timeout Low
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477 // WORCTL (0xA2) - Sleep Timer Control
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478 #define WORCTL_WOR_RESET 0x04
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479 #define WORCTL_WOR_RES 0x03
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480 #define WORCTL_WOR_RES0 0x01
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481 #define WORCTL_WOR_RES1 0x02
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483 #define WORCTL_WOR_RES_1 (0x00)
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484 #define WORCTL_WOR_RES_32 (0x01)
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485 #define WORCTL_WOR_RES_1024 (0x02)
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486 #define WORCTL_WOR_RES_32768 (0x03)
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489 // WORIRQ (0xA1) - Sleep Timer Interrupt Control
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490 #define WORIRQ_EVENT0_MASK 0x10
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491 #define WORIRQ_EVENT0_FLAG 0x01
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494 // T3CNT (0xCA) - Timer 3 Counter
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496 // T3CTL (0xCB) - Timer 3 Control
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497 #define T3CTL_DIV 0xE0
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498 #define T3CTL_DIV0 0x20
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499 #define T3CTL_DIV1 0x40
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500 #define T3CTL_DIV2 0x80
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501 #define T3CTL_START 0x10
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502 #define T3CTL_OVFIM 0x08
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503 #define T3CTL_CLR 0x04
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504 #define T3CTL_MODE 0x03
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505 #define T3CTL_MODE0 0x01
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506 #define T3CTL_MODE1 0x02
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508 #define T3CTL_DIV_1 (0x00 << 5)
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509 #define T3CTL_DIV_2 (0x01 << 5)
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510 #define T3CTL_DIV_4 (0x02 << 5)
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511 #define T3CTL_DIV_8 (0x03 << 5)
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512 #define T3CTL_DIV_16 (0x04 << 5)
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513 #define T3CTL_DIV_32 (0x05 << 5)
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514 #define T3CTL_DIV_64 (0x06 << 5)
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515 #define T3CTL_DIV_128 (0x07 << 5)
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517 #define T3CTL_MODE_FREERUN (0x00)
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518 #define T3CTL_MODE_DOWN (0x01)
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519 #define T3CTL_MODE_MODULO (0x02)
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520 #define T3CTL_MODE_UPDOWN (0x03)
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524 // T3CCTL0 (0xCC) - Timer 3 Channel 0 Compare Control
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525 #define T3CCTL0_IM 0x40
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526 #define T3CCTL0_MODE 0x04
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527 #define T3CCTL0_CMP 0x38
\r
528 #define T3CCTL0_CMP0 0x08
\r
529 #define T3CCTL0_CMP1 0x10
\r
530 #define T3CCTL0_CMP2 0x20
\r
532 #define T3C0_SET_ON_CMP (0x00 << 3) // Set output on compare
\r
533 #define T3C0_CLR_ON_CMP (0x01 << 3) // Clear output on compare
\r
534 #define T3C0_TOG_ON_CMP (0x02 << 3) // Toggle output on compare
\r
535 #define T3C0_SET_CMP_UP_CLR_0 (0x03 << 3) // Set output on compare-up clear on 0
\r
536 #define T3C0_CLR_CMP_UP_SET_0 (0x04 << 3) // Clear output on compare-up set on 0
\r
537 #define T3C0_SET_CMP_CLR_255 (0x05 << 3) // Set when equal to T3CC0, clear on 255
\r
538 #define T3C0_CLR_CMP_SET_0 (0x06 << 3) // Clear when equal to T3CC0, set on 0
\r
542 // T3CC0 (0xCD) - Timer 3 Channel 0 Compare Value
\r
544 // T3CCTL1 (0xCE) - Timer 3 Channel 1 Compare Control
\r
546 #define T3CCTL1_IM 0x40
\r
547 #define T3CCTL1_MODE 0x04
\r
548 #define T3CCTL1_CMP 0x38
\r
549 #define T3CCTL1_CMP0 0x08
\r
550 #define T3CCTL1_CMP1 0x10
\r
551 #define T3CCTL1_CMP2 0x20
\r
553 #define T3C1_SET_ON_CMP (0x00 << 3) // Set output on compare
\r
554 #define T3C1_CLR_ON_CMP (0x01 << 3) // Clear output on compare
\r
555 #define T3C1_TOG_ON_CMP (0x02 << 3) // Toggle output on compare
\r
556 #define T3C1_SET_CMP_UP_CLR_0 (0x03 << 3) // Set output on compare-up clear on 0
\r
557 #define T3C1_CLR_CMP_UP_SET_0 (0x04 << 3) // Clear output on compare-up set on 0
\r
558 #define T3C1_SET_CMP_CLR_C0 (0x05 << 3) // Set when equal to T3CC1, clear when equal to T3CC0
\r
559 #define T3C1_CLR_CMP_SET_C0 (0x06 << 3) // Clear when equal to T3CC1, set when equal to T3CC0
\r
562 // T3CC1 (0xCF) - Timer 3 Channel 1 Compare Value
\r
564 // T4CNT (0xEA) - Timer 4 Counter
\r
566 // T4CTL (0xEB) - Timer 4 Control
\r
567 #define T4CTL_DIV 0xE0
\r
568 #define T4CTL_DIV0 0x20
\r
569 #define T4CTL_DIV1 0x40
\r
570 #define T4CTL_DIV2 0x80
\r
571 #define T4CTL_START 0x10
\r
572 #define T4CTL_OVFIM 0x08
\r
573 #define T4CTL_CLR 0x04
\r
574 #define T4CTL_MODE 0x03
\r
575 #define T4CTL_MODE0 0x01
\r
576 #define T4CTL_MODE1 0x02
\r
578 #define T4CTL_MODE_FREERUN (0x00)
\r
579 #define T4CTL_MODE_DOWN (0x01)
\r
580 #define T4CTL_MODE_MODULO (0x02)
\r
581 #define T4CTL_MODE_UPDOWN (0x03)
\r
583 #define T4CTL_DIV_1 (0x00 << 5)
\r
584 #define T4CTL_DIV_2 (0x01 << 5)
\r
585 #define T4CTL_DIV_4 (0x02 << 5)
\r
586 #define T4CTL_DIV_8 (0x03 << 5)
\r
587 #define T4CTL_DIV_16 (0x04 << 5)
\r
588 #define T4CTL_DIV_32 (0x05 << 5)
\r
589 #define T4CTL_DIV_64 (0x06 << 5)
\r
590 #define T4CTL_DIV_128 (0x07 << 5)
\r
593 // T4CCTL0 (0xEC) - Timer 4 Channel 0 Compare Control
\r
594 #define T4CCTL0_IM 0x40
\r
595 #define T4CCTL0_CMP 0x38
\r
596 #define T4CCTL0_CMP0 0x08
\r
597 #define T4CCTL0_CMP1 0x10
\r
598 #define T4CCTL0_CMP2 0x20
\r
599 #define T4CCTL0_MODE 0x04
\r
601 #define T4CCTL0_SET_ON_CMP (0x00 << 3)
\r
602 #define T4CCTL0_CLR_ON_CMP (0x01 << 3)
\r
603 #define T4CCTL0_TOG_ON_CMP (0x02 << 3)
\r
604 #define T4CCTL0_SET_CMP_UP_CLR_0 (0x03 << 3)
\r
605 #define T4CCTL0_CLR_CMP_UP_SET_0 (0x04 << 3)
\r
606 #define T4CCTL0_SET_CMP_CLR_255 (0x05 << 3)
\r
607 #define T4CCTL0_CLR_CMP_SET_0 (0x06 << 3)
\r
610 // T4CC0 (0xED) - Timer 4 Channel 0 Compare Value
\r
612 // T4CCTL1 (0xEE) - Timer 4 Channel 1 Compare Control
\r
613 #define T4CCTL1_IM 0x40
\r
614 #define T4CCTL1_CMP 0x38
\r
615 #define T4CCTL1_CMP0 0x08
\r
616 #define T4CCTL1_CMP1 0x10
\r
617 #define T4CCTL1_CMP2 0x20
\r
618 #define T4CCTL1_MODE 0x04
\r
620 #define T4CCTL1_SET_ON_CMP (0x00 << 3)
\r
621 #define T4CCTL1_CLR_ON_CMP (0x01 << 3)
\r
622 #define T4CCTL1_TOG_ON_CMP (0x02 << 3)
\r
623 #define T4CCTL1_SET_CMP_UP_CLR_0 (0x03 << 3)
\r
624 #define T4CCTL1_CLR_CMP_UP_SET_0 (0x04 << 3)
\r
625 #define T4CCTL1_SET_CMP_CLR_C0 (0x05 << 3)
\r
626 #define T4CCTL1_CLR_CMP_SET_C0 (0x06 << 3)
\r
629 // TIMIF (0xD8) - Timers 1/3/4 Interrupt Mask/Flag - bit accessible SFR register
\r
632 /*******************************************************************************
\r
636 // ADCL (0xBA) - ADC Data Low (only bit 7-4 used)
\r
638 // ADCH (0xBB) - ADC Data High
\r
640 // ADCCON1 (0xB4) - ADC Control 1
\r
641 #define ADCCON1_EOC 0x80
\r
642 #define ADCCON1_ST 0x40
\r
643 #define ADCCON1_STSEL 0x30
\r
644 #define ADCCON1_STSEL0 0x10
\r
645 #define ADCCON1_STSEL1 0x20
\r
646 #define ADCCON1_RCTRL 0x0C
\r
647 #define ADCCON1_RCTRL0 0x04
\r
648 #define ADCCON1_RCTRL1 0x08
\r
650 #define STSEL_P2_0 (0x00 << 4)
\r
651 #define STSEL_FULL_SPEED (0x01 << 4)
\r
652 #define STSEL_T1C0_CMP_EVT (0x02 << 4)
\r
653 #define STSEL_ST (0x03 << 4)
\r
655 #define ADCCON1_RCTRL_COMPL (0x00 << 2)
\r
656 #define ADCCON1_RCTRL_LFSR13 (0x01 << 2)
\r
660 // ADCCON2 (0xB5) - ADC Control 2
\r
661 #define ADCCON2_SREF 0xC0
\r
662 #define ADCCON2_SREF0 0x40
\r
663 #define ADCCON2_SREF1 0x80
\r
664 #define ADCCON2_SDIV 0x30
\r
665 #define ADCCON2_SDIV0 0x10
\r
666 #define ADCCON2_SDIV1 0x20
\r
667 #define ADCCON2_SCH 0x0F
\r
668 #define ADCCON2_SCH0 0x01
\r
669 #define ADCCON2_SCH1 0x02
\r
670 #define ADCCON2_SCH2 0x04
\r
671 #define ADCCON2_SCH3 0x08
\r
673 #define ADCCON2_SREF_1_25V (0x00 << 6)
\r
674 #define ADCCON2_SREF_P0_7 (0x01 << 6)
\r
675 #define ADCCON2_SREF_AVDD (0x02 << 6)
\r
676 #define ADCCON2_SREF_P0_6_P0_7 (0x03 << 6)
\r
678 #define ADCCON2_SDIV_64 (0x00 << 4)
\r
679 #define ADCCON2_SDIV_128 (0x01 << 4)
\r
680 #define ADCCON2_SDIV_256 (0x02 << 4)
\r
681 #define ADCCON2_SDIV_512 (0x03 << 4)
\r
683 #define ADCCON2_SCH_AIN0 (0x00)
\r
684 #define ADCCON2_SCH_AIN1 (0x01)
\r
685 #define ADCCON2_SCH_AIN2 (0x02)
\r
686 #define ADCCON2_SCH_AIN3 (0x03)
\r
687 #define ADCCON2_SCH_AIN4 (0x04)
\r
688 #define ADCCON2_SCH_AIN5 (0x05)
\r
689 #define ADCCON2_SCH_AIN6 (0x06)
\r
690 #define ADCCON2_SCH_AIN7 (0x07)
\r
691 #define ADCCON2_SCH_AIN0_1 (0x08)
\r
692 #define ADCCON2_SCH_AIN2_3 (0x09)
\r
693 #define ADCCON2_SCH_AIN4_5 (0x0A)
\r
694 #define ADCCON2_SCH_AIN6_7 (0x0B)
\r
695 #define ADCCON2_SCH_GND (0x0C)
\r
696 #define ADCCON2_SCH_POSVOL (0x0D)
\r
697 #define ADCCON2_SCH_TEMPR (0x0E)
\r
698 #define ADCCON2_SCH_VDD_3 (0x0F)
\r
701 // ADCCON3 (0xB6) - ADC Control 3
\r
702 #define ADCCON3_EREF 0xC0
\r
703 #define ADCCON3_EREF0 0x40
\r
704 #define ADCCON3_EREF1 0x80
\r
705 #define ADCCON3_EDIV 0x30
\r
706 #define ADCCON3_EDIV0 0x10
\r
707 #define ADCCON3_EDIV1 0x20
\r
708 #define ADCCON2_ECH 0x0F
\r
709 #define ADCCON2_ECH0 0x01
\r
710 #define ADCCON2_ECH1 0x02
\r
711 #define ADCCON2_ECH2 0x04
\r
712 #define ADCCON2_ECH3 0x08
\r
714 #define ADCCON3_EREF_1_25V (0x00 << 6)
\r
715 #define ADCCON3_EREF_P0_7 (0x01 << 6)
\r
716 #define ADCCON3_EREF_AVDD (0x02 << 6)
\r
717 #define ADCCON3_EREF_P0_6_P0_7 (0x03 << 6)
\r
719 #define ADCCON3_EDIV_64 (0x00 << 4)
\r
720 #define ADCCON3_EDIV_128 (0x01 << 4)
\r
721 #define ADCCON3_EDIV_256 (0x02 << 4)
\r
722 #define ADCCON3_EDIV_512 (0x03 << 4)
\r
724 #define ADCCON3_ECH_AIN0 (0x00)
\r
725 #define ADCCON3_ECH_AIN1 (0x01)
\r
726 #define ADCCON3_ECH_AIN2 (0x02)
\r
727 #define ADCCON3_ECH_AIN3 (0x03)
\r
728 #define ADCCON3_ECH_AIN4 (0x04)
\r
729 #define ADCCON3_ECH_AIN5 (0x05)
\r
730 #define ADCCON3_ECH_AIN6 (0x06)
\r
731 #define ADCCON3_ECH_AIN7 (0x07)
\r
732 #define ADCCON3_ECH_AIN0_1 (0x08)
\r
733 #define ADCCON3_ECH_AIN2_3 (0x09)
\r
734 #define ADCCON3_ECH_AIN4_5 (0x0A)
\r
735 #define ADCCON3_ECH_AIN6_7 (0x0B)
\r
736 #define ADCCON3_ECH_GND (0x0C)
\r
737 #define ADCCON3_ECH_POSVOL (0x0D)
\r
738 #define ADCCON3_ECH_TEMPR (0x0E)
\r
739 #define ADCCON3_ECH_VDD_3 (0x0F)
\r
743 /*******************************************************************************
\r
744 * Random Number Generator
\r
747 // RNDL (0xBC) - Random Number Generator Data Low Byte
\r
749 // RNDH (0xBD) - Random Number Generator Data High Byte
\r
752 /*******************************************************************************
\r
756 // ENCCS (0xB3) - Encryption Control and Status
\r
757 #define ENCCS_MODE 0x70
\r
758 #define ENCCS_MODE0 0x10
\r
759 #define ENCCS_MODE1 0x20
\r
760 #define ENCCS_MODE2 0x40
\r
761 #define ENCCS_RDY 0x08
\r
762 #define ENCCS_CMD 0x06
\r
763 #define ENCCS_CMD0 0x02
\r
764 #define ENCCS_CMD1 0x04
\r
765 #define ENCCS_ST 0x01
\r
767 #define ENCCS_MODE_CBC (0x00 << 4)
\r
768 #define ENCCS_MODE_CFB (0x01 << 4)
\r
769 #define ENCCS_MODE_OFB (0x02 << 4)
\r
770 #define ENCCS_MODE_CTR (0x03 << 4)
\r
771 #define ENCCS_MODE_ECB (0x04 << 4)
\r
772 #define ENCCS_MODE_CBCMAC (0x05 << 4)
\r
774 #define ENCCS_CMD_ENC (0x00 << 1)
\r
775 #define ENCCS_CMD_DEC (0x01 << 1)
\r
776 #define ENCCS_CMD_LDKEY (0x02 << 1)
\r
777 #define ENCCS_CMD_LDIV (0x03 << 1)
\r
780 // ENCDI (0xB1) - Encryption Input Data
\r
782 // ENCDO (0xB2) - Encryption Output Data
\r
785 /*******************************************************************************
\r
789 // WDCTL (0xC9) - Watchdog Timer Control
\r
790 #define WDCTL_CLR 0xF0
\r
791 #define WDCTL_CLR0 0x10
\r
792 #define WDCTL_CLR1 0x20
\r
793 #define WDCTL_CLR2 0x40
\r
794 #define WDCTL_CLR3 0x80
\r
795 #define WDCTL_EN 0x08
\r
796 #define WDCTL_MODE 0x04
\r
797 #define WDCTL_INT 0x03
\r
798 #define WDCTL_INT0 0x01
\r
799 #define WDCTL_INT1 0x02
\r
802 #define WDCTL_INT_SEC_1 (0x00)
\r
803 #define WDCTL_INT1_MSEC_250 (0x01)
\r
804 #define WDCTL_INT2_MSEC_15 (0x02)
\r
805 #define WDCTL_INT3_MSEC_2 (0x03)
\r
809 /*******************************************************************************
\r
813 // U0CSR (0x86) - USART 0 Control and Status
\r
815 #define U0CSR_MODE 0x80
\r
816 #define U0CSR_RE 0x40
\r
817 #define U0CSR_SLAVE 0x20
\r
818 #define U0CSR_FE 0x10
\r
819 #define U0CSR_ERR 0x08
\r
820 #define U0CSR_RX_BYTE 0x04
\r
821 #define U0CSR_TX_BYTE 0x02
\r
822 #define U0CSR_ACTIVE 0x01
\r
825 // U0UCR (0xC4) - USART 0 UART Control
\r
826 #define U0UCR_FLUSH 0x80
\r
827 #define U0UCR_FLOW 0x40
\r
828 #define U0UCR_D9 0x20
\r
829 #define U0UCR_BIT9 0x10
\r
830 #define U0UCR_PARITY 0x08
\r
831 #define U0UCR_SPB 0x04
\r
832 #define U0UCR_STOP 0x02
\r
833 #define U0UCR_START 0x01
\r
836 // U0GCR (0xC5) - USART 0 Generic Control
\r
837 #define U0GCR_CPOL 0x80
\r
838 #define U0GCR_CPHA 0x40
\r
839 #define U0GCR_ORDER 0x20
\r
840 #define U0GCR_BAUD_E 0x1F
\r
841 #define U0GCR_BAUD_E0 0x01
\r
842 #define U0GCR_BAUD_E1 0x02
\r
843 #define U0GCR_BAUD_E2 0x04
\r
844 #define U0GCR_BAUD_E3 0x08
\r
845 #define U0GCR_BAUD_E4 0x10
\r
848 // U0DBUF (0xC1) - USART 0 Receive/Transmit Data Buffer
\r
850 // U0BAUD (0xC2) - USART 0 Baud Rate Control
\r
852 // U1CSR (0xF8) - USART 1 Control and Status - bit accessible SFR register
\r
853 #define U1CSR_MODE 0x80
\r
854 #define U1CSR_RE 0x40
\r
855 #define U1CSR_SLAVE 0x20
\r
856 #define U1CSR_FE 0x10
\r
857 #define U1CSR_ERR 0x08
\r
858 #define U1CSR_RX_BYTE 0x04
\r
859 #define U1CSR_TX_BYTE 0x02
\r
860 #define U1CSR_ACTIVE 0x01
\r
863 // U1UCR (0xFB) - USART 1 UART Control
\r
864 #define U1UCR_FLUSH 0x80
\r
865 #define U1UCR_FLOW 0x40
\r
866 #define U1UCR_D9 0x20
\r
867 #define U1UCR_BIT9 0x10
\r
868 #define U1UCR_PARITY 0x08
\r
869 #define U1UCR_SPB 0x04
\r
870 #define U1UCR_STOP 0x02
\r
871 #define U1UCR_START 0x01
\r
874 // U1GCR (0xFC) - USART 1 Generic Control
\r
875 #define U1GCR_CPOL 0x80
\r
876 #define U1GCR_CPHA 0x40
\r
877 #define U1GCR_ORDER 0x20
\r
878 #define U1GCR_BAUD_E 0x1F
\r
879 #define U1GCR_BAUD_E0 0x01
\r
880 #define U1GCR_BAUD_E1 0x02
\r
881 #define U1GCR_BAUD_E2 0x04
\r
882 #define U1GCR_BAUD_E3 0x08
\r
883 #define U1GCR_BAUD_E4 0x10
\r
886 // U1DBUF (0xF9) - USART 1 Receive/Transmit Data Buffer
\r
888 // U1BAUD (0xFA) - USART 1 Baud Rate Control
\r
891 /*******************************************************************************
\r
895 // 0xDF40: I2SCFG0 - I2S Configuration Register 0
\r
896 #define I2SCFG0_TXIEN 0x80
\r
897 #define I2SCFG0_RXIEN 0x40
\r
898 #define I2SCFG0_ULAWE 0x20
\r
899 #define I2SCFG0_ULAWC 0x10
\r
900 #define I2SCFG0_TXMONO 0x08
\r
901 #define I2SCFG0_RXMONO 0x04
\r
902 #define I2SCFG0_MASTER 0x02
\r
903 #define I2SCFG0_ENAB 0x01
\r
906 // 0xDF41: I2SCFG1 - I2S Configuration Register 1
\r
907 #define I2SCFG1_WORDS 0xF8
\r
908 #define I2SCFG1_WORDS0 0x08
\r
909 #define I2SCFG1_WORDS1 0x10
\r
910 #define I2SCFG1_WORDS2 0x20
\r
911 #define I2SCFG1_WORDS3 0x40
\r
912 #define I2SCFG1_WORDS4 0x80
\r
913 #define I2SCFG1_TRIGNUM 0x06
\r
914 #define I2SCFG1_TRIGNUM0 0x02
\r
915 #define I2SCFG1_TRIGNUM1 0x04
\r
916 #define I2SCFG1_IOLOC 0x01
\r
918 #define I2SCFG1_TRIGNUM_NO_TRIG (0x00 << 1)
\r
919 #define I2SCFG1_TRIGNUM_USB_SOF (0x01 << 1)
\r
920 #define I2SCFG1_TRIGNUM_IOC_1 (0x02 << 1)
\r
921 #define I2SCFG1_TRIGNUM_T1_CH0 (0x03 << 1)
\r
925 // 0xDF42: I2SDATL - I2S Data Low Byte
\r
927 // 0xDF43: I2SDATH - I2S Data High Byte
\r
929 // 0xDF44: I2SWCNT - I2S Word Count Register
\r
931 // 0xDF45: I2SSTAT - I2S Status Register
\r
932 #define I2SSTAT_TXUNF 0x80
\r
933 #define I2SSTAT_RXOVF 0x40
\r
934 #define I2SSTAT_TXLR 0x20
\r
935 #define I2SSTAT_RXLR 0x10
\r
936 #define I2SSTAT_TXIRQ 0x08
\r
937 #define I2SSTAT_RXIRQ 0x04
\r
938 #define I2SSTAT_WCNT 0x03
\r
939 #define I2SSTAT_WCNT0 0x01
\r
940 #define I2SSTAT_WCNT1 0x02
\r
942 #define I2SSTAT_WCNT_10BIT (0x02)
\r
943 #define I2SSTAT_WCNT_9BIT (0x01)
\r
944 #define I2SSTAT_WCNT_9_10BIT (0x02)
\r
947 // 0xDF46: I2SCLKF0 - I2S Clock Configuration Register 0
\r
949 // 0xDF47: I2SCLKF1 - I2S Clock Configuration Register 1
\r
951 // 0xDF48: I2SCLKF2 - I2S Clock Configuration Register 2
\r
956 /*******************************************************************************
\r
960 // RFIF (0xE9) - RF Interrupt Flags
\r
961 #define RFIF_IRQ_TXUNF 0x80
\r
962 #define RFIF_IRQ_RXOVF 0x40
\r
963 #define RFIF_IRQ_TIMEOUT 0x20
\r
964 #define RFIF_IRQ_DONE 0x10
\r
965 #define RFIF_IRQ_CS 0x08
\r
966 #define RFIF_IRQ_PQT 0x04
\r
967 #define RFIF_IRQ_CCA 0x02
\r
968 #define RFIF_IRQ_SFD 0x01
\r
971 // RFIM (0x91) - RF Interrupt Mask
\r
972 #define RFIM_IM_TXUNF 0x80
\r
973 #define RFIM_IM_RXOVF 0x40
\r
974 #define RFIM_IM_TIMEOUT 0x20
\r
975 #define RFIM_IM_DONE 0x10
\r
976 #define RFIM_IM_CS 0x08
\r
977 #define RFIM_IM_PQT 0x04
\r
978 #define RFIM_IM_CCA 0x02
\r
979 #define RFIM_IM_SFD 0x01
\r
982 // 0xDF2F: IOCFG2 - Radio Test Signal Configuration (P1_7)
\r
983 #define IOCFG2_GDO2_INV 0x40
\r
984 #define IOCFG2_GDO2_CFG 0x3F
\r
987 // 0xDF30: IOCFG1 - Radio Test Signal Configuration (P1_6)
\r
988 #define IOCFG1_GDO_DS 0x80
\r
989 #define IOCFG1_GDO1_INV 0x40
\r
990 #define IOCFG1_GDO1_CFG 0x3F
\r
993 // 0xDF31: IOCFG0 - Radio Test Signal Configuration (P1_5)
\r
994 #define IOCFG0_GDO0_INV 0x40
\r
995 #define IOCFG0_GDO0_CFG 0x3F
\r
998 // 0xDF03: PKTCTRL1 - Packet Automation Control
\r
999 #define PKTCTRL1_PQT 0xE0
\r
1000 #define PKTCTRL1_PQT0 0x20
\r
1001 #define PKTCTRL1_PQT1 0x40
\r
1002 #define PKTCTRL1_PQT2 0x80
\r
1003 #define PKTCTRL1_APPEND_STATUS 0x04
\r
1004 #define PKTCTRL1_ADR_CHK 0x03
\r
1005 #define PKTCTRL1_ADR_CHK0 0x01
\r
1006 #define PKTCTRL1_ADR_CHK1 0x02
\r
1008 #define ADR_CHK_NONE (0x00)
\r
1009 #define ADR_CHK_NO_BRDCST (0x01)
\r
1010 #define ADR_CHK_0_BRDCST (0x02)
\r
1011 #define ADR_CHK_0_255_BRDCST (0x03)
\r
1014 // 0xDF04: PKTCTRL0 - Packet Automation Control
\r
1015 #define PKTCTRL0_WHITE_DATA 0x40
\r
1016 #define PKTCTRL0_PKT_FORMAT 0x30
\r
1017 #define PKTCTRL0_PKT_FORMAT0 0x10
\r
1018 #define PKTCTRL0_PKT_FORMAT1 0x20
\r
1019 #define PKTCTRL0_CC2400_EN 0x08
\r
1020 #define PKTCTRL0_CRC_EN 0x04
\r
1021 #define PKTCTRL0_LENGTH_CONFIG 0x03
\r
1022 #define PKTCTRL0_LENGTH_CONFIG0 0x01
\r
1024 #define PKT_FORMAT_NORM (0x00)
\r
1025 #define PKT_FORMAT_RAND (0x02)
\r
1027 #define PKTCTRL0_LENGTH_CONFIG_FIX (0x00)
\r
1028 #define PKTCTRL0_LENGTH_CONFIG_VAR (0x01)
\r
1031 // 0xDF05: ADDR - Device Address
\r
1033 // 0xDF06: CHANNR - Channel Number
\r
1035 // 0xDF07: FSCTRL1 - Frequency Synthesizer Control (only bit 0-4 used)
\r
1037 // 0xDF08: FSCTRL0 - Frequency Synthesizer Control
\r
1039 // 0xDF09: FREQ2 - Frequency Control Word, High Byte
\r
1041 // 0xDF0A: FREQ1 - Frequency Control Word, Middle Byte
\r
1043 // 0xDF0B: FREQ0 - Frequency Control Word, Low Byte
\r
1045 // 0xDF0C: MDMCFG4 - Modem configuration
\r
1047 // 0xDF0D: MDMCFG3 - Modem Configuration
\r
1049 // 0xDF0E: MDMCFG2 - Modem Configuration
\r
1050 #define MDMCFG2_DEM_DCFILT_OFF 0x80
\r
1051 #define MDMCFG2_MOD_FORMAT 0x70
\r
1052 #define MDMCFG2_MOD_FORMAT0 0x10
\r
1053 #define MDMCFG2_MOD_FORMAT1 0x20
\r
1054 #define MDMCFG2_MOD_FORMAT2 0x40
\r
1055 #define MDMCFG2_MANCHESTER_EN 0x08
\r
1056 #define MDMCFG2_SYNC_MODE 0x07
\r
1057 #define MDMCFG2_SYNC_MODE0 0x01
\r
1058 #define MDMCFG2_SYNC_MODE1 0x02
\r
1059 #define MDMCFG2_SYNC_MODE2 0x04
\r
1061 #define MOD_FORMAT_2_FSK (0x00 << 4)
\r
1062 #define MOD_FORMAT_GFSK (0x01 << 4)
\r
1063 #define MOD_FORMAT_MSK (0x07 << 4)
\r
1065 #define SYNC_MODE_NO_PRE (0x00)
\r
1066 #define SYNC_MODE_15_16 (0x01)
\r
1067 #define SYNC_MODE_16_16 (0x02)
\r
1068 #define SYNC_MODE_30_32 (0x03)
\r
1069 #define SYNC_MODE_NO_PRE_CS (0x04) // CS = carrier-sense above threshold
\r
1070 #define SYNC_MODE_15_16_CS (0x05)
\r
1071 #define SYNC_MODE_16_16_CS (0x06)
\r
1072 #define SYNC_MODE_30_32_CS (0x07)
\r
1075 // 0xDF0F: MDMCG1 - Modem Configuration
\r
1076 #define MDMCG1_FEC_EN 0x80
\r
1077 #define MDMCG1_NUM_PREAMBLE 0x70
\r
1078 #define MDMCG1_NUM_PREAMBLE0 0x10
\r
1079 #define MDMCG1_NUM_PREAMBLE1 0x20
\r
1080 #define MDMCG1_NUM_PREAMBLE2 0x40
\r
1081 #define MDMCG1_CHANSPC_E 0x03
\r
1082 #define MDMCG1_CHANSPC_E0 0x01
\r
1083 #define MDMCG1_CHANSPC_E1 0x02
\r
1085 #define MDMCG1_NUM_PREAMBLE_2 (0x00 << 4)
\r
1086 #define MDMCG1_NUM_PREAMBLE_3 (0x01 << 4)
\r
1087 #define MDMCG1_NUM_PREAMBLE_4 (0x02 << 4)
\r
1088 #define MDMCG1_NUM_PREAMBLE_6 (0x03 << 4)
\r
1089 #define MDMCG1_NUM_PREAMBLE_8 (0x04 << 4)
\r
1090 #define MDMCG1_NUM_PREAMBLE_12 (0x05 << 4)
\r
1091 #define MDMCG1_NUM_PREAMBLE_16 (0x06 << 4)
\r
1092 #define MDMCG1_NUM_PREAMBLE_24 (0x07 << 4)
\r
1095 // 0xDF10: MDMCFG0 - Modem Configuration
\r
1097 // 0xDF11: DEVIATN - Modem Deviation Setting
\r
1098 #define DEVIATN_DEVIATION_E 0x70
\r
1099 #define DEVIATN_DEVIATION_E0 0x10
\r
1100 #define DEVIATN_DEVIATION_E1 0x20
\r
1101 #define DEVIATN_DEVIATION_E2 0x40
\r
1102 #define DEVIATN_DEVIATION_M 0x07
\r
1103 #define DEVIATN_DEVIATION_M0 0x01
\r
1104 #define DEVIATN_DEVIATION_M1 0x02
\r
1105 #define DEVIATN_DEVIATION_M2 0x04
\r
1108 // 0xDF12: MCSM2 - Main Radio Control State Machine Configuration
\r
1109 #define MCSM2_RX_TIME_RSSI 0x10
\r
1110 #define MCSM2_RX_TIME_QUAL 0x08
\r
1111 #define MCSM2_RX_TIME 0x07
\r
1114 // 0xDF13: MCSM1 - Main Radio Control State Machine Configuration
\r
1115 #define MCSM1_CCA_MODE 0x30
\r
1116 #define MCSM1_CCA_MODE0 0x10
\r
1117 #define MCSM1_CCA_MODE1 0x20
\r
1118 #define MCSM1_RXOFF_MODE 0x0C
\r
1119 #define MCSM1_RXOFF_MODE0 0x04
\r
1120 #define MCSM1_RXOFF_MODE1 0x08
\r
1121 #define MCSM1_TXOFF_MODE 0x03
\r
1122 #define MCSM1_TXOFF_MODE0 0x01
\r
1123 #define MCSM1_TXOFF_MODE1 0x02
\r
1125 #define MCSM1_CCA_MODE_ALWAYS (0x00 << 4)
\r
1126 #define MCSM1_CCA_MODE_RSSI0 (0x01 << 4)
\r
1127 #define MCSM1_CCA_MODE_PACKET (0x02 << 4)
\r
1128 #define MCSM1_CCA_MODE_RSSI1 (0x03 << 4)
\r
1130 #define MCSM1_RXOFF_MODE_IDLE (0x00 << 2)
\r
1131 #define MCSM1_RXOFF_MODE_FSTXON (0x01 << 2)
\r
1132 #define MCSM1_RXOFF_MODE_TX (0x02 << 2)
\r
1133 #define MCSM1_RXOFF_MODE_RX (0x03 << 2)
\r
1135 #define MCSM1_TXOFF_MODE_IDLE (0x00 << 0)
\r
1136 #define MCSM1_TXOFF_MODE_FSTXON (0x01 << 0)
\r
1137 #define MCSM1_TXOFF_MODE_TX (0x02 << 0)
\r
1138 #define MCSM1_TXOFF_MODE_RX (0x03 << 0)
\r
1141 // 0xDF14: MCSM0 - Main Radio Control State Machine Configuration
\r
1142 #define MCSM0_FS_AUTOCAL 0x30
\r
1144 #define FS_AUTOCAL_NEVER (0x00 << 4)
\r
1145 #define FS_AUTOCAL_FROM_IDLE (0x01 << 4)
\r
1146 #define FS_AUTOCAL_TO_IDLE (0x02 << 4)
\r
1147 #define FS_AUTOCAL_4TH_TO_IDLE (0x03 << 4)
\r
1150 // 0xDF15: FOCCFG - Frequency Offset Compensation Configuration
\r
1151 #define FOCCFG_FOC_BS_CS_GATE 0x20
\r
1152 #define FOCCFG_FOC_PRE_K 0x18
\r
1153 #define FOCCFG_FOC_PRE_K0 0x08
\r
1154 #define FOCCFG_FOC_PRE_K1 0x10
\r
1155 #define FOCCFG_FOC_POST_K 0x04
\r
1156 #define FOCCFG_FOC_LIMIT 0x03
\r
1157 #define FOCCFG_FOC_LIMIT0 0x01
\r
1158 #define FOCCFG_FOC_LIMIT1 0x02
\r
1160 #define FOC_PRE_K_1K (0x00 << 3)
\r
1161 #define FOC_PRE_K_2K (0x02 << 3)
\r
1162 #define FOC_PRE_K_3K (0x03 << 3)
\r
1163 #define FOC_PRE_K_4K (0x04 << 3)
\r
1165 #define FOC_LIMIT_0 (0x00)
\r
1166 #define FOC_LIMIT_DIV8 (0x01)
\r
1167 #define FOC_LIMIT_DIV4 (0x02)
\r
1168 #define FOC_LIMIT_DIV2 (0x03)
\r
1171 // 0xDF16: BSCFG - Bit Synchronization Configuration
\r
1172 #define BSCFG_BS_PRE_KI 0xC0
\r
1173 #define BSCFG_BS_PRE_KI0 0x40
\r
1174 #define BSCFG_BS_PRE_KI1 0x80
\r
1175 #define BSCFG_BS_PRE_KP 0x30
\r
1176 #define BSCFG_BS_PRE_KP0 0x10
\r
1177 #define BSCFG_BS_PRE_KP1 0x20
\r
1178 #define BSCFG_BS_POST_KI 0x08
\r
1179 #define BSCFG_BS_POST_KP 0x04
\r
1180 #define BSCFG_BS_LIMIT 0x03
\r
1181 #define BSCFG_BS_LIMIT0 0x01
\r
1182 #define BSCFG_BS_LIMIT1 0x02
\r
1184 #define BSCFG_BS_PRE_KI_1K (0x00 << 6)
\r
1185 #define BSCFG_BS_PRE_KI_2K (0x01 << 6)
\r
1186 #define BSCFG_BS_PRE_KI_3K (0x02 << 6)
\r
1187 #define BSCFG_BS_PRE_KI_4K (0x03 << 6)
\r
1189 #define BSCFG_BS_PRE_KP_1K (0x00 << 4)
\r
1190 #define BSCFG_BS_PRE_KP_2K (0x01 << 4)
\r
1191 #define BSCFG_BS_PRE_KP_3K (0x02 << 4)
\r
1192 #define BSCFG_BS_PRE_KP_4K (0x03 << 4)
\r
1194 #define BSCFG_BS_LIMIT_0 (0x00)
\r
1195 #define BSCFG_BS_LIMIT_3 (0x01)
\r
1196 #define BSCFG_BS_LIMIT_6 (0x02)
\r
1197 #define BSCFG_BS_LIMIT_12 (0x03)
\r
1200 // 0xDF17: AGCCTRL2 - AGC Control
\r
1201 #define AGCCTRL2_MAX_DVGA_GAIN 0xC0
\r
1202 #define AGCCTRL2_MAX_LNA_GAIN 0x38
\r
1203 #define AGCCTRL2_MAGN_TARGET 0x07
\r
1206 // 0xDF18: AGCCTRL1 - AGC Control
\r
1207 #define AGCCTRL1_AGC_LNA_PRIORITY 0x40
\r
1208 #define AGCCTRL1_CARRIER_SENSE_REL_THR 0x30
\r
1209 #define AGCCTRL1_CARRIER_SENSE_ABS_THR 0x0F
\r
1212 // 0xDF19: AGCCTRL0 - AGC Control
\r
1213 #define AGCCTRL0_HYST_LEVEL 0xC0
\r
1214 #define AGCCTRL0_WAIT_TIME 0x30
\r
1215 #define AGCCTRL0_AGC_FREEZE 0x0C
\r
1216 #define AGCCTRL0_FILTER_LENGTH 0x03
\r
1219 // 0xDF1A: FREND1 - Front End RX Configuration
\r
1220 #define FREND1_LNA_CURRENT 0xC0
\r
1221 #define FREND1_LNA2MIX_CURRENT 0x30
\r
1222 #define FREND1_LODIV_BUF_CURRENT_RX 0x0C
\r
1223 #define FREND1_MIX_CURRENT 0x03
\r
1226 // 0xDF1B: FREND0 - Front End TX Configuration
\r
1227 #define FREND0_LODIV_BUF_CURRENT_TX 0x30
\r
1230 // 0xDF1C: FSCAL3 - Frequency Synthesizer Calibration
\r
1231 #define FSCAL3_FSCAL3 0xC0
\r
1232 #define FSCAL3_CHP_CURR_CAL_EN 0x30
\r
1235 // 0xDF1D: FSCAL2 - Frequency Synthesizer Calibration
\r
1236 #define FSCAL2_VCO_CORE_H_EN 0x20
\r
1237 #define FSCAL2_FSCAL2 0x1F
\r
1240 // 0xDF1E: FSCAL1 - Frequency Synthesizer Calibration
\r
1242 // 0xDF1F: FSCAL0 - Frequency Synthesizer Calibration
\r
1244 // 0xDF25: TEST0 - Various Test Settings
\r
1247 // RFST (0xE1) - RF Strobe Commands
\r
1248 #define RFST_SFSTXON 0x00
\r
1249 #define RFST_SCAL 0x01
\r
1250 #define RFST_SRX 0x02
\r
1251 #define RFST_STX 0x03
\r
1252 #define RFST_SIDLE 0x04
\r
1253 #define RFST_SNOP 0x05
\r
1255 // 0xDF3B: MARCSTATE - Main Radio Control State Machine State
\r
1256 #define MARCSTATE_MARC_STATE 0x1F
\r
1258 #define MARC_STATE_SLEEP 0x00
\r
1259 #define MARC_STATE_IDLE 0x01
\r
1260 #define MARC_STATE_VCOON_MC 0x03
\r
1261 #define MARC_STATE_REGON_MC 0x04
\r
1262 #define MARC_STATE_MANCAL 0x05
\r
1263 #define MARC_STATE_VCOON 0x06
\r
1264 #define MARC_STATE_REGON 0x07
\r
1265 #define MARC_STATE_STARTCAL 0x08
\r
1266 #define MARC_STATE_BWBOOST 0x09
\r
1267 #define MARC_STATE_FS_LOCK 0x0A
\r
1268 #define MARC_STATE_IFADCON 0x0B
\r
1269 #define MARC_STATE_ENDCAL 0x0C
\r
1270 #define MARC_STATE_RX 0x0D
\r
1271 #define MARC_STATE_RX_END 0x0E
\r
1272 #define MARC_STATE_RX_RST 0x0F
\r
1273 #define MARC_STATE_TXRX_SWITCH 0x10
\r
1274 #define MARC_STATE_RX_OVERFLOW 0x11
\r
1275 #define MARC_STATE_FSTXON 0x12
\r
1276 #define MARC_STATE_TX 0x13
\r
1277 #define MARC_STATE_TX_END 0x14
\r
1278 #define MARC_STATE_RXTX_SWITCH 0x15
\r
1279 #define MARC_STATE_TX_UNDERFLOW 0x16
\r
1283 /***********************************************************************/
\r
projects / goodfet / blob