projects
/
goodfet
/ blobdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
|
commitdiff
|
tree
raw
|
inline
| side by side
Bit of rearranging of Chipcon support.
[goodfet]
/
firmware
/
apps
/
glitch
/
glitch.c
diff --git
a/firmware/apps/glitch/glitch.c
b/firmware/apps/glitch/glitch.c
index
56de8c3
..
f337e42
100644
(file)
--- a/
firmware/apps/glitch/glitch.c
+++ b/
firmware/apps/glitch/glitch.c
@@
-27,11
+27,13
@@
void glitchprime(){
void glitchsetup(){
#ifdef DAC12IR
//Set GSEL high to disable glitching.
void glitchsetup(){
#ifdef DAC12IR
//Set GSEL high to disable glitching.
-
- P5DIR|=0x80;
- P6DIR|=BIT6+BIT5;
- P5OUT|=0x80;
+ //Normal voltage, use resistors instead of output.
+ P5DIR=0x80; //ONLY glitch pin is output.
+ P5OUT|=0x80; //It MUST begin high.
+ P5REN|=0xFF; //Resistors pull high and low weakly.
+
+ P6DIR|=BIT6+BIT5;
P6OUT|=BIT6+BIT5;
WDTCTL = WDTPW + WDTHOLD; // Stop WDT
P6OUT|=BIT6+BIT5;
WDTCTL = WDTPW + WDTHOLD; // Stop WDT
@@
-44,8
+46,7
@@
void glitchsetup(){
}
// Timer A0 interrupt service routine
}
// Timer A0 interrupt service routine
-interrupt(TIMERA0_VECTOR) Timer_A (void)
-{
+interrupt(TIMERA0_VECTOR) Timer_A (void){
P5OUT&=~BIT7;//Glitch
//P5DIR=BIT7; //All else high impedance.
P5OUT|=BIT7;//Normal
P5OUT&=~BIT7;//Glitch
//P5DIR=BIT7; //All else high impedance.
P5OUT|=BIT7;//Normal
@@
-70,6
+71,12
@@
void glitchvoltages(u16 gnd, u16 vcc){
//debughex(gnd);
//debughex(vcc);
//debughex(gnd);
//debughex(vcc);
+ /** N.B., because this is confusing as hell. As per Page 86 of
+ SLAS541F, P6SEL is not what controls the use of the DAC0/DAC1
+ functions on P6.6 and P6.5. Instead, CAPD or DAC12AMP>0 sets
+ the state.
+ */
+
#ifdef DAC12IR
ADC12CTL0 = REF2_5V + REFON; // Internal 2.5V ref on
// Delay here for reference to settle.
#ifdef DAC12IR
ADC12CTL0 = REF2_5V + REFON; // Internal 2.5V ref on
// Delay here for reference to settle.