void ccsetup(){
P5OUT|=MOSI+SCK+RST;
P5DIR|=MOSI+SCK+RST;
- //P5DIR&=~MISO; //MOSI is MISO
-
//P5REN=0xFF;
-
}
//! Initialize the debugger
void ccdebuginit(){
+ //Port output BUT NOT DIRECTION is set at start.
+ P5OUT|=MOSI+SCK+RST;
+
delay(30); //So the beginning is ready for glitching.
//Two positive debug clock pulses while !RST is low.
P5OUT&=~SCK;
P5OUT&=~RST;
- /*
- //pulse twice, old code.
- CCDELAY(CCSPEED);
- P5OUT|=SCK; //up
- CCDELAY(CCSPEED);
- P5OUT&=~SCK; //down
- CCDELAY(CCSPEED);
-
- P5OUT|=SCK; //up
- CCDELAY(CCSPEED);
- P5OUT&=~SCK; //down
- CCDELAY(CCSPEED);
- */
-
- P5OUT^=SCK;
- P5OUT^=SCK;
- P5OUT^=SCK;
+ //Two rising edges.
+ P5OUT^=SCK; //up
+ P5OUT^=SCK; //down
+ P5OUT^=SCK; //up
P5OUT^=SCK; //Unnecessary.
if(cmddata[0]&0x4)
ccread(1);
txdata(app,verb,1);
-
break;
case WRITE: //Write a command with no reply.
cccmd(len);
txdata(app,verb,0);
break;
case START://enter debugger
- ccsetup();
+ //ccsetup(); //interferes with glitching
ccdebuginit();
txdata(app,verb,0);
break;
void glitchsetup(){
#ifdef DAC12IR
//Set GSEL high to disable glitching.
-
- P5DIR|=0x80;
- P6DIR|=BIT6+BIT5;
- P5OUT|=0x80;
+ //Normal voltage, use resistors instead of output.
+ P5DIR=0x80; //ONLY glitch pin is output.
+ P5OUT|=0x80; //It MUST begin high.
+ P5REN|=0xFF; //Resistors pull high and low weakly.
+
+ P6DIR|=BIT6+BIT5;
P6OUT|=BIT6+BIT5;
WDTCTL = WDTPW + WDTHOLD; // Stop WDT
}
// Timer A0 interrupt service routine
-interrupt(TIMERA0_VECTOR) Timer_A (void)
-{
+interrupt(TIMERA0_VECTOR) Timer_A (void){
P5OUT&=~BIT7;//Glitch
//P5DIR=BIT7; //All else high impedance.
P5OUT|=BIT7;//Normal
//debughex(gnd);
//debughex(vcc);
+ /** N.B., because this is confusing as hell. As per Page 86 of
+ SLAS541F, P6SEL is not what controls the use of the DAC0/DAC1
+ functions on P6.6 and P6.5. Instead, CAPD or DAC12AMP>0 sets
+ the state.
+ */
+
#ifdef DAC12IR
ADC12CTL0 = REF2_5V + REFON; // Internal 2.5V ref on
// Delay here for reference to settle.