1 /* Generic Philips CL RC632 Routines
3 * (C) 2005-2006 Harald Welte <laforge@gnumonks.org>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2
10 * as published by the Free Software Foundation
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
27 #include <sys/types.h>
29 #include <librfid/rfid.h>
30 #include <librfid/rfid_asic.h>
31 #include <librfid/rfid_asic_rc632.h>
32 #include <librfid/rfid_reader_cm5121.h>
33 #include <librfid/rfid_layer2_iso14443a.h>
34 #include <librfid/rfid_protocol_mifare_classic.h>
36 #include "rfid_iso14443_common.h"
43 #define RC632_TMO_AUTH1 140
45 #define ENTER() DEBUGP("entering\n")
46 const struct rfid_asic rc632;
48 /* Register and FIFO Access functions */
50 rc632_reg_write(struct rfid_asic_handle *handle,
54 return handle->rath->rat->priv.rc632.fn.reg_write(handle->rath, reg, val);
58 rc632_reg_read(struct rfid_asic_handle *handle,
62 return handle->rath->rat->priv.rc632.fn.reg_read(handle->rath, reg, val);
66 rc632_fifo_write(struct rfid_asic_handle *handle,
71 return handle->rath->rat->priv.rc632.fn.fifo_write(handle->rath,
76 rc632_fifo_read(struct rfid_asic_handle *handle,
80 return handle->rath->rat->priv.rc632.fn.fifo_read(handle->rath, len, buf);
85 rc632_set_bits(struct rfid_asic_handle *handle,
92 ret = rc632_reg_read(handle, reg, &tmp);
96 /* if bits are already set, no need to set them again */
97 if ((tmp & val) == val)
100 return rc632_reg_write(handle, reg, (tmp|val)&0xff);
103 rc632_set_bit_mask(struct rfid_asic_handle *handle,
104 u_int8_t reg, u_int8_t mask, u_int8_t val)
109 ret = rc632_reg_read(handle, reg, &tmp);
113 /* if bits are already like we want them, abort */
114 if ((tmp & mask) == val)
117 return rc632_reg_write(handle, reg, (tmp & ~mask)|(val & mask));
121 rc632_clear_bits(struct rfid_asic_handle *handle,
128 ret = rc632_reg_read(handle, reg, &tmp);
130 DEBUGP("error during reg_read(%p, %d):%d\n",
134 /* if bits are already cleared, no need to clear them again */
135 if ((tmp & val) == 0)
138 return rc632_reg_write(handle, reg, (tmp & ~val)&0xff);
142 rc632_turn_on_rf(struct rfid_asic_handle *handle)
145 return rc632_set_bits(handle, RC632_REG_TX_CONTROL, 0x03);
149 rc632_turn_off_rf(struct rfid_asic_handle *handle)
152 return rc632_clear_bits(handle, RC632_REG_TX_CONTROL, 0x03);
156 rc632_power_up(struct rfid_asic_handle *handle)
159 return rc632_clear_bits(handle, RC632_REG_CONTROL,
160 RC632_CONTROL_POWERDOWN);
164 rc632_power_down(struct rfid_asic_handle *handle)
166 return rc632_set_bits(handle, RC632_REG_CONTROL,
167 RC632_CONTROL_POWERDOWN);
170 /* calculate best 8bit prescaler and divisor for given usec timeout */
171 static int best_prescaler(u_int64_t timeout, u_int8_t *prescaler,
174 u_int8_t best_prescaler, best_divisor, i;
175 int64_t smallest_diff;
177 smallest_diff = LLONG_MAX;
180 for (i = 0; i < 21; i++) {
181 u_int64_t clk, tmp_div, res;
183 clk = 13560000 / (1 << i);
184 tmp_div = (clk * timeout) / 1000000;
187 if ((tmp_div > 0xff) || (tmp_div > clk))
190 res = 1000000 / (clk / tmp_div);
191 diff = res - timeout;
196 if (diff < smallest_diff) {
198 best_divisor = tmp_div;
199 smallest_diff = diff;
203 *prescaler = best_prescaler;
204 *divisor = best_divisor;
206 DEBUGP("timeout %u usec, prescaler = %u, divisor = %u\n",
207 timeout, best_prescaler, best_divisor);
213 rc632_timer_set(struct rfid_asic_handle *handle,
217 u_int8_t prescaler, divisor;
219 ret = best_prescaler(timeout, &prescaler, &divisor);
221 ret = rc632_reg_write(handle, RC632_REG_TIMER_CLOCK,
226 ret = rc632_reg_write(handle, RC632_REG_TIMER_CONTROL,
227 RC632_TMR_START_TX_END|RC632_TMR_STOP_RX_BEGIN);
229 /* clear timer irq bit */
230 ret = rc632_set_bits(handle, RC632_REG_INTERRUPT_RQ, RC632_IRQ_TIMER);
232 ret |= rc632_reg_write(handle, RC632_REG_TIMER_RELOAD, divisor);
237 /* Wait until RC632 is idle or TIMER IRQ has happened */
238 static int rc632_wait_idle_timer(struct rfid_asic_handle *handle)
244 rc632_reg_read(handle, RC632_REG_PRIMARY_STATUS, &irq);
245 rc632_reg_read(handle, RC632_REG_ERROR_FLAG, &irq);
246 ret = rc632_reg_read(handle, RC632_REG_INTERRUPT_RQ, &irq);
250 /* FIXME: currently we're lazy: If we actually received
251 * something even after the timer expired, we accept it */
252 if (irq & RC632_IRQ_TIMER && !(irq & RC632_IRQ_RX)) {
254 rc632_reg_read(handle, RC632_REG_PRIMARY_STATUS, &foo);
256 rc632_reg_read(handle, RC632_REG_ERROR_FLAG, &foo);
261 ret = rc632_reg_read(handle, RC632_REG_COMMAND, &cmd);
268 /* poll every millisecond */
273 /* Stupid RC632 implementations don't evaluate interrupts but poll the
274 * command register for "status idle" */
276 rc632_wait_idle(struct rfid_asic_handle *handle, u_int64_t timeout)
280 #define USLEEP_PER_CYCLE 128
283 ret = rc632_reg_read(handle, RC632_REG_COMMAND, &cmd);
288 /* FIXME: read second time ?? */
294 rc632_reg_read(handle, RC632_REG_PRIMARY_STATUS, &foo);
296 rc632_reg_read(handle, RC632_REG_ERROR_FLAG, &foo);
299 /* Abort after some timeout */
300 if (cycles > timeout*100/USLEEP_PER_CYCLE) {
305 usleep(USLEEP_PER_CYCLE);
312 rc632_transmit(struct rfid_asic_handle *handle,
318 const u_int8_t *cur_buf = buf;
326 ret = rc632_fifo_write(handle, cur_len, cur_buf, 0x03);
330 if (cur_buf == buf) {
331 /* only start transmit first time */
332 ret = rc632_reg_write(handle, RC632_REG_COMMAND,
339 if (cur_buf < buf + len) {
340 cur_len = buf - cur_buf;
348 return rc632_wait_idle(handle, timeout);
352 tcl_toggle_pcb(struct rfid_asic_handle *handle)
354 // FIXME: toggle something between 0x0a and 0x0b
359 rc632_transceive(struct rfid_asic_handle *handle,
360 const u_int8_t *tx_buf,
369 const u_int8_t *cur_tx_buf = tx_buf;
371 DEBUGP("timer = %u\n", timer);
378 ret = rc632_timer_set(handle, timer*10);
382 ret = rc632_reg_write(handle, RC632_REG_COMMAND, 0x00);
383 /* clear all interrupts */
384 ret = rc632_reg_write(handle, RC632_REG_INTERRUPT_RQ, 0x7f);
387 ret = rc632_fifo_write(handle, cur_tx_len, cur_tx_buf, 0x03);
391 if (cur_tx_buf == tx_buf) {
392 ret = rc632_reg_write(handle, RC632_REG_COMMAND,
393 RC632_CMD_TRANSCEIVE);
398 cur_tx_buf += cur_tx_len;
399 if (cur_tx_buf < tx_buf + tx_len) {
401 ret = rc632_reg_read(handle, RC632_REG_FIFO_LENGTH,
406 cur_tx_len = 64 - fifo_fill;
407 //printf("refilling tx fifo with %u bytes\n", cur_tx_len);
411 } while (cur_tx_len);
414 tcl_toggle_pcb(handle);
416 //ret = rc632_wait_idle_timer(handle);
417 ret = rc632_wait_idle(handle, timer);
421 ret = rc632_reg_read(handle, RC632_REG_FIFO_LENGTH, &rx_avail);
425 if (rx_avail > *rx_len) {
426 //printf("rx_avail(%d) > rx_len(%d), JFYI\n", rx_avail, *rx_len);
427 } else if (*rx_len > rx_avail)
433 DEBUGP("rx_len == 0\n");
435 rc632_reg_read(handle, RC632_REG_ERROR_FLAG, &tmp);
436 rc632_reg_read(handle, RC632_REG_CHANNEL_REDUNDANCY, &tmp);
441 return rc632_fifo_read(handle, *rx_len, rx_buf);
442 /* FIXME: discard addidional bytes in FIFO */
446 rc632_read_eeprom(struct rfid_asic_handle *handle)
448 u_int8_t recvbuf[60];
456 ret = rc632_fifo_write(handle, 3, sndbuf, 0x03);
460 ret = rc632_reg_write(handle, RC632_REG_COMMAND, RC632_CMD_READ_E2);
466 ret = rc632_fifo_read(handle, sizeof(recvbuf), recvbuf);
470 // FIXME: do something with eeprom contents
475 rc632_calc_crc16_from(struct rfid_asic_handle *handle)
477 u_int8_t sndbuf[2] = { 0x01, 0x02 };
478 u_int8_t crc_lsb = 0x00 , crc_msb = 0x00;
481 ret = rc632_reg_write(handle, RC632_REG_CRC_PRESET_LSB, 0x12);
485 ret = rc632_reg_write(handle, RC632_REG_CRC_PRESET_MSB, 0xe0);
489 ret = rc632_fifo_write(handle, sizeof(sndbuf), sndbuf, 3);
493 ret = rc632_reg_write(handle, RC632_REG_COMMAND, RC632_CMD_CALC_CRC);
497 usleep(10000); // FIXME: no checking for cmd completion?
499 ret = rc632_reg_read(handle, RC632_REG_CRC_RESULT_LSB, &crc_lsb);
503 ret = rc632_reg_read(handle, RC632_REG_CRC_RESULT_MSB, &crc_msb);
507 // FIXME: what to do with crc result?
513 rc632_register_dump(struct rfid_asic_handle *handle, u_int8_t *buf)
518 for (i = 0; i <= 0x3f; i++) {
519 ret = rc632_reg_read(handle, i, &buf[i]);
520 // do we want error checks?
527 /* generic FIFO access functions (if no more efficient ones provided by
528 * transport driver) */
533 // FIXME: implementation (not needed for CM 5121)
540 // FIXME: implementation (not neded for CM 5121)
545 rc632_init(struct rfid_asic_handle *ah)
549 /* switch off rf (make sure PICCs are reset at init time) */
550 ret = rc632_power_down(ah);
557 ret = rc632_power_up(ah);
561 /* disable register paging */
562 ret = rc632_reg_write(ah, 0x00, 0x00);
566 /* set some sane default values */
567 ret = rc632_reg_write(ah, 0x11, 0x5b);
572 ret = rc632_turn_off_rf(ah);
579 ret = rc632_turn_on_rf(ah);
587 rc632_fini(struct rfid_asic_handle *ah)
592 ret = rc632_turn_off_rf(ah);
596 ret = rc632_power_down(ah);
603 struct rfid_asic_handle *
604 rc632_open(struct rfid_asic_transport_handle *th)
606 struct rfid_asic_handle *h;
608 h = malloc_asic_handle(sizeof(*h));
611 memset(h, 0, sizeof(*h));
613 h->asic = (void*)&rc632;
616 /* FIXME: this is only cm5121 specific, since the latency
617 * down to the RC632 FIFO is too long to refill during TX/RX */
618 h->mtu = h->mru = 64;
620 if (rc632_init(h) < 0) {
629 rc632_close(struct rfid_asic_handle *h)
637 * Philips CL RC632 primitives for ISO 14443-A compliant PICC's
639 * (C) 2005-2006 by Harald Welte <laforge@gnumonks.org>
644 rc632_iso14443a_init(struct rfid_asic_handle *handle)
648 // FIXME: some fifo work (drain fifo?)
650 /* flush fifo (our way) */
651 ret = rc632_reg_write(handle, RC632_REG_CONTROL,
652 RC632_CONTROL_FIFO_FLUSH);
654 ret = rc632_reg_write(handle, RC632_REG_TX_CONTROL,
655 (RC632_TXCTRL_TX1_RF_EN |
656 RC632_TXCTRL_TX2_RF_EN |
657 RC632_TXCTRL_TX2_INV |
658 RC632_TXCTRL_FORCE_100_ASK |
659 RC632_TXCTRL_MOD_SRC_INT));
663 ret = rc632_reg_write(handle, RC632_REG_CW_CONDUCTANCE,
664 CM5121_CW_CONDUCTANCE);
668 /* Since FORCE_100_ASK is set (cf mc073930.pdf), this line may be left out? */
669 ret = rc632_reg_write(handle, RC632_REG_MOD_CONDUCTANCE,
670 CM5121_MOD_CONDUCTANCE);
674 ret = rc632_reg_write(handle, RC632_REG_CODER_CONTROL,
675 (RC632_CDRCTRL_TXCD_14443A |
676 RC632_CDRCTRL_RATE_106K));
680 ret = rc632_reg_write(handle, RC632_REG_MOD_WIDTH, 0x13);
684 ret = rc632_reg_write(handle, RC632_REG_MOD_WIDTH_SOF, 0x3f);
688 ret = rc632_reg_write(handle, RC632_REG_TYPE_B_FRAMING, 0x00);
692 ret = rc632_reg_write(handle, RC632_REG_RX_CONTROL1,
693 (RC632_RXCTRL1_GAIN_35DB |
694 RC632_RXCTRL1_ISO14443 |
695 RC632_RXCTRL1_SUBCP_8));
699 ret = rc632_reg_write(handle, RC632_REG_DECODER_CONTROL,
700 (RC632_DECCTRL_MANCHESTER |
701 RC632_DECCTRL_RXFR_14443A));
705 ret = rc632_reg_write(handle, RC632_REG_BIT_PHASE,
706 CM5121_14443A_BITPHASE);
710 ret = rc632_reg_write(handle, RC632_REG_RX_THRESHOLD,
711 CM5121_14443A_THRESHOLD);
715 ret = rc632_reg_write(handle, RC632_REG_BPSK_DEM_CONTROL, 0x00);
719 ret = rc632_reg_write(handle, RC632_REG_RX_CONTROL2,
720 (RC632_RXCTRL2_DECSRC_INT |
721 RC632_RXCTRL2_CLK_Q));
725 /* Omnikey proprietary driver has 0x03, but 0x06 is the default reset value ?!? */
726 ret = rc632_reg_write(handle, RC632_REG_RX_WAIT, 0x06);
730 ret = rc632_reg_write(handle, RC632_REG_CHANNEL_REDUNDANCY,
731 (RC632_CR_PARITY_ENABLE |
732 RC632_CR_PARITY_ODD));
736 ret = rc632_reg_write(handle, RC632_REG_CRC_PRESET_LSB, 0x63);
740 ret = rc632_reg_write(handle, RC632_REG_CRC_PRESET_MSB, 0x63);
748 rc632_iso14443a_fini(struct iso14443a_handle *handle_14443)
752 ret = rc632_turn_off_rf(handle);
762 /* issue a 14443-3 A PCD -> PICC command in a short frame, such as REQA, WUPA */
764 rc632_iso14443a_transceive_sf(struct rfid_asic_handle *handle,
766 struct iso14443a_atqa *atqa)
772 memset(atqa, 0, sizeof(*atqa));
776 /* transfer only 7 bits of last byte in frame */
777 ret = rc632_reg_write(handle, RC632_REG_BIT_FRAMING, 0x07);
781 ret = rc632_clear_bits(handle, RC632_REG_CONTROL,
782 RC632_CONTROL_CRYPTO1_ON);
787 ret = rc632_reg_write(handle, RC632_REG_CHANNEL_REDUNDANCY,
788 (RC632_CR_PARITY_ENABLE |
789 RC632_CR_PARITY_ODD));
791 ret = rc632_clear_bits(handle, RC632_REG_CHANNEL_REDUNDANCY,
792 RC632_CR_RX_CRC_ENABLE|RC632_CR_TX_CRC_ENABLE);
798 ret = rc632_transceive(handle, tx_buf, sizeof(tx_buf),
799 (u_int8_t *)atqa, &rx_len,
800 ISO14443A_FDT_ANTICOL_LAST1, 0);
802 DEBUGP("error during rc632_transceive()\n");
806 /* switch back to normal 8bit last byte */
807 ret = rc632_reg_write(handle, RC632_REG_BIT_FRAMING, 0x00);
812 DEBUGP("rx_len(%d) != 2\n", rx_len);
819 /* transceive regular frame */
821 rc632_iso14443ab_transceive(struct rfid_asic_handle *handle,
822 unsigned int frametype,
823 const u_int8_t *tx_buf, unsigned int tx_len,
824 u_int8_t *rx_buf, unsigned int *rx_len,
825 u_int64_t timeout, unsigned int flags)
829 u_int8_t channel_red;
836 memset(rx_buf, 0, *rx_len);
839 case RFID_14443A_FRAME_REGULAR:
840 case RFID_MIFARE_FRAME:
841 channel_red = RC632_CR_RX_CRC_ENABLE|RC632_CR_TX_CRC_ENABLE
842 |RC632_CR_PARITY_ENABLE|RC632_CR_PARITY_ODD;
844 case RFID_14443B_FRAME_REGULAR:
845 channel_red = RC632_CR_RX_CRC_ENABLE|RC632_CR_TX_CRC_ENABLE
849 case RFID_MIFARE_FRAME:
850 channel_red = RC632_CR_PARITY_ENABLE|RC632_CR_PARITY_ODD;
857 ret = rc632_reg_write(handle, RC632_REG_CHANNEL_REDUNDANCY,
862 ret = rc632_transceive(handle, tx_buf, tx_len, rx_buf, &rxl, timeout, 0);
871 /* transceive anti collission bitframe */
873 rc632_iso14443a_transceive_acf(struct rfid_asic_handle *handle,
874 struct iso14443a_anticol_cmd *acf,
875 unsigned int *bit_of_col)
879 u_int8_t rx_len = sizeof(rx_buf);
880 u_int8_t rx_align = 0, tx_last_bits, tx_bytes, tx_bytes_total;
883 *bit_of_col = ISO14443A_BITOFCOL_NONE;
884 memset(rx_buf, 0, sizeof(rx_buf));
886 /* disable mifare cryto */
887 ret = rc632_clear_bits(handle, RC632_REG_CONTROL,
888 RC632_CONTROL_CRYPTO1_ON);
892 /* disable CRC summing */
894 ret = rc632_reg_write(handle, RC632_REG_CHANNEL_REDUNDANCY,
895 (RC632_CR_PARITY_ENABLE |
896 RC632_CR_PARITY_ODD));
898 ret = rc632_clear_bits(handle, RC632_REG_CHANNEL_REDUNDANCY,
899 RC632_CR_TX_CRC_ENABLE|RC632_CR_TX_CRC_ENABLE);
904 tx_last_bits = acf->nvb & 0x07; /* lower nibble indicates bits */
905 tx_bytes = ( acf->nvb >> 4 ) & 0x07;
907 tx_bytes_total = tx_bytes+1;
908 rx_align = tx_last_bits & 0x07; /* rx frame complements tx */
911 tx_bytes_total = tx_bytes;
913 /* set RxAlign and TxLastBits*/
914 ret = rc632_reg_write(handle, RC632_REG_BIT_FRAMING,
915 (rx_align << 4) | (tx_last_bits));
919 ret = rc632_transceive(handle, (u_int8_t *)acf, tx_bytes_total,
920 rx_buf, &rx_len, 0x32, 0);
924 /* bitwise-OR the two halves of the split byte */
925 acf->uid_bits[tx_bytes-2] = (
926 (acf->uid_bits[tx_bytes-2] & (0xff >> (8-tx_last_bits)))
931 memcpy(&acf->uid_bits[tx_bytes-1], &rx_buf[1], rx_len-1);
933 /* determine whether there was a collission */
934 ret = rc632_reg_read(handle, RC632_REG_ERROR_FLAG, &error_flag);
938 if (error_flag & RC632_ERR_FLAG_COL_ERR) {
939 /* retrieve bit of collission */
940 ret = rc632_reg_read(handle, RC632_REG_COLL_POS, &boc);
944 /* bit of collission relative to start of part 1 of
945 * anticollision frame (!) */
946 *bit_of_col = 2*8 + boc;
953 RC632_RATE_106 = 0x00,
954 RC632_RATE_212 = 0x01,
955 RC632_RATE_424 = 0x02,
956 RC632_RATE_848 = 0x03,
960 u_int8_t subc_pulses;
962 u_int8_t rx_threshold;
963 u_int8_t bpsk_dem_ctrl;
971 static struct rx_config rx_configs[] = {
973 .subc_pulses = RC632_RXCTRL1_SUBCP_8,
974 .rx_coding = RC632_DECCTRL_MANCHESTER,
975 .rx_threshold = 0x88,
976 .bpsk_dem_ctrl = 0x00,
979 .subc_pulses = RC632_RXCTRL1_SUBCP_4,
980 .rx_coding = RC632_DECCTRL_BPSK,
981 .rx_threshold = 0x50,
982 .bpsk_dem_ctrl = 0x0c,
985 .subc_pulses = RC632_RXCTRL1_SUBCP_2,
986 .rx_coding = RC632_DECCTRL_BPSK,
987 .rx_threshold = 0x50,
988 .bpsk_dem_ctrl = 0x0c,
991 .subc_pulses = RC632_RXCTRL1_SUBCP_1,
992 .rx_coding = RC632_DECCTRL_BPSK,
993 .rx_threshold = 0x50,
994 .bpsk_dem_ctrl = 0x0c,
998 static struct tx_config tx_configs[] = {
1000 .rate = RC632_CDRCTRL_RATE_106K,
1004 .rate = RC632_CDRCTRL_RATE_212K,
1008 .rate = RC632_CDRCTRL_RATE_424K,
1012 .rate = RC632_CDRCTRL_RATE_848K,
1017 static int rc632_iso14443a_set_speed(struct rfid_asic_handle *handle,
1018 unsigned int tx, unsigned int rate)
1026 if (rate > ARRAY_SIZE(rx_configs))
1029 rc = rc632_set_bit_mask(handle, RC632_REG_RX_CONTROL1,
1030 RC632_RXCTRL1_SUBCP_MASK,
1031 rx_configs[rate].subc_pulses);
1035 rc = rc632_set_bit_mask(handle, RC632_REG_DECODER_CONTROL,
1037 rx_configs[rate].rx_coding);
1041 rc = rc632_reg_write(handle, RC632_REG_RX_THRESHOLD,
1042 rx_configs[rate].rx_threshold);
1046 if (rx_configs[rate].rx_coding == RC632_DECCTRL_BPSK) {
1047 rc = rc632_reg_write(handle,
1048 RC632_REG_BPSK_DEM_CONTROL,
1049 rx_configs[rate].bpsk_dem_ctrl);
1055 if (rate > ARRAY_SIZE(tx_configs))
1058 rc = rc632_set_bit_mask(handle, RC632_REG_CODER_CONTROL,
1059 RC632_CDRCTRL_RATE_MASK,
1060 tx_configs[rate].rate);
1064 rc = rc632_reg_write(handle, RC632_REG_MOD_WIDTH,
1065 tx_configs[rate].mod_width);
1073 static int rc632_iso14443b_init(struct rfid_asic_handle *handle)
1077 // FIXME: some FIFO work
1079 /* flush fifo (our way) */
1080 ret = rc632_reg_write(handle, RC632_REG_CONTROL,
1081 RC632_CONTROL_FIFO_FLUSH);
1085 ret = rc632_reg_write(handle, RC632_REG_TX_CONTROL,
1086 (RC632_TXCTRL_TX1_RF_EN |
1087 RC632_TXCTRL_TX2_RF_EN |
1088 RC632_TXCTRL_TX2_INV |
1089 RC632_TXCTRL_MOD_SRC_INT));
1093 ret = rc632_reg_write(handle, RC632_REG_CW_CONDUCTANCE, 0x3f);
1097 ret = rc632_reg_write(handle, RC632_REG_MOD_CONDUCTANCE, 0x04);
1101 ret = rc632_reg_write(handle, RC632_REG_CODER_CONTROL,
1102 (RC632_CDRCTRL_TXCD_NRZ |
1103 RC632_CDRCTRL_RATE_14443B));
1107 ret = rc632_reg_write(handle, RC632_REG_MOD_WIDTH, 0x13);
1111 ret = rc632_reg_write(handle, RC632_REG_MOD_WIDTH_SOF, 0x3f);
1115 ret = rc632_reg_write(handle, RC632_REG_TYPE_B_FRAMING,
1116 (RC632_TBFRAMING_SOF_11L_3H |
1117 (6 << RC632_TBFRAMING_SPACE_SHIFT) |
1118 RC632_TBFRAMING_EOF_11));
1122 ret = rc632_reg_write(handle, RC632_REG_RX_CONTROL1,
1123 (RC632_RXCTRL1_GAIN_35DB |
1124 RC632_RXCTRL1_ISO14443 |
1125 RC632_RXCTRL1_SUBCP_8));
1129 ret = rc632_reg_write(handle, RC632_REG_DECODER_CONTROL,
1130 (RC632_DECCTRL_BPSK |
1131 RC632_DECCTRL_RXFR_14443B));
1135 ret = rc632_reg_write(handle, RC632_REG_BIT_PHASE,
1136 CM5121_14443B_BITPHASE);
1140 ret = rc632_reg_write(handle, RC632_REG_RX_THRESHOLD,
1141 CM5121_14443B_THRESHOLD);
1145 ret = rc632_reg_write(handle, RC632_REG_BPSK_DEM_CONTROL,
1146 ((0x2 & RC632_BPSKD_TAUB_MASK)<<RC632_BPSKD_TAUB_SHIFT |
1147 (0x3 & RC632_BPSKD_TAUD_MASK)<<RC632_BPSKD_TAUD_SHIFT |
1148 RC632_BPSKD_FILTER_AMP_DETECT |
1149 RC632_BPSKD_NO_RX_EOF |
1150 RC632_BPSKD_NO_RX_EGT));
1154 ret = rc632_reg_write(handle, RC632_REG_RX_CONTROL2,
1155 (RC632_RXCTRL2_AUTO_PD |
1156 RC632_RXCTRL2_DECSRC_INT));
1160 ret = rc632_reg_write(handle, RC632_REG_RX_WAIT, 0x03);
1164 ret = rc632_reg_write(handle, RC632_REG_CHANNEL_REDUNDANCY,
1165 (RC632_CR_TX_CRC_ENABLE |
1166 RC632_CR_RX_CRC_ENABLE |
1171 ret = rc632_reg_write(handle, RC632_REG_CRC_PRESET_LSB, 0xff);
1175 ret = rc632_reg_write(handle, RC632_REG_CRC_PRESET_MSB, 0xff);
1183 rc632_iso15693_init(struct rfid_asic_handle *h)
1187 ret = rc632_reg_write(h, RC632_REG_TX_CONTROL,
1188 (RC632_TXCTRL_MOD_SRC_INT |
1189 RC632_TXCTRL_TX2_INV |
1190 RC632_TXCTRL_TX2_RF_EN |
1191 RC632_TXCTRL_TX1_RF_EN));
1195 ret = rc632_reg_write(h, RC632_REG_CW_CONDUCTANCE, 0x3f);
1199 ret = rc632_reg_write(h, RC632_REG_MOD_CONDUCTANCE, 0x03);
1203 ret = rc632_reg_write(h, RC632_REG_CODER_CONTROL,
1204 (RC632_CDRCTRL_RATE_15693 |
1209 ret = rc632_reg_write(h, RC632_REG_MOD_WIDTH, 0x3f);
1213 ret = rc632_reg_write(h, RC632_REG_MOD_WIDTH_SOF, 0x3f);
1217 ret = rc632_reg_write(h, RC632_REG_TYPE_B_FRAMING, 0x00);
1221 ret = rc632_reg_write(h, RC632_REG_RX_CONTROL1,
1222 (RC632_RXCTRL1_SUBCP_16 |
1223 RC632_RXCTRL1_ISO15693 |
1224 RC632_RXCTRL1_GAIN_35DB));
1228 ret = rc632_reg_write(h, RC632_REG_DECODER_CONTROL,
1229 (RC632_DECCTRL_RXFR_15693 |
1230 RC632_DECCTRL_RX_INVERT));
1234 ret = rc632_reg_write(h, RC632_REG_BIT_PHASE, 0xe0);
1238 ret = rc632_reg_write(h, RC632_REG_RX_THRESHOLD, 0xff);
1242 ret = rc632_reg_write(h, RC632_REG_BPSK_DEM_CONTROL, 0x00);
1246 ret = rc632_reg_write(h, RC632_REG_RX_CONTROL2,
1247 (RC632_RXCTRL2_AUTO_PD |
1248 RC632_RXCTRL2_DECSRC_INT));
1252 ret = rc632_reg_write(h, RC632_REG_CHANNEL_REDUNDANCY,
1254 RC632_CR_RX_CRC_ENABLE |
1255 RC632_CR_TX_CRC_ENABLE));
1259 ret = rc632_reg_write(h, RC632_REG_CRC_PRESET_LSB, 0xff);
1263 ret = rc632_reg_write(h, RC632_REG_CRC_PRESET_MSB, 0xff);
1271 rc632_iso15693_icode_init(struct rfid_asic_handle *h)
1275 ret = rc632_reg_write(h, RC632_REG_TX_CONTROL,
1276 (RC632_TXCTRL_MOD_SRC_INT |
1277 RC632_TXCTRL_TX2_INV |
1278 RC632_TXCTRL_TX2_RF_EN |
1279 RC632_TXCTRL_TX1_RF_EN));
1283 ret = rc632_reg_write(h, RC632_REG_CW_CONDUCTANCE, 0x3f);
1287 ret = rc632_reg_write(h, RC632_REG_MOD_CONDUCTANCE, 0x02);
1291 ret = rc632_reg_write(h, RC632_REG_CODER_CONTROL, 0x2c);
1295 ret = rc632_reg_write(h, RC632_REG_MOD_WIDTH, 0x3f);
1299 ret = rc632_reg_write(h, RC632_REG_MOD_WIDTH_SOF, 0x3f);
1303 ret = rc632_reg_write(h, RC632_REG_MOD_WIDTH_SOF, 0x3f);
1307 ret = rc632_reg_write(h, RC632_REG_TYPE_B_FRAMING, 0x00);
1311 ret = rc632_reg_write(h, RC632_REG_RX_CONTROL1, 0x8b); /* FIXME */
1315 ret = rc632_reg_write(h, RC632_REG_DECODER_CONTROL, 0x00);
1319 ret = rc632_reg_write(h, RC632_REG_BIT_PHASE, 0x52);
1323 ret = rc632_reg_write(h, RC632_REG_RX_THRESHOLD, 0x66);
1327 ret = rc632_reg_write(h, RC632_REG_BPSK_DEM_CONTROL, 0x00);
1331 ret = rc632_reg_write(h, RC632_REG_RX_CONTROL2,
1332 RC632_RXCTRL2_DECSRC_INT);
1336 ret = rc632_reg_write(h, RC632_REG_CHANNEL_REDUNDANCY,
1337 (RC632_CR_RX_CRC_ENABLE |
1338 RC632_CR_TX_CRC_ENABLE));
1339 ret = rc632_reg_write(h, RC632_REG_CRC_PRESET_LSB, 0xfe);
1343 ret = rc632_reg_write(h, RC632_REG_CRC_PRESET_MSB, 0xff);
1351 rc632_iso15693_icl_init(struct rfid_asic_handle *h)
1357 ret = rc632_reg_write(h, RC632_REG_TX_CONTROL,
1358 (RC632_TXCTRL_MOD_SRC_INT |
1359 RC632_TXCTRL_TX2_INV |
1360 RC632_TXCTRL_TX2_RF_EN |
1361 RC632_TXCTRL_TX1_RF_EN));
1365 ret = rc632_reg_write(h, RC632_REG_CW_CONDUCTANCE, 0x3f);
1369 ret = rc632_reg_write(h, RC632_REG_MOD_CONDUCTANCE, 0x11);
1373 ret = rc632_reg_write(h, RC632_REG_CODER_CONTROL,
1374 (RC632_CDRCTRL_RATE_15693 |
1375 RC632_CDRCTRL_TXCD_ICODE_STD |
1380 ret = rc632_reg_write(h, RC632_REG_MOD_WIDTH, 0x3f);
1384 ret = rc632_reg_write(h, RC632_REG_MOD_WIDTH_SOF, 0x3f);
1387 ret = rc632_reg_write(h, RC632_REG_RX_CONTROL1,
1388 (RC632_RXCTRL1_SUBCP_16|
1389 RC632_RXCTRL1_ISO15693|
1390 RC632_RXCTRL1_GAIN_35DB));
1393 ret = rc632_reg_write(h, RC632_REG_DECODER_CONTROL,
1394 (RC632_DECCTRL_RX_INVERT|
1395 RC632_DECCTRL_RXFR_15693));
1399 ret = rc632_reg_write(h, RC632_REG_BIT_PHASE, 0xbd);
1403 ret = rc632_reg_write(h, RC632_REG_RX_THRESHOLD, 0xff);
1407 ret = rc632_reg_write(h, RC632_REG_BPSK_DEM_CONTROL, 0x00);
1411 ret = rc632_reg_write(h, RC632_REG_RX_CONTROL2,
1412 RC632_RXCTRL2_DECSRC_INT);
1416 ret = rc632_reg_write(h, RC632_REG_CHANNEL_REDUNDANCY, 0x00);
1420 ret = rc632_reg_write(h, RC632_REG_CRC_PRESET_LSB, 0x12);
1424 ret = rc632_reg_write(h, RC632_REG_CRC_PRESET_MSB, 0xe0);
1431 struct mifare_authcmd {
1433 u_int8_t block_address;
1434 u_int32_t serno; /* lsb 1 2 msb */
1435 } __attribute__ ((packed));
1438 #define RFID_MIFARE_KEY_LEN 6
1439 #define RFID_MIFARE_KEY_CODED_LEN 12
1441 /* Transform crypto1 key from generic 6byte into rc632 specific 12byte */
1443 rc632_mifare_transform_key(const u_int8_t *key6, u_int8_t *key12)
1449 for (i = 0; i < RFID_MIFARE_KEY_LEN; i++) {
1450 ln = key6[i] & 0x0f;
1452 key12[i * 2 + 1] = (~ln << 4) | ln;
1453 key12[i * 2] = (~hn << 4) | hn;
1459 rc632_mifare_set_key(struct rfid_asic_handle *h, const u_int8_t *key)
1461 u_int8_t coded_key[RFID_MIFARE_KEY_CODED_LEN];
1465 ret = rc632_mifare_transform_key(key, coded_key);
1469 /* Terminate probably running command */
1470 ret = rc632_reg_write(h, RC632_REG_COMMAND, RC632_CMD_IDLE);
1474 ret = rc632_fifo_write(h, RFID_MIFARE_KEY_CODED_LEN, coded_key, 0x03);
1478 ret = rc632_reg_write(h, RC632_REG_COMMAND, RC632_CMD_LOAD_KEY);
1482 ret = rc632_wait_idle(h, RC632_TMO_AUTH1);
1486 ret = rc632_reg_read(h, RC632_REG_ERROR_FLAG, ®);
1490 if (reg & RC632_ERR_FLAG_KEY_ERR)
1497 rc632_mifare_auth(struct rfid_asic_handle *h, u_int8_t cmd, u_int32_t serno,
1501 struct mifare_authcmd acmd;
1504 if (cmd != RFID_CMD_MIFARE_AUTH1A && cmd != RFID_CMD_MIFARE_AUTH1B) {
1505 DEBUGP("invalid auth command\n");
1509 /* Initialize acmd */
1510 acmd.block_address = block & 0xff;
1511 acmd.auth_cmd = cmd;
1512 //acmd.serno = htonl(serno);
1517 ret = rc632_clear_bits(h, RC632_REG_CHANNEL_REDUNDANCY,
1518 RC632_CR_RX_CRC_ENABLE);
1520 /* Clear Rx CRC, Set Tx CRC and Odd Parity */
1521 ret = rc632_reg_write(h, RC632_REG_CHANNEL_REDUNDANCY,
1522 RC632_CR_TX_CRC_ENABLE | RC632_CR_PARITY_ODD |
1523 RC632_CR_PARITY_ENABLE);
1528 /* Send Authent1 Command */
1529 ret = rc632_fifo_write(h, sizeof(acmd), (unsigned char *)&acmd, 0x03);
1533 ret = rc632_reg_write(h, RC632_REG_COMMAND, RC632_CMD_AUTHENT1);
1535 DEBUGP("error during AUTHENT1");
1539 /* Wait until transmitter is idle */
1540 ret = rc632_wait_idle(h, RC632_TMO_AUTH1);
1544 ret = rc632_reg_read(h, RC632_REG_SECONDARY_STATUS, ®);
1548 DEBUGP("bitframe?");
1553 ret = rc632_clear_bits(h, RC632_REG_CHANNEL_REDUNDANCY,
1554 RC632_CR_TX_CRC_ENABLE);
1558 /* Send Authent2 Command */
1559 ret = rc632_reg_write(h, RC632_REG_COMMAND, RC632_CMD_AUTHENT2);
1563 /* Wait until transmitter is idle */
1564 ret = rc632_wait_idle(h, RC632_TMO_AUTH1);
1568 /* Check whether authentication was successful */
1569 ret = rc632_reg_read(h, RC632_REG_CONTROL, ®);
1573 if (!(reg & RC632_CONTROL_CRYPTO1_ON)) {
1574 DEBUGP("authentication not successful");
1581 /* transceive regular frame */
1583 rc632_mifare_transceive(struct rfid_asic_handle *handle,
1584 const u_int8_t *tx_buf, unsigned int tx_len,
1585 u_int8_t *rx_buf, unsigned int *rx_len,
1586 u_int64_t timeout, unsigned int flags)
1589 u_int8_t rxl = *rx_len & 0xff;
1591 DEBUGP("entered\n");
1592 memset(rx_buf, 0, *rx_len);
1595 ret = rc632_reg_write(handle, RC632_REG_CHANNEL_REDUNDANCY,
1596 (RC632_CR_PARITY_ENABLE |
1597 RC632_CR_PARITY_ODD |
1598 RC632_CR_TX_CRC_ENABLE |
1599 RC632_CR_RX_CRC_ENABLE));
1601 ret = rc632_clear_bits(handle, RC632_REG_CHANNEL_REDUNDANCY,
1602 RC632_CR_RX_CRC_ENABLE|RC632_CR_TX_CRC_ENABLE);
1607 ret = rc632_transceive(handle, tx_buf, tx_len, rx_buf, &rxl, 0x32, 0);
1616 const struct rfid_asic rc632 = {
1617 .name = "Philips CL RC632",
1618 .fc = ISO14443_FREQ_CARRIER,
1621 .power_up = &rc632_power_up,
1622 .power_down = &rc632_power_down,
1623 .turn_on_rf = &rc632_turn_on_rf,
1624 .turn_off_rf = &rc632_turn_off_rf,
1625 .transceive = &rc632_iso14443ab_transceive,
1627 .init = &rc632_iso14443a_init,
1628 .transceive_sf = &rc632_iso14443a_transceive_sf,
1629 .transceive_acf = &rc632_iso14443a_transceive_acf,
1630 .set_speed = &rc632_iso14443a_set_speed,
1633 .init = &rc632_iso14443b_init,
1636 .init = &rc632_iso15693_init,
1639 .setkey = &rc632_mifare_set_key,
1640 .auth = &rc632_mifare_auth,