1 /* Generic Philips CL RC632 Routines
3 * (C) 2005-2008 Harald Welte <laforge@gnumonks.org>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2
10 * as published by the Free Software Foundation
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
27 #include <sys/types.h>
29 #include <librfid/rfid.h>
30 #include <librfid/rfid_asic.h>
31 #include <librfid/rfid_asic_rc632.h>
32 #include <librfid/rfid_reader_cm5121.h>
33 #include <librfid/rfid_layer2_iso14443a.h>
34 #include <librfid/rfid_layer2_iso15693.h>
35 #include <librfid/rfid_protocol_mifare_classic.h>
37 #include "rfid_iso14443_common.h"
44 #define RC632_TMO_AUTH1 140
46 #define TIMER_RELAX_FACTOR 10
48 #define ENTER() DEBUGP("entering\n")
49 const struct rfid_asic rc632;
51 struct register_file {
56 /* Register and FIFO Access functions */
58 rc632_reg_write(struct rfid_asic_handle *handle,
62 return handle->rath->rat->priv.rc632.fn.reg_write(handle->rath, reg, val);
66 rc632_reg_read(struct rfid_asic_handle *handle,
70 return handle->rath->rat->priv.rc632.fn.reg_read(handle->rath, reg, val);
74 rc632_fifo_write(struct rfid_asic_handle *handle,
79 return handle->rath->rat->priv.rc632.fn.fifo_write(handle->rath,
84 rc632_fifo_read(struct rfid_asic_handle *handle,
88 return handle->rath->rat->priv.rc632.fn.fifo_read(handle->rath, len, buf);
93 rc632_set_bits(struct rfid_asic_handle *handle,
100 ret = rc632_reg_read(handle, reg, &tmp);
104 /* if bits are already set, no need to set them again */
105 if ((tmp & val) == val)
108 return rc632_reg_write(handle, reg, (tmp|val)&0xff);
111 rc632_set_bit_mask(struct rfid_asic_handle *handle,
112 u_int8_t reg, u_int8_t mask, u_int8_t val)
117 ret = rc632_reg_read(handle, reg, &tmp);
121 /* if bits are already like we want them, abort */
122 if ((tmp & mask) == val)
125 return rc632_reg_write(handle, reg, (tmp & ~mask)|(val & mask));
129 rc632_clear_bits(struct rfid_asic_handle *handle,
136 ret = rc632_reg_read(handle, reg, &tmp);
138 DEBUGP("error during reg_read(%p, %d):%d\n",
142 /* if bits are already cleared, no need to clear them again */
143 if ((tmp & val) == 0)
146 return rc632_reg_write(handle, reg, (tmp & ~val)&0xff);
150 rc632_clear_irqs(struct rfid_asic_handle *handle, u_int8_t bits)
152 return rc632_reg_write(handle, RC632_REG_INTERRUPT_RQ, (~RC632_INT_SET)&bits);
156 rc632_rf_power(struct rfid_asic_handle *handle, int on)
160 return rc632_set_bits(handle, RC632_REG_TX_CONTROL,
161 RC632_TXCTRL_TX1_RF_EN|
162 RC632_TXCTRL_TX2_RF_EN);
164 return rc632_clear_bits(handle, RC632_REG_TX_CONTROL,
165 RC632_TXCTRL_TX1_RF_EN|
166 RC632_TXCTRL_TX2_RF_EN);
170 rc632_power(struct rfid_asic_handle *handle, int on)
174 return rc632_clear_bits(handle, RC632_REG_CONTROL,
175 RC632_CONTROL_POWERDOWN);
177 return rc632_set_bits(handle, RC632_REG_CONTROL,
178 RC632_CONTROL_POWERDOWN);
182 rc632_execute_script(struct rfid_asic_handle *h, struct register_file *f,
187 for (i = 0; i < len; i++) {
188 ret = rc632_reg_write(h, f[i].reg, f[i].val);
196 /* calculate best 8bit prescaler and divisor for given usec timeout */
197 static int best_prescaler(u_int64_t timeout, u_int8_t *prescaler,
200 u_int8_t best_prescaler, best_divisor, i;
201 int64_t smallest_diff;
203 smallest_diff = LLONG_MAX;
206 for (i = 0; i < 21; i++) {
207 u_int64_t clk, tmp_div, res;
209 clk = 13560000 / (1 << i);
210 tmp_div = (clk * timeout) / 1000000;
213 if ((tmp_div > 0xff) || (tmp_div > clk))
216 res = 1000000 / (clk / tmp_div);
217 diff = res - timeout;
222 if (diff < smallest_diff) {
224 best_divisor = tmp_div;
225 smallest_diff = diff;
229 *prescaler = best_prescaler;
230 *divisor = best_divisor;
232 DEBUGP("timeout %u usec, prescaler = %u, divisor = %u\n",
233 timeout, best_prescaler, best_divisor);
239 rc632_timer_set(struct rfid_asic_handle *handle,
243 u_int8_t prescaler, divisor, irq;
245 timeout *= TIMER_RELAX_FACTOR;
247 ret = best_prescaler(timeout, &prescaler, &divisor);
249 ret = rc632_reg_write(handle, RC632_REG_TIMER_CLOCK,
254 ret = rc632_reg_write(handle, RC632_REG_TIMER_CONTROL,
255 RC632_TMR_START_TX_END|RC632_TMR_STOP_RX_BEGIN);
257 /* clear timer irq bit */
258 ret = rc632_clear_irqs(handle, RC632_IRQ_TIMER);
260 /* enable timer IRQ */
261 ret |= rc632_reg_write(handle, RC632_REG_INTERRUPT_EN, RC632_IRQ_SET | RC632_IRQ_TIMER);
263 ret |= rc632_reg_write(handle, RC632_REG_TIMER_RELOAD, divisor);
268 /* Wait until RC632 is idle or TIMER IRQ has happened */
269 static int rc632_wait_idle_timer(struct rfid_asic_handle *handle)
272 u_int8_t stat, irq, cmd;
274 ret = rc632_reg_read(handle, RC632_REG_INTERRUPT_EN, &irq);
277 DEBUGP_INTERRUPT_FLAG("irq_en",irq);
279 ret = rc632_reg_write(handle, RC632_REG_INTERRUPT_EN, RC632_IRQ_SET
287 rc632_reg_read(handle, RC632_REG_PRIMARY_STATUS, &stat);
288 DEBUGP_STATUS_FLAG(stat);
289 if (stat & RC632_STAT_ERR) {
291 ret = rc632_reg_read(handle, RC632_REG_ERROR_FLAG, &err);
294 DEBUGP_ERROR_FLAG(err);
295 if (err & (RC632_ERR_FLAG_COL_ERR |
296 RC632_ERR_FLAG_PARITY_ERR |
297 RC632_ERR_FLAG_FRAMING_ERR |
298 /* FIXME: why get we CRC errors in CL2 anticol at iso14443a operation with mifare UL? */
299 /* RC632_ERR_FLAG_CRC_ERR | */
303 if (stat & RC632_STAT_IRQ) {
304 ret = rc632_reg_read(handle, RC632_REG_INTERRUPT_RQ, &irq);
307 DEBUGP_INTERRUPT_FLAG("irq_rq",irq);
309 if (irq & RC632_IRQ_TIMER && !(irq & RC632_IRQ_RX)) {
310 DEBUGP("timer expired before RX!!\n");
311 rc632_clear_irqs(handle, RC632_IRQ_TIMER);
316 ret = rc632_reg_read(handle, RC632_REG_COMMAND, &cmd);
321 rc632_clear_irqs(handle, RC632_IRQ_RX);
325 /* poll every millisecond */
330 /* Stupid RC632 implementations don't evaluate interrupts but poll the
331 * command register for "status idle" */
333 rc632_wait_idle(struct rfid_asic_handle *handle, u_int64_t timeout)
337 #define USLEEP_PER_CYCLE 128
339 timeout *= TIMER_RELAX_FACTOR;
342 ret = rc632_reg_read(handle, RC632_REG_COMMAND, &cmd);
348 rc632_reg_read(handle, RC632_REG_PRIMARY_STATUS, &foo);
349 DEBUGP_STATUS_FLAG(foo);
350 /* check if Error has occured (ERR flag set) */
351 if (foo & RC632_STAT_ERR) {
352 rc632_reg_read(handle, RC632_REG_ERROR_FLAG, &foo);
353 DEBUGP_ERROR_FLAG(foo);
355 /* check if IRQ has occurred (IRQ flag set)*/
356 if (foo & RC632_STAT_IRQ) {
357 ret = rc632_reg_read(handle, RC632_REG_INTERRUPT_RQ, &foo);
358 DEBUGP_INTERRUPT_FLAG("irq_rq",foo);
359 /* clear all interrupts */
360 ret = rc632_clear_irqs(handle, 0xff);
366 /* FIXME: read second time ?? */
367 DEBUGP("cmd == 0 (IDLE)\n");
371 /* Abort after some timeout */
372 if (cycles > timeout/USLEEP_PER_CYCLE) {
373 DEBUGP("timeout...\n");
378 usleep(USLEEP_PER_CYCLE);
385 rc632_transmit(struct rfid_asic_handle *handle,
391 const u_int8_t *cur_buf = buf;
393 DEBUGP("timeout=%u, tx_len=%u\n", timeout, len);
401 ret = rc632_fifo_write(handle, cur_len, cur_buf, 0x03);
405 if (cur_buf == buf) {
406 /* only start transmit first time */
407 ret = rc632_reg_write(handle, RC632_REG_COMMAND,
414 if (cur_buf < buf + len) {
415 cur_len = buf - cur_buf;
423 return rc632_wait_idle(handle, timeout);
427 tcl_toggle_pcb(struct rfid_asic_handle *handle)
429 /* FIXME: toggle something between 0x0a and 0x0b */
434 rc632_transceive(struct rfid_asic_handle *handle,
435 const u_int8_t *tx_buf,
442 int ret, cur_tx_len, i;
444 const u_int8_t *cur_tx_buf = tx_buf;
446 DEBUGP("timeout=%u, rx_len=%u, tx_len=%u\n", timer, *rx_len, tx_len);
454 ret = rc632_reg_write(handle, RC632_REG_COMMAND, RC632_CMD_IDLE);
455 /* clear all interrupts */
456 ret = rc632_reg_write(handle, RC632_REG_INTERRUPT_RQ, 0x7f);
459 rc632_reg_read(handle, RC632_REG_PRIMARY_STATUS, &tmp);
460 DEBUGP_STATUS_FLAG(tmp);
461 rc632_reg_read(handle, RC632_REG_ERROR_FLAG, &tmp);
462 DEBUGP_ERROR_FLAG(tmp);
465 ret = rc632_timer_set(handle, timer);
470 ret = rc632_fifo_write(handle, cur_tx_len, cur_tx_buf, 0x03);
474 if (cur_tx_buf == tx_buf) {
475 ret = rc632_reg_write(handle, RC632_REG_COMMAND,
476 RC632_CMD_TRANSCEIVE);
481 cur_tx_buf += cur_tx_len;
482 if (cur_tx_buf < tx_buf + tx_len) {
484 ret = rc632_reg_read(handle, RC632_REG_FIFO_LENGTH,
489 cur_tx_len = 64 - fifo_fill;
493 } while (cur_tx_len);
496 tcl_toggle_pcb(handle);
498 ret = rc632_wait_idle_timer(handle);
499 //ret = rc632_wait_idle(handle, timer);
501 DEBUGP("rc632_wait_idle >> ret=%d %s\n",ret,(ret==-ETIMEDOUT)?"ETIMEDOUT":"");
505 ret = rc632_reg_read(handle, RC632_REG_FIFO_LENGTH, &rx_avail);
509 if (rx_avail > *rx_len)
510 DEBUGP("rx_avail(%d) > rx_len(%d), JFYI\n", rx_avail, *rx_len);
511 else if (*rx_len > rx_avail)
514 DEBUGP("rx_len == %d\n",*rx_len);
519 for (i = 0; i < 1; i++){
520 rc632_reg_read(handle, RC632_REG_PRIMARY_STATUS, &tmp);
521 DEBUGP_STATUS_FLAG(tmp);
522 rc632_reg_read(handle, RC632_REG_ERROR_FLAG, &tmp);
523 DEBUGP_ERROR_FLAG(tmp);
525 rc632_reg_read(handle, RC632_REG_CHANNEL_REDUNDANCY, &tmp);
531 return rc632_fifo_read(handle, *rx_len, rx_buf);
532 /* FIXME: discard addidional bytes in FIFO */
537 rc632_receive(struct rfid_asic_handle *handle,
542 int ret, cur_tx_len, i;
545 DEBUGP("timeout=%u, rx_len=%u\n", timer, *rx_len);
546 ret = rc632_reg_write(handle, RC632_REG_COMMAND, 0x00); /* IDLE */
547 /* clear all interrupts */
548 ret = rc632_reg_write(handle, RC632_REG_INTERRUPT_RQ, 0x7f);
550 ret = rc632_timer_set(handle, timer);
554 ret = rc632_reg_write(handle, RC632_REG_COMMAND,RC632_CMD_RECEIVE);
558 /* the timer cannot start in hardware based on the command we just
559 * sent. this means that our timing will always be quite a bit more lax,
560 * i.e. we'll always wait for a bit longer than the specs ask us to. */
561 ret = rc632_set_bits(handle, RC632_REG_CONTROL,
562 RC632_CONTROL_TIMER_START);
566 //ret = rc632_wait_idle(handle, timer);
567 ret = rc632_wait_idle_timer(handle);
571 ret = rc632_reg_read(handle, RC632_REG_FIFO_LENGTH, &rx_avail);
575 if (rx_avail > *rx_len) {
576 //DEBUGP("rx_avail(%d) > rx_len(%d), JFYI\n", rx_avail, *rx_len);
577 } else if (*rx_len > rx_avail)
583 DEBUGP("rx_len == 0\n");
585 for (i = 0; i < 1; i++) {
586 rc632_reg_read(handle, RC632_REG_PRIMARY_STATUS, &tmp);
587 DEBUGP_STATUS_FLAG(tmp);
588 rc632_reg_read(handle, RC632_REG_ERROR_FLAG, &tmp);
589 DEBUGP_ERROR_FLAG(tmp);
592 rc632_reg_read(handle, RC632_REG_CHANNEL_REDUNDANCY, &tmp);
596 return rc632_fifo_read(handle, *rx_len, rx_buf);
597 /* FIXME: discard additional bytes in FIFO */
600 #define MAX_WRITE_LEN 16 /* see Sec. 18.6.1.2 of RC632 Spec Rev. 3.2. */
603 rc632_write_eeprom(struct rfid_asic_handle *handle, u_int16_t addr,
604 u_int8_t *data, u_int8_t len)
606 u_int8_t sndbuf[MAX_WRITE_LEN + 2];
610 if (len > MAX_WRITE_LEN)
617 sndbuf[0] = addr & 0x00ff; /* LSB */
618 sndbuf[1] = addr >> 8; /* MSB */
619 memcpy(&sndbuf[2], data, len);
621 ret = rc632_fifo_write(handle, len + 2, sndbuf, 0x03);
625 ret = rc632_reg_write(handle, RC632_REG_COMMAND, RC632_CMD_WRITE_E2);
629 ret = rc632_reg_read(handle, RC632_REG_ERROR_FLAG, ®);
633 if (reg & RC632_ERR_FLAG_ACCESS_ERR)
638 ret = rc632_reg_read(handle, RC632_REG_SECONDARY_STATUS, ®);
642 if (reg & RC632_SEC_ST_E2_READY) {
643 /* the E2Write command must be terminated, See sec. 18.6.1.3 */
644 ret = rc632_reg_write(handle, RC632_REG_COMMAND, RC632_CMD_IDLE);
653 rc632_read_eeprom(struct rfid_asic_handle *handle, u_int16_t addr,
654 u_int8_t *buf, u_int8_t len)
660 sndbuf[0] = addr & 0xff;
661 sndbuf[1] = addr >> 8;
664 ret = rc632_fifo_write(handle, 3, sndbuf, 0x03);
668 ret = rc632_reg_write(handle, RC632_REG_COMMAND, RC632_CMD_READ_E2);
672 ret = rc632_reg_read(handle, RC632_REG_ERROR_FLAG, ®);
676 if (reg & RC632_ERR_FLAG_ACCESS_ERR)
681 return rc632_fifo_read(handle, len, buf);
685 rc632_calc_crc16_from(struct rfid_asic_handle *handle)
687 u_int8_t sndbuf[2] = { 0x01, 0x02 };
688 u_int8_t crc_lsb = 0x00 , crc_msb = 0x00;
691 ret = rc632_reg_write(handle, RC632_REG_CRC_PRESET_LSB, 0x12);
695 ret = rc632_reg_write(handle, RC632_REG_CRC_PRESET_MSB, 0xe0);
699 ret = rc632_fifo_write(handle, sizeof(sndbuf), sndbuf, 3);
703 ret = rc632_reg_write(handle, RC632_REG_COMMAND, RC632_CMD_CALC_CRC);
707 usleep(10000); /* FIXME: no checking for cmd completion? *
709 ret = rc632_reg_read(handle, RC632_REG_CRC_RESULT_LSB, &crc_lsb);
713 ret = rc632_reg_read(handle, RC632_REG_CRC_RESULT_MSB, &crc_msb);
717 /* FIXME: what to do with crc result? */
723 rc632_register_dump(struct rfid_asic_handle *handle, u_int8_t *buf)
728 for (i = 0; i <= 0x3f; i++)
729 ret |= rc632_reg_read(handle, i, &buf[i]);
734 /* generic FIFO access functions (if no more efficient ones provided by
735 * transport driver) */
740 /* FIXME: implementation (not needed for CM 5121) */
747 /* FIXME: implementation (not neded for CM 5121) */
752 rc632_init(struct rfid_asic_handle *ah)
756 /* switch off rf (make sure PICCs are reset at init time) */
757 ret = rc632_power(ah, 0);
764 ret = rc632_power(ah, 1);
768 /* disable register paging */
769 ret = rc632_reg_write(ah, 0x00, 0x00);
773 /* set some sane default values */
774 ret = rc632_reg_write(ah, 0x11, 0x5b);
779 ret = rc632_rf_power(ah, 0);
786 ret = rc632_rf_power(ah, 1);
794 rc632_fini(struct rfid_asic_handle *ah)
799 ret = rc632_rf_power(ah, 0);
803 ret = rc632_power(ah, 0);
810 struct rfid_asic_handle *
811 rc632_open(struct rfid_asic_transport_handle *th)
813 struct rfid_asic_handle *h;
815 h = malloc_asic_handle(sizeof(*h));
818 memset(h, 0, sizeof(*h));
820 h->asic = (void*)&rc632;
823 /* FIXME: this is only cm5121 specific, since the latency
824 * down to the RC632 FIFO is too long to refill during TX/RX */
825 h->mtu = h->mru = 64;
827 if (rc632_init(h) < 0) {
836 rc632_close(struct rfid_asic_handle *h)
846 /* Register file for ISO14443A standard */
847 static struct register_file iso14443a_script[] = {
849 .reg = RC632_REG_TX_CONTROL,
850 .val = RC632_TXCTRL_MOD_SRC_INT |
851 RC632_TXCTRL_TX2_INV |
852 RC632_TXCTRL_FORCE_100_ASK |
853 RC632_TXCTRL_TX2_RF_EN |
854 RC632_TXCTRL_TX1_RF_EN,
856 .reg = RC632_REG_CW_CONDUCTANCE,
857 .val = CM5121_CW_CONDUCTANCE,
859 .reg = RC632_REG_MOD_CONDUCTANCE,
860 .val = CM5121_MOD_CONDUCTANCE,
862 .reg = RC632_REG_CODER_CONTROL,
863 .val = (RC632_CDRCTRL_TXCD_14443A |
864 RC632_CDRCTRL_RATE_106K),
866 .reg = RC632_REG_MOD_WIDTH,
869 .reg = RC632_REG_MOD_WIDTH_SOF,
872 .reg = RC632_REG_TYPE_B_FRAMING,
875 .reg = RC632_REG_RX_CONTROL1,
876 .val = (RC632_RXCTRL1_GAIN_35DB |
877 RC632_RXCTRL1_ISO14443 |
878 RC632_RXCTRL1_SUBCP_8),
880 .reg = RC632_REG_DECODER_CONTROL,
881 .val = (RC632_DECCTRL_MANCHESTER |
882 RC632_DECCTRL_RXFR_14443A),
884 .reg = RC632_REG_BIT_PHASE,
885 .val = CM5121_14443A_BITPHASE,
887 .reg = RC632_REG_RX_THRESHOLD,
888 .val = CM5121_14443A_THRESHOLD,
890 .reg = RC632_REG_BPSK_DEM_CONTROL,
893 .reg = RC632_REG_RX_CONTROL2,
894 .val = (RC632_RXCTRL2_DECSRC_INT |
895 RC632_RXCTRL2_CLK_Q),
897 .reg = RC632_REG_RX_WAIT,
898 //.val = 0x03, /* default value */
899 .val = 0x06, /* omnikey */
901 .reg = RC632_REG_CHANNEL_REDUNDANCY,
902 .val = (RC632_CR_PARITY_ENABLE |
903 RC632_CR_PARITY_ODD),
905 .reg = RC632_REG_CRC_PRESET_LSB,
908 .reg = RC632_REG_CRC_PRESET_MSB,
914 rc632_iso14443a_init(struct rfid_asic_handle *handle)
918 /* flush fifo (our way) */
919 ret = rc632_reg_write(handle, RC632_REG_CONTROL,
920 RC632_CONTROL_FIFO_FLUSH);
922 ret = rc632_execute_script(handle, iso14443a_script,
923 ARRAY_SIZE(iso14443a_script));
931 rc632_iso14443a_fini(struct iso14443a_handle *handle_14443)
935 ret = rc632_rf_power(handle, 0);
945 /* issue a 14443-3 A PCD -> PICC command in a short frame, such as REQA, WUPA */
947 rc632_iso14443a_transceive_sf(struct rfid_asic_handle *handle,
949 struct iso14443a_atqa *atqa)
956 memset(atqa, 0, sizeof(*atqa));
960 /* transfer only 7 bits of last byte in frame */
961 ret = rc632_reg_write(handle, RC632_REG_BIT_FRAMING, 0x07);
965 ret = rc632_clear_bits(handle, RC632_REG_CONTROL,
966 RC632_CONTROL_CRYPTO1_ON);
971 ret = rc632_reg_write(handle, RC632_REG_CHANNEL_REDUNDANCY,
972 (RC632_CR_PARITY_ENABLE |
973 RC632_CR_PARITY_ODD));
975 ret = rc632_clear_bits(handle, RC632_REG_CHANNEL_REDUNDANCY,
976 RC632_CR_RX_CRC_ENABLE|RC632_CR_TX_CRC_ENABLE);
982 ret = rc632_transceive(handle, tx_buf, sizeof(tx_buf),
983 (u_int8_t *)atqa, &rx_len,
984 ISO14443A_FDT_ANTICOL_LAST1, 0);
986 DEBUGP("error during rc632_transceive()\n");
990 /* switch back to normal 8bit last byte */
991 ret = rc632_reg_write(handle, RC632_REG_BIT_FRAMING, 0x00);
995 /* determine whether there was a collission */
996 ret = rc632_reg_read(handle, RC632_REG_ERROR_FLAG, &error_flag);
1000 if (error_flag & RC632_ERR_FLAG_COL_ERR) {
1002 /* retrieve bit of collission */
1003 ret = rc632_reg_read(handle, RC632_REG_COLL_POS, &boc);
1006 DEBUGP("collision detected in xcv_sf: bit_of_col=%u\n", boc);
1007 /* FIXME: how to signal this up the stack */
1011 DEBUGP("rx_len(%d) != 2\n", rx_len);
1018 /* transceive regular frame */
1020 rc632_iso14443ab_transceive(struct rfid_asic_handle *handle,
1021 unsigned int frametype,
1022 const u_int8_t *tx_buf, unsigned int tx_len,
1023 u_int8_t *rx_buf, unsigned int *rx_len,
1024 u_int64_t timeout, unsigned int flags)
1028 u_int8_t channel_red;
1035 memset(rx_buf, 0, *rx_len);
1037 switch (frametype) {
1038 case RFID_14443A_FRAME_REGULAR:
1039 case RFID_MIFARE_FRAME:
1040 channel_red = RC632_CR_RX_CRC_ENABLE|RC632_CR_TX_CRC_ENABLE
1041 |RC632_CR_PARITY_ENABLE|RC632_CR_PARITY_ODD;
1043 case RFID_14443B_FRAME_REGULAR:
1044 channel_red = RC632_CR_RX_CRC_ENABLE|RC632_CR_TX_CRC_ENABLE
1048 case RFID_MIFARE_FRAME:
1049 channel_red = RC632_CR_PARITY_ENABLE|RC632_CR_PARITY_ODD;
1052 case RFID_15693_FRAME:
1053 channel_red = RC632_CR_CRC3309 | RC632_CR_RX_CRC_ENABLE
1054 | RC632_CR_TX_CRC_ENABLE;
1056 case RFID_15693_FRAME_ICODE1:
1057 /* FIXME: implement */
1062 ret = rc632_reg_write(handle, RC632_REG_CHANNEL_REDUNDANCY,
1066 DEBUGP("tx_len=%u\n",tx_len);
1067 ret = rc632_transceive(handle, tx_buf, tx_len, rx_buf, &rxl, timeout, 0);
1076 /* transceive anti collission bitframe */
1078 rc632_iso14443a_transceive_acf(struct rfid_asic_handle *handle,
1079 struct iso14443a_anticol_cmd *acf,
1080 unsigned int *bit_of_col)
1083 u_int8_t rx_buf[64];
1084 u_int8_t rx_len = sizeof(rx_buf);
1085 u_int8_t rx_align = 0, tx_last_bits, tx_bytes, tx_bytes_total;
1087 u_int8_t error_flag;
1088 *bit_of_col = ISO14443A_BITOFCOL_NONE;
1089 memset(rx_buf, 0, sizeof(rx_buf));
1091 /* disable mifare cryto */
1092 ret = rc632_clear_bits(handle, RC632_REG_CONTROL,
1093 RC632_CONTROL_CRYPTO1_ON);
1097 /* disable CRC summing */
1099 ret = rc632_reg_write(handle, RC632_REG_CHANNEL_REDUNDANCY,
1100 (RC632_CR_PARITY_ENABLE |
1101 RC632_CR_PARITY_ODD));
1103 ret = rc632_clear_bits(handle, RC632_REG_CHANNEL_REDUNDANCY,
1104 RC632_CR_TX_CRC_ENABLE|RC632_CR_TX_CRC_ENABLE);
1109 tx_last_bits = acf->nvb & 0x07; /* lower nibble indicates bits */
1110 tx_bytes = ( acf->nvb >> 4 ) & 0x07;
1112 tx_bytes_total = tx_bytes+1;
1113 rx_align = tx_last_bits & 0x07; /* rx frame complements tx */
1116 tx_bytes_total = tx_bytes;
1118 /* set RxAlign and TxLastBits*/
1119 ret = rc632_reg_write(handle, RC632_REG_BIT_FRAMING,
1120 (rx_align << 4) | (tx_last_bits));
1124 ret = rc632_transceive(handle, (u_int8_t *)acf, tx_bytes_total,
1125 rx_buf, &rx_len, 0x32, 0);
1129 /* bitwise-OR the two halves of the split byte */
1130 acf->uid_bits[tx_bytes-2] = (
1131 (acf->uid_bits[tx_bytes-2] & (0xff >> (8-tx_last_bits)))
1136 memcpy(&acf->uid_bits[tx_bytes-1], &rx_buf[1], rx_len-1);
1138 /* determine whether there was a collission */
1139 ret = rc632_reg_read(handle, RC632_REG_ERROR_FLAG, &error_flag);
1143 if (error_flag & RC632_ERR_FLAG_COL_ERR) {
1144 /* retrieve bit of collission */
1145 ret = rc632_reg_read(handle, RC632_REG_COLL_POS, &boc);
1149 /* bit of collission relative to start of part 1 of
1150 * anticollision frame (!) */
1151 *bit_of_col = 2*8 + boc;
1158 RC632_RATE_106 = 0x00,
1159 RC632_RATE_212 = 0x01,
1160 RC632_RATE_424 = 0x02,
1161 RC632_RATE_848 = 0x03,
1165 u_int8_t subc_pulses;
1167 u_int8_t rx_threshold;
1168 u_int8_t bpsk_dem_ctrl;
1176 static struct rx_config rx_configs[] = {
1178 .subc_pulses = RC632_RXCTRL1_SUBCP_8,
1179 .rx_coding = RC632_DECCTRL_MANCHESTER,
1180 .rx_threshold = 0x88,
1181 .bpsk_dem_ctrl = 0x00,
1184 .subc_pulses = RC632_RXCTRL1_SUBCP_4,
1185 .rx_coding = RC632_DECCTRL_BPSK,
1186 .rx_threshold = 0x50,
1187 .bpsk_dem_ctrl = 0x0c,
1190 .subc_pulses = RC632_RXCTRL1_SUBCP_2,
1191 .rx_coding = RC632_DECCTRL_BPSK,
1192 .rx_threshold = 0x50,
1193 .bpsk_dem_ctrl = 0x0c,
1196 .subc_pulses = RC632_RXCTRL1_SUBCP_1,
1197 .rx_coding = RC632_DECCTRL_BPSK,
1198 .rx_threshold = 0x50,
1199 .bpsk_dem_ctrl = 0x0c,
1203 static struct tx_config tx_configs[] = {
1205 .rate = RC632_CDRCTRL_RATE_106K,
1209 .rate = RC632_CDRCTRL_RATE_212K,
1213 .rate = RC632_CDRCTRL_RATE_424K,
1217 .rate = RC632_CDRCTRL_RATE_848K,
1222 static int rc632_iso14443a_set_speed(struct rfid_asic_handle *handle,
1223 unsigned int tx, unsigned int rate)
1231 if (rate > ARRAY_SIZE(rx_configs))
1234 rc = rc632_set_bit_mask(handle, RC632_REG_RX_CONTROL1,
1235 RC632_RXCTRL1_SUBCP_MASK,
1236 rx_configs[rate].subc_pulses);
1240 rc = rc632_set_bit_mask(handle, RC632_REG_DECODER_CONTROL,
1242 rx_configs[rate].rx_coding);
1246 rc = rc632_reg_write(handle, RC632_REG_RX_THRESHOLD,
1247 rx_configs[rate].rx_threshold);
1251 if (rx_configs[rate].rx_coding == RC632_DECCTRL_BPSK) {
1252 rc = rc632_reg_write(handle,
1253 RC632_REG_BPSK_DEM_CONTROL,
1254 rx_configs[rate].bpsk_dem_ctrl);
1260 if (rate > ARRAY_SIZE(tx_configs))
1263 rc = rc632_set_bit_mask(handle, RC632_REG_CODER_CONTROL,
1264 RC632_CDRCTRL_RATE_MASK,
1265 tx_configs[rate].rate);
1269 rc = rc632_reg_write(handle, RC632_REG_MOD_WIDTH,
1270 tx_configs[rate].mod_width);
1279 static struct register_file iso14443b_script[] = {
1281 .reg = RC632_REG_TX_CONTROL,
1282 .val = (RC632_TXCTRL_TX1_RF_EN |
1283 RC632_TXCTRL_TX2_RF_EN |
1284 RC632_TXCTRL_TX2_INV |
1285 RC632_TXCTRL_MOD_SRC_INT),
1287 .reg = RC632_REG_CW_CONDUCTANCE,
1290 .reg = RC632_REG_MOD_CONDUCTANCE,
1293 .reg = RC632_REG_CODER_CONTROL,
1294 .val = (RC632_CDRCTRL_TXCD_NRZ |
1295 RC632_CDRCTRL_RATE_14443B),
1297 .reg = RC632_REG_MOD_WIDTH,
1300 .reg = RC632_REG_MOD_WIDTH_SOF,
1303 .reg = RC632_REG_TYPE_B_FRAMING,
1304 .val = (RC632_TBFRAMING_SOF_11L_3H |
1305 (6 << RC632_TBFRAMING_SPACE_SHIFT) |
1306 RC632_TBFRAMING_EOF_11);
1308 .reg = RC632_REG_RX_CONTROL1,
1309 .val = (RC632_RXCTRL1_GAIN_35DB |
1310 RC632_RXCTRL1_ISO14443,
1311 RC632_RXCTRL1_SUBCP_8),
1313 .reg = RC632_REG_DECODER_CONTROL,
1314 .val = (RC632_DECCTRL_BPSK |
1315 RC632_DECCTRL_RXFR_14443B),
1317 .reg = RC632_REG_BIT_PHASE,
1318 .val = CM5121_14443B_BITPHASE,
1320 .reg = RC632_REG_RX_THRESHOLD,
1321 .val = CM5121_14443B_THRESHOLD,
1323 .reg = RC632_REG_BPSK_DEM_CONTROL,
1324 .val = ((0x2 & RC632_BPSKD_TAUB_MASK)<<RC632_BPSKD_TAUB_SHIFT |
1325 (0x3 & RC632_BPSKD_TAUD_MASK)<<RC632_BPSKD_TAUD_SHIFT |
1326 RC632_BPSKD_FILTER_AMP_DETECT |
1327 RC632_BPSKD_NO_RX_EOF |
1328 RC632_BPSKD_NO_RX_EGT),
1330 .reg = RC632_REG_RX_CONTROL2,
1331 .val = (RC632_RXCTRL2_AUTO_PD |
1332 RC632_RXCTRL2_DECSRC_INT),
1334 .reg = RC632_REG_RX_WAIT,
1337 .reg = RC632_REG_CHANNEL_REDUNDANCY,
1338 .val = (RC632_CR_TX_CRC_ENABLE |
1339 RC632_CR_RX_CRC_ENABLE |
1342 .reg = RC632_REG_CRC_PRESET_LSB,
1345 .reg = RC632_REG_CRC_PRESET_MSB,
1351 static int rc632_iso14443b_init(struct rfid_asic_handle *handle)
1355 /* FIXME: some FIFO work */
1357 /* flush fifo (our way) */
1358 ret = rc632_reg_write(handle, RC632_REG_CONTROL,
1359 RC632_CONTROL_FIFO_FLUSH);
1363 ret = rc632_reg_write(handle, RC632_REG_TX_CONTROL,
1364 (RC632_TXCTRL_TX1_RF_EN |
1365 RC632_TXCTRL_TX2_RF_EN |
1366 RC632_TXCTRL_TX2_INV |
1367 RC632_TXCTRL_MOD_SRC_INT));
1371 ret = rc632_reg_write(handle, RC632_REG_CW_CONDUCTANCE, 0x3f);
1375 ret = rc632_reg_write(handle, RC632_REG_MOD_CONDUCTANCE, 0x04);
1379 ret = rc632_reg_write(handle, RC632_REG_CODER_CONTROL,
1380 (RC632_CDRCTRL_TXCD_NRZ |
1381 RC632_CDRCTRL_RATE_14443B));
1385 ret = rc632_reg_write(handle, RC632_REG_MOD_WIDTH, 0x13);
1389 ret = rc632_reg_write(handle, RC632_REG_MOD_WIDTH_SOF, 0x3f);
1393 ret = rc632_reg_write(handle, RC632_REG_TYPE_B_FRAMING,
1394 (RC632_TBFRAMING_SOF_11L_3H |
1395 (6 << RC632_TBFRAMING_SPACE_SHIFT) |
1396 RC632_TBFRAMING_EOF_11));
1400 ret = rc632_reg_write(handle, RC632_REG_RX_CONTROL1,
1401 (RC632_RXCTRL1_GAIN_35DB |
1402 RC632_RXCTRL1_ISO14443 |
1403 RC632_RXCTRL1_SUBCP_8));
1407 ret = rc632_reg_write(handle, RC632_REG_DECODER_CONTROL,
1408 (RC632_DECCTRL_BPSK |
1409 RC632_DECCTRL_RXFR_14443B));
1413 ret = rc632_reg_write(handle, RC632_REG_BIT_PHASE,
1414 CM5121_14443B_BITPHASE);
1418 ret = rc632_reg_write(handle, RC632_REG_RX_THRESHOLD,
1419 CM5121_14443B_THRESHOLD);
1423 ret = rc632_reg_write(handle, RC632_REG_BPSK_DEM_CONTROL,
1424 ((0x2 & RC632_BPSKD_TAUB_MASK)<<RC632_BPSKD_TAUB_SHIFT |
1425 (0x3 & RC632_BPSKD_TAUD_MASK)<<RC632_BPSKD_TAUD_SHIFT |
1426 RC632_BPSKD_FILTER_AMP_DETECT |
1427 RC632_BPSKD_NO_RX_EOF |
1428 RC632_BPSKD_NO_RX_EGT));
1432 ret = rc632_reg_write(handle, RC632_REG_RX_CONTROL2,
1433 (RC632_RXCTRL2_AUTO_PD |
1434 RC632_RXCTRL2_DECSRC_INT));
1438 ret = rc632_reg_write(handle, RC632_REG_RX_WAIT, 0x03);
1442 ret = rc632_reg_write(handle, RC632_REG_CHANNEL_REDUNDANCY,
1443 (RC632_CR_TX_CRC_ENABLE |
1444 RC632_CR_RX_CRC_ENABLE |
1449 ret = rc632_reg_write(handle, RC632_REG_CRC_PRESET_LSB, 0xff);
1453 ret = rc632_reg_write(handle, RC632_REG_CRC_PRESET_MSB, 0xff);
1466 /* Register file for ISO15693 standard */
1467 static struct register_file iso15693_fast_script[] = {
1469 .reg = RC632_REG_TX_CONTROL,
1470 .val = RC632_TXCTRL_MOD_SRC_INT |
1471 RC632_TXCTRL_TX2_INV |
1472 RC632_TXCTRL_TX2_RF_EN |
1473 RC632_TXCTRL_TX1_RF_EN,
1475 .reg = RC632_REG_CW_CONDUCTANCE,
1478 .reg = RC632_REG_MOD_CONDUCTANCE,
1479 /* FIXME: nxp default for icode1/15693: 0x05 */
1481 .val = 0x21, /* omnikey */
1483 .reg = RC632_REG_CODER_CONTROL,
1484 .val = RC632_CDRCTRL_TXCD_15693_FAST |
1485 RC632_CDRCTRL_RATE_15693,
1487 .reg = RC632_REG_MOD_WIDTH,
1490 .reg = RC632_REG_MOD_WIDTH_SOF,
1493 .reg = RC632_REG_TYPE_B_FRAMING,
1496 .reg = RC632_REG_RX_CONTROL1,
1497 .val = RC632_RXCTRL1_ISO15693 |
1498 RC632_RXCTRL1_SUBCP_16 |
1499 RC632_RXCTRL1_GAIN_35DB,
1501 /* FIXME: this should always be the case */
1502 .reg = RC632_REG_RX_CONTROL2,
1503 .val = RC632_RXCTRL2_DECSRC_INT,
1505 .reg = RC632_REG_DECODER_CONTROL,
1506 .val = RC632_DECCTRL_MANCHESTER |
1507 RC632_DECCTRL_RX_INVERT |
1508 RC632_DECCTRL_ZEROAFTERCOL |
1509 RC632_DECCTRL_RXFR_15693,
1511 .reg = RC632_REG_BIT_PHASE,
1512 /* FIXME: nxp default for icode1/15693: 0x54 */
1514 .val = 0xd0, /* omnikey */
1516 .reg = RC632_REG_RX_THRESHOLD,
1517 /* FIXME: nxp default for icode1/15693: 0x68 */
1521 .reg = RC632_REG_BPSK_DEM_CONTROL,
1524 .reg = RC632_REG_CHANNEL_REDUNDANCY,
1525 .val = RC632_CR_RX_CRC_ENABLE |
1526 RC632_CR_TX_CRC_ENABLE |
1529 .reg = RC632_REG_CRC_PRESET_LSB,
1532 .reg = RC632_REG_CRC_PRESET_MSB,
1537 /* Register file for I*Code standard */
1538 static struct register_file icode1_std_script[] = {
1540 .reg = RC632_REG_TX_CONTROL,
1541 .val = RC632_TXCTRL_MOD_SRC_INT |
1542 RC632_TXCTRL_TX2_INV |
1543 RC632_TXCTRL_TX2_RF_EN |
1544 RC632_TXCTRL_TX1_RF_EN,
1546 .reg = RC632_REG_CW_CONDUCTANCE,
1549 .reg = RC632_REG_MOD_CONDUCTANCE,
1550 /* FIXME: nxp default for icode1/15693: 0x05 */
1553 .reg = RC632_REG_CODER_CONTROL,
1554 .val = RC632_CDRCTRL_TXCD_ICODE_STD |
1555 RC632_CDRCTRL_RATE_15693,
1557 .reg = RC632_REG_MOD_WIDTH,
1560 .reg = RC632_REG_MOD_WIDTH_SOF,
1563 .reg = RC632_REG_TYPE_B_FRAMING,
1566 .reg = RC632_REG_RX_CONTROL1,
1567 .val = RC632_RXCTRL1_ISO15693 |
1568 RC632_RXCTRL1_SUBCP_16 |
1569 RC632_RXCTRL1_GAIN_35DB,
1571 /* FIXME: this should always be the case */
1572 .reg = RC632_REG_RX_CONTROL2,
1573 .val = RC632_RXCTRL2_DECSRC_INT,
1575 .reg = RC632_REG_DECODER_CONTROL,
1576 .val = RC632_DECCTRL_MANCHESTER |
1577 RC632_DECCTRL_RXFR_ICODE,
1579 .reg = RC632_REG_BIT_PHASE,
1580 /* FIXME: nxp default for icode1/15693: 0x54 */
1583 .reg = RC632_REG_RX_THRESHOLD,
1584 /* FIXME: nxp default for icode1/15693: 0x68 */
1587 .reg = RC632_REG_BPSK_DEM_CONTROL,
1590 .reg = RC632_REG_CHANNEL_REDUNDANCY,
1591 /* 16bit CRC, no parity, not CRC3309 */
1592 .val = RC632_CR_RX_CRC_ENABLE |
1593 RC632_CR_TX_CRC_ENABLE,
1595 .reg = RC632_REG_CRC_PRESET_LSB,
1598 .reg = RC632_REG_CRC_PRESET_MSB,
1601 .reg = RC632_REG_INTERRUPT_EN,
1602 .val = RC632_INT_IDLE |
1609 /* incremental changes on top of icode1_std_script */
1610 static struct register_file icode1_fast_patch[] = {
1612 .reg = RC632_REG_CODER_CONTROL,
1613 .val = RC632_CDRCTRL_TXCD_ICODE_FAST |
1614 RC632_CDRCTRL_RATE_ICODE_FAST,
1616 .reg = RC632_REG_MOD_WIDTH_SOF,
1617 .val = 0x73, /* 18.88uS */
1623 rc632_iso15693_init(struct rfid_asic_handle *h)
1627 /* flush fifo (our way) */
1628 ret = rc632_reg_write(h, RC632_REG_CONTROL,
1629 RC632_CONTROL_FIFO_FLUSH);
1633 ret = rc632_execute_script(h, iso15693_fast_script,
1634 ARRAY_SIZE(iso15693_fast_script));
1642 rc632_iso15693_icode1_init(struct rfid_asic_handle *h)
1646 ret = rc632_execute_script(h, icode1_std_script,
1647 ARRAY_SIZE(icode1_std_script));
1651 /* FIXME: how to configure fast/slow properly? */
1654 ret = rc632_execute_script(h, icode1_fast_patch,
1655 ARRAY_SIZE(icode1_fast_patch));
1665 rc632_iso15693_icl_init(struct rfid_asic_handle *h)
1671 ret = rc632_reg_write(h, RC632_REG_TX_CONTROL,
1672 (RC632_TXCTRL_MOD_SRC_INT |
1673 RC632_TXCTRL_TX2_INV |
1674 RC632_TXCTRL_TX2_RF_EN |
1675 RC632_TXCTRL_TX1_RF_EN));
1679 ret = rc632_reg_write(h, RC632_REG_CW_CONDUCTANCE, 0x3f);
1683 ret = rc632_reg_write(h, RC632_REG_MOD_CONDUCTANCE, 0x11);
1687 ret = rc632_reg_write(h, RC632_REG_CODER_CONTROL,
1688 (RC632_CDRCTRL_RATE_15693 |
1689 RC632_CDRCTRL_TXCD_ICODE_STD |
1694 ret = rc632_reg_write(h, RC632_REG_MOD_WIDTH, 0x3f);
1698 ret = rc632_reg_write(h, RC632_REG_MOD_WIDTH_SOF, 0x3f);
1701 ret = rc632_reg_write(h, RC632_REG_RX_CONTROL1,
1702 (RC632_RXCTRL1_SUBCP_16|
1703 RC632_RXCTRL1_ISO15693|
1704 RC632_RXCTRL1_GAIN_35DB));
1707 ret = rc632_reg_write(h, RC632_REG_DECODER_CONTROL,
1708 (RC632_DECCTRL_RX_INVERT|
1709 RC632_DECCTRL_RXFR_15693));
1713 ret = rc632_reg_write(h, RC632_REG_BIT_PHASE, 0xbd);
1717 ret = rc632_reg_write(h, RC632_REG_RX_THRESHOLD, 0xff);
1721 ret = rc632_reg_write(h, RC632_REG_BPSK_DEM_CONTROL, 0x00);
1725 ret = rc632_reg_write(h, RC632_REG_RX_CONTROL2,
1726 RC632_RXCTRL2_DECSRC_INT);
1730 ret = rc632_reg_write(h, RC632_REG_CHANNEL_REDUNDANCY, 0x00);
1734 ret = rc632_reg_write(h, RC632_REG_CRC_PRESET_LSB, 0x12);
1738 ret = rc632_reg_write(h, RC632_REG_CRC_PRESET_MSB, 0xe0);
1745 static void uuid_reversecpy(unsigned char* out, unsigned char* in, int len)
1756 rc632_iso15693_transceive_ac(struct rfid_asic_handle *handle,
1757 const struct iso15693_anticol_cmd *acf,
1758 unsigned int acf_len,
1759 struct iso15693_anticol_resp *resp,
1760 unsigned int *rx_len, unsigned char *bit_of_col)
1762 u_int8_t error_flag, boc;
1765 int ret, tx_len, mask_len_bytes;
1766 unsigned int rate = ISO15693_T_SLOW;
1768 if (acf->req.flags & RFID_15693_F_RATE_HIGH)
1769 rate = ISO15693_T_FAST;
1771 DEBUGP("acf = %s\n", rfid_hexdump(acf, acf_len));
1773 ret = rc632_transceive(handle, (u_int8_t *)acf, acf_len,
1774 (u_int8_t *) resp, rx_len,
1775 iso15693_timing[rate][ISO15693_T1], 0);
1776 if (ret == -ETIMEDOUT || ret == -EIO)
1779 /* determine whether there was a collission */
1780 ret = rc632_reg_read(handle, RC632_REG_ERROR_FLAG, &error_flag);
1783 DEBUGP_ERROR_FLAG(error_flag);
1785 //FIXME: check for framing and crc errors...
1786 if (error_flag & RC632_ERR_FLAG_COL_ERR) {
1787 /* retrieve bit of collission */
1788 ret = rc632_reg_read(handle, RC632_REG_COLL_POS, &boc);
1794 if (error_flag & RC632_ERR_FLAG_CRC_ERR)
1803 mask_len_bytes = (acf->mask_len % 8) ? acf->mask_len/8+1 : acf->mask_len/8;
1805 if (acf->current_slot == 0) {
1806 /* first call: transmit Inventory frame */
1807 DEBUGP("first_frame\n");
1809 tx_len = sizeof(struct iso15693_request) + 1 + mask_len_bytes;
1811 ret = rc632_transceive(handle, (u_int8_t *)&req, tx_len,
1812 (u_int8_t *)&rx_buf, &rx_len, ISO15693_T1, 0);
1813 acf->current_slot = 1;
1814 DEBUGP("rc632_transceive ret: %d rx_len: %d\n",ret,rx_len);
1815 /* if ((ret < 0)&&(ret != -ETIMEDOUT))
1819 /* second++ call: end timeslot with EOFpulse and read */
1820 DEBUGP("second++_frame\n");
1821 if ((acf->current_slot > 16) ||
1822 ((acf->flags & RFID_15693_F5_NSLOTS_1 == 0)
1823 && (acf->current_slot > 1))) {
1825 memset(uuid, 0, ISO15693_UID_LEN);
1829 /* reset EOF-pulse-bit to 0 */
1830 ret = rc632_clear_bits(handle, RC632_REG_CODER_CONTROL,
1831 RC632_CDRCTRL_15693_EOF_PULSE);
1833 /* generate EOF pulse */
1834 ret = rc632_set_bits(handle, RC632_REG_CODER_CONTROL,
1835 RC632_CDRCTRL_15693_EOF_PULSE);
1838 // DEBUGP("waiting for EOF pulse\n");
1839 // ret = rc632_wait_idle(handle, 10); //wait for idle
1841 rx_len = sizeof(rx_buf);
1842 ret = rc632_receive(handle, (u_int8_t*)&rx_buf, &rx_len, ISO15693_T3);
1843 DEBUGP("rc632_receive ret: %d rx_len: %d\n", ret, rx_len);
1844 acf->current_slot++;
1846 /* if ((ret < 0)&&(ret != -ETIMEDOUT))
1850 rc632_reg_read(handle, RC632_REG_PRIMARY_STATUS, &tmp);
1851 DEBUGP_STATUS_FLAG(tmp);
1853 if (ret == -ETIMEDOUT) {
1854 /* no VICC answer in this timeslot*/
1855 memset(uuid, 0, ISO15693_UID_LEN);
1858 /* determine whether there was a collission */
1859 ret = rc632_reg_read(handle, RC632_REG_ERROR_FLAG, &error_flag);
1860 DEBUGP_ERROR_FLAG(error_flag);
1864 if (error_flag & RC632_ERR_FLAG_COL_ERR) {
1865 /* retrieve bit of collission */
1866 ret = rc632_reg_read(handle, RC632_REG_COLL_POS, &boc);
1870 memcpy(uuid, rx_buf.uuid, ISO15693_UID_LEN);
1871 // uuid_reversecpy(uuid, rx_buf.uuid, ISO15693_UID_LEN);
1872 DEBUGP("Collision in slot %d bit %d\n",
1873 acf->current_slot,boc);
1876 /* no collision-> retrieve uuid */
1877 DEBUGP("no collision in slot %d\n", acf->current_slot);
1878 memcpy(uuid, rx_buf.uuid, ISO15693_UID_LEN);
1879 //uuid_reversecpy(uuid, rx_buf.uuid, ISO15693_UID_LEN);
1887 struct mifare_authcmd {
1889 u_int8_t block_address;
1890 u_int32_t serno; /* lsb 1 2 msb */
1891 } __attribute__ ((packed));
1894 #define RFID_MIFARE_KEY_LEN 6
1895 #define RFID_MIFARE_KEY_CODED_LEN 12
1897 /* Transform crypto1 key from generic 6byte into rc632 specific 12byte */
1899 rc632_mifare_transform_key(const u_int8_t *key6, u_int8_t *key12)
1905 for (i = 0; i < RFID_MIFARE_KEY_LEN; i++) {
1906 ln = key6[i] & 0x0f;
1908 key12[i * 2 + 1] = (~ln << 4) | ln;
1909 key12[i * 2] = (~hn << 4) | hn;
1915 rc632_mifare_set_key(struct rfid_asic_handle *h, const u_int8_t *key)
1917 u_int8_t coded_key[RFID_MIFARE_KEY_CODED_LEN];
1921 ret = rc632_mifare_transform_key(key, coded_key);
1925 /* Terminate probably running command */
1926 ret = rc632_reg_write(h, RC632_REG_COMMAND, RC632_CMD_IDLE);
1930 ret = rc632_fifo_write(h, RFID_MIFARE_KEY_CODED_LEN, coded_key, 0x03);
1934 ret = rc632_reg_write(h, RC632_REG_COMMAND, RC632_CMD_LOAD_KEY);
1938 ret = rc632_timer_set(h, RC632_TMO_AUTH1);
1942 //ret = rc632_wait_idle(h, RC632_TMO_AUTH1);
1943 ret = rc632_wait_idle_timer(h);
1947 ret = rc632_reg_read(h, RC632_REG_ERROR_FLAG, ®);
1951 if (reg & RC632_ERR_FLAG_KEY_ERR)
1958 rc632_mifare_set_key_ee(struct rfid_asic_handle *h, unsigned int addr)
1961 u_int8_t cmd_addr[2];
1964 if (addr > 0xffff - RFID_MIFARE_KEY_CODED_LEN)
1967 cmd_addr[0] = addr & 0xff; /* LSB */
1968 cmd_addr[1] = (addr >> 8) & 0xff; /* MSB */
1970 /* Terminate probably running command */
1971 ret = rc632_reg_write(h, RC632_REG_COMMAND, RC632_CMD_IDLE);
1975 /* Write the key address to the FIFO */
1976 ret = rc632_fifo_write(h, 2, cmd_addr, 0x03);
1980 ret = rc632_reg_write(h, RC632_REG_COMMAND, RC632_CMD_LOAD_KEY_E2);
1984 ret = rc632_timer_set(h, RC632_TMO_AUTH1);
1988 //ret = rc632_wait_idle(h, RC632_TMO_AUTH1);
1989 ret = rc632_wait_idle_timer(h);
1993 ret = rc632_reg_read(h, RC632_REG_ERROR_FLAG, ®);
1997 if (reg & RC632_ERR_FLAG_KEY_ERR)
2004 rc632_mifare_auth(struct rfid_asic_handle *h, u_int8_t cmd, u_int32_t serno,
2008 struct mifare_authcmd acmd;
2011 if (cmd != RFID_CMD_MIFARE_AUTH1A && cmd != RFID_CMD_MIFARE_AUTH1B) {
2012 DEBUGP("invalid auth command\n");
2016 /* Initialize acmd */
2017 acmd.block_address = block & 0xff;
2018 acmd.auth_cmd = cmd;
2019 //acmd.serno = htonl(serno);
2024 ret = rc632_clear_bits(h, RC632_REG_CHANNEL_REDUNDANCY,
2025 RC632_CR_RX_CRC_ENABLE);
2027 /* Clear Rx CRC, Set Tx CRC and Odd Parity */
2028 ret = rc632_reg_write(h, RC632_REG_CHANNEL_REDUNDANCY,
2029 RC632_CR_TX_CRC_ENABLE | RC632_CR_PARITY_ODD |
2030 RC632_CR_PARITY_ENABLE);
2035 /* Send Authent1 Command */
2036 ret = rc632_fifo_write(h, sizeof(acmd), (unsigned char *)&acmd, 0x03);
2040 ret = rc632_reg_write(h, RC632_REG_COMMAND, RC632_CMD_AUTHENT1);
2042 DEBUGP("error during AUTHENT1");
2046 /* Wait until transmitter is idle */
2047 ret = rc632_timer_set(h, RC632_TMO_AUTH1);
2051 //ret = rc632_wait_idle(h, RC632_TMO_AUTH1);
2052 ret = rc632_wait_idle_timer(h);
2056 ret = rc632_reg_read(h, RC632_REG_SECONDARY_STATUS, ®);
2060 DEBUGP("bitframe?");
2065 ret = rc632_clear_bits(h, RC632_REG_CHANNEL_REDUNDANCY,
2066 RC632_CR_TX_CRC_ENABLE);
2070 /* Wait until transmitter is idle */
2071 ret = rc632_timer_set(h, RC632_TMO_AUTH1);
2075 /* Send Authent2 Command */
2076 ret = rc632_reg_write(h, RC632_REG_COMMAND, RC632_CMD_AUTHENT2);
2080 /* Wait until transmitter is idle */
2081 //ret = rc632_wait_idle(h, RC632_TMO_AUTH1);
2082 ret = rc632_wait_idle_timer(h);
2086 /* Check whether authentication was successful */
2087 ret = rc632_reg_read(h, RC632_REG_CONTROL, ®);
2091 if (!(reg & RC632_CONTROL_CRYPTO1_ON)) {
2092 DEBUGP("authentication not successful");
2099 /* transceive regular frame */
2101 rc632_mifare_transceive(struct rfid_asic_handle *handle,
2102 const u_int8_t *tx_buf, unsigned int tx_len,
2103 u_int8_t *rx_buf, unsigned int *rx_len,
2104 u_int64_t timeout, unsigned int flags)
2107 u_int8_t rxl = *rx_len & 0xff;
2109 DEBUGP("entered\n");
2110 memset(rx_buf, 0, *rx_len);
2113 ret = rc632_reg_write(handle, RC632_REG_CHANNEL_REDUNDANCY,
2114 (RC632_CR_PARITY_ENABLE |
2115 RC632_CR_PARITY_ODD |
2116 RC632_CR_TX_CRC_ENABLE |
2117 RC632_CR_RX_CRC_ENABLE));
2119 ret = rc632_clear_bits(handle, RC632_REG_CHANNEL_REDUNDANCY,
2120 RC632_CR_RX_CRC_ENABLE|RC632_CR_TX_CRC_ENABLE);
2125 ret = rc632_transceive(handle, tx_buf, tx_len, rx_buf, &rxl, 0x32, 0);
2136 rc632_layer2_init(struct rfid_asic_handle *h, enum rfid_layer2_id l2)
2139 case RFID_LAYER2_ISO14443A:
2140 return rc632_iso14443a_init(h);
2141 case RFID_LAYER2_ISO14443B:
2142 return rc632_iso14443b_init(h);
2143 case RFID_LAYER2_ISO15693:
2144 return rc632_iso15693_init(h);
2145 case RFID_LAYER2_ICODE1:
2146 return rc632_iso15693_icode1_init(h);
2152 const struct rfid_asic rc632 = {
2153 .name = "Philips CL RC632",
2154 .fc = ISO14443_FREQ_CARRIER,
2157 .power = &rc632_power,
2158 .rf_power = &rc632_rf_power,
2159 .transceive = &rc632_iso14443ab_transceive,
2160 .init = &rc632_layer2_init,
2162 .transceive_sf = &rc632_iso14443a_transceive_sf,
2163 .transceive_acf = &rc632_iso14443a_transceive_acf,
2164 .set_speed = &rc632_iso14443a_set_speed,
2167 .transceive_ac = &rc632_iso15693_transceive_ac,
2170 .setkey = &rc632_mifare_set_key,
2171 .setkey_ee = &rc632_mifare_set_key_ee,
2172 .auth = &rc632_mifare_auth,