1 /* Generic Philips CL RC632 Routines
3 * (C) 2005-2006 Harald Welte <laforge@gnumonks.org>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2
10 * as published by the Free Software Foundation
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
27 #include <sys/types.h>
29 #include <librfid/rfid.h>
30 #include <librfid/rfid_asic.h>
31 #include <librfid/rfid_asic_rc632.h>
32 #include <librfid/rfid_reader_cm5121.h>
33 #include <librfid/rfid_layer2_iso14443a.h>
34 #include <librfid/rfid_protocol_mifare_classic.h>
36 #include "rfid_iso14443_common.h"
38 //#include "rc632_14443a.h"
41 #define RC632_TMO_AUTH1 140
43 #define ENTER() DEBUGP("entering\n")
44 const struct rfid_asic rc632;
46 /* Register and FIFO Access functions */
48 rc632_reg_write(struct rfid_asic_handle *handle,
52 return handle->rath->rat->priv.rc632.fn.reg_write(handle->rath, reg, val);
56 rc632_reg_read(struct rfid_asic_handle *handle,
60 return handle->rath->rat->priv.rc632.fn.reg_read(handle->rath, reg, val);
64 rc632_fifo_write(struct rfid_asic_handle *handle,
69 return handle->rath->rat->priv.rc632.fn.fifo_write(handle->rath,
74 rc632_fifo_read(struct rfid_asic_handle *handle,
78 return handle->rath->rat->priv.rc632.fn.fifo_read(handle->rath, len, buf);
83 rc632_set_bits(struct rfid_asic_handle *handle,
90 ret = rc632_reg_read(handle, reg, &tmp);
94 /* if bits are already set, no need to set them again */
95 if ((tmp & val) == val)
98 return rc632_reg_write(handle, reg, (tmp|val)&0xff);
101 rc632_set_bit_mask(struct rfid_asic_handle *handle,
102 u_int8_t reg, u_int8_t mask, u_int8_t val)
107 ret = rc632_reg_read(handle, reg, &tmp);
111 /* if bits are already like we want them, abort */
112 if ((tmp & mask) == val)
115 return rc632_reg_write(handle, reg, (tmp & ~mask)|(val & mask));
119 rc632_clear_bits(struct rfid_asic_handle *handle,
126 ret = rc632_reg_read(handle, reg, &tmp);
128 DEBUGP("error during reg_read(%p, %d):%d\n",
132 /* if bits are already cleared, no need to clear them again */
133 if ((tmp & val) == 0)
136 return rc632_reg_write(handle, reg, (tmp & ~val)&0xff);
140 rc632_turn_on_rf(struct rfid_asic_handle *handle)
143 return rc632_set_bits(handle, RC632_REG_TX_CONTROL, 0x03);
147 rc632_turn_off_rf(struct rfid_asic_handle *handle)
150 return rc632_clear_bits(handle, RC632_REG_TX_CONTROL, 0x03);
154 rc632_power_up(struct rfid_asic_handle *handle)
157 return rc632_clear_bits(handle, RC632_REG_CONTROL,
158 RC632_CONTROL_POWERDOWN);
162 rc632_power_down(struct rfid_asic_handle *handle)
164 return rc632_set_bits(handle, RC632_REG_CONTROL,
165 RC632_CONTROL_POWERDOWN);
168 /* calculate best 8bit prescaler and divisor for given usec timeout */
169 static int best_prescaler(u_int64_t timeout, u_int8_t *prescaler,
172 u_int8_t best_prescaler, best_divisor, i;
173 int64_t smallest_diff;
175 smallest_diff = LLONG_MAX;
178 for (i = 0; i < 21; i++) {
179 u_int64_t clk, tmp_div, res;
181 clk = 13560000 / (1 << i);
182 tmp_div = (clk * timeout) / 1000000;
185 if ((tmp_div > 0xff) || (tmp_div > clk))
188 res = 1000000 / (clk / tmp_div);
189 diff = res - timeout;
194 if (diff < smallest_diff) {
196 best_divisor = tmp_div;
197 smallest_diff = diff;
201 *prescaler = best_prescaler;
202 *divisor = best_divisor;
204 DEBUGP("timeout %u usec, prescaler = %u, divisor = %u\n",
205 timeout, best_prescaler, best_divisor);
211 rc632_timer_set(struct rfid_asic_handle *handle,
215 u_int8_t prescaler, divisor;
217 ret = best_prescaler(timeout, &prescaler, &divisor);
219 ret = rc632_reg_write(handle, RC632_REG_TIMER_CLOCK,
224 ret = rc632_reg_write(handle, RC632_REG_TIMER_CONTROL,
225 RC632_TMR_START_TX_END|RC632_TMR_STOP_RX_BEGIN);
227 /* clear timer irq bit */
228 ret = rc632_set_bits(handle, RC632_REG_INTERRUPT_RQ, RC632_IRQ_TIMER);
230 ret |= rc632_reg_write(handle, RC632_REG_TIMER_RELOAD, divisor);
235 /* Wait until RC632 is idle or TIMER IRQ has happened */
236 static int rc632_wait_idle_timer(struct rfid_asic_handle *handle)
242 rc632_reg_read(handle, RC632_REG_PRIMARY_STATUS, &irq);
243 rc632_reg_read(handle, RC632_REG_ERROR_FLAG, &irq);
244 ret = rc632_reg_read(handle, RC632_REG_INTERRUPT_RQ, &irq);
248 /* FIXME: currently we're lazy: If we actually received
249 * something even after the timer expired, we accept it */
250 if (irq & RC632_IRQ_TIMER && !(irq & RC632_IRQ_RX)) {
252 rc632_reg_read(handle, RC632_REG_PRIMARY_STATUS, &foo);
254 rc632_reg_read(handle, RC632_REG_ERROR_FLAG, &foo);
259 ret = rc632_reg_read(handle, RC632_REG_COMMAND, &cmd);
266 /* poll every millisecond */
271 /* Stupid RC632 implementations don't evaluate interrupts but poll the
272 * command register for "status idle" */
274 rc632_wait_idle(struct rfid_asic_handle *handle, u_int64_t timeout)
278 #define USLEEP_PER_CYCLE 128
281 ret = rc632_reg_read(handle, RC632_REG_COMMAND, &cmd);
286 /* FIXME: read second time ?? */
292 rc632_reg_read(handle, RC632_REG_PRIMARY_STATUS, &foo);
294 rc632_reg_read(handle, RC632_REG_ERROR_FLAG, &foo);
297 /* Abort after some timeout */
298 if (cycles > timeout*100/USLEEP_PER_CYCLE) {
303 usleep(USLEEP_PER_CYCLE);
310 rc632_transmit(struct rfid_asic_handle *handle,
316 const u_int8_t *cur_buf = buf;
324 ret = rc632_fifo_write(handle, cur_len, cur_buf, 0x03);
328 if (cur_buf == buf) {
329 /* only start transmit first time */
330 ret = rc632_reg_write(handle, RC632_REG_COMMAND,
337 if (cur_buf < buf + len) {
338 cur_len = buf - cur_buf;
346 return rc632_wait_idle(handle, timeout);
350 tcl_toggle_pcb(struct rfid_asic_handle *handle)
352 // FIXME: toggle something between 0x0a and 0x0b
357 rc632_transceive(struct rfid_asic_handle *handle,
358 const u_int8_t *tx_buf,
367 const u_int8_t *cur_tx_buf = tx_buf;
369 DEBUGP("timer = %u\n", timer);
376 ret = rc632_timer_set(handle, timer*10);
380 ret = rc632_reg_write(handle, RC632_REG_COMMAND, 0x00);
381 /* clear all interrupts */
382 ret = rc632_reg_write(handle, RC632_REG_INTERRUPT_RQ, 0x7f);
385 ret = rc632_fifo_write(handle, cur_tx_len, cur_tx_buf, 0x03);
389 if (cur_tx_buf == tx_buf) {
390 ret = rc632_reg_write(handle, RC632_REG_COMMAND,
391 RC632_CMD_TRANSCEIVE);
396 cur_tx_buf += cur_tx_len;
397 if (cur_tx_buf < tx_buf + tx_len) {
399 ret = rc632_reg_read(handle, RC632_REG_FIFO_LENGTH,
404 cur_tx_len = 64 - fifo_fill;
405 //printf("refilling tx fifo with %u bytes\n", cur_tx_len);
409 } while (cur_tx_len);
412 tcl_toggle_pcb(handle);
414 //ret = rc632_wait_idle_timer(handle);
415 ret = rc632_wait_idle(handle, timer);
419 ret = rc632_reg_read(handle, RC632_REG_FIFO_LENGTH, &rx_avail);
423 if (rx_avail > *rx_len) {
424 //printf("rx_avail(%d) > rx_len(%d), JFYI\n", rx_avail, *rx_len);
425 } else if (*rx_len > rx_avail)
431 DEBUGP("rx_len == 0\n");
433 rc632_reg_read(handle, RC632_REG_ERROR_FLAG, &tmp);
434 rc632_reg_read(handle, RC632_REG_CHANNEL_REDUNDANCY, &tmp);
439 return rc632_fifo_read(handle, *rx_len, rx_buf);
440 /* FIXME: discard addidional bytes in FIFO */
444 rc632_read_eeprom(struct rfid_asic_handle *handle)
446 u_int8_t recvbuf[60];
454 ret = rc632_fifo_write(handle, 3, sndbuf, 0x03);
458 ret = rc632_reg_write(handle, RC632_REG_COMMAND, RC632_CMD_READ_E2);
464 ret = rc632_fifo_read(handle, sizeof(recvbuf), recvbuf);
468 // FIXME: do something with eeprom contents
473 rc632_calc_crc16_from(struct rfid_asic_handle *handle)
475 u_int8_t sndbuf[2] = { 0x01, 0x02 };
476 u_int8_t crc_lsb = 0x00 , crc_msb = 0x00;
479 ret = rc632_reg_write(handle, RC632_REG_CRC_PRESET_LSB, 0x12);
483 ret = rc632_reg_write(handle, RC632_REG_CRC_PRESET_MSB, 0xe0);
487 ret = rc632_fifo_write(handle, sizeof(sndbuf), sndbuf, 3);
491 ret = rc632_reg_write(handle, RC632_REG_COMMAND, RC632_CMD_CALC_CRC);
495 usleep(10000); // FIXME: no checking for cmd completion?
497 ret = rc632_reg_read(handle, RC632_REG_CRC_RESULT_LSB, &crc_lsb);
501 ret = rc632_reg_read(handle, RC632_REG_CRC_RESULT_MSB, &crc_msb);
505 // FIXME: what to do with crc result?
511 rc632_register_dump(struct rfid_asic_handle *handle, u_int8_t *buf)
516 for (i = 0; i <= 0x3f; i++) {
517 ret = rc632_reg_read(handle, i, &buf[i]);
518 // do we want error checks?
525 /* generic FIFO access functions (if no more efficient ones provided by
526 * transport driver) */
531 // FIXME: implementation (not needed for CM 5121)
538 // FIXME: implementation (not neded for CM 5121)
543 rc632_init(struct rfid_asic_handle *ah)
547 /* switch off rf (make sure PICCs are reset at init time) */
548 ret = rc632_power_down(ah);
555 ret = rc632_power_up(ah);
559 /* disable register paging */
560 ret = rc632_reg_write(ah, 0x00, 0x00);
564 /* set some sane default values */
565 ret = rc632_reg_write(ah, 0x11, 0x5b);
570 ret = rc632_turn_off_rf(ah);
577 ret = rc632_turn_on_rf(ah);
585 rc632_fini(struct rfid_asic_handle *ah)
590 ret = rc632_turn_off_rf(ah);
594 ret = rc632_power_down(ah);
601 struct rfid_asic_handle *
602 rc632_open(struct rfid_asic_transport_handle *th)
604 struct rfid_asic_handle *h;
606 h = malloc_asic_handle(sizeof(*h));
609 memset(h, 0, sizeof(*h));
614 /* FIXME: this is only cm5121 specific, since the latency
615 * down to the RC632 FIFO is too long to refill during TX/RX */
616 h->mtu = h->mru = 64;
618 if (rc632_init(h) < 0) {
627 rc632_close(struct rfid_asic_handle *h)
635 * Philips CL RC632 primitives for ISO 14443-A compliant PICC's
637 * (C) 2005-2006 by Harald Welte <laforge@gnumonks.org>
642 rc632_iso14443a_init(struct rfid_asic_handle *handle)
646 // FIXME: some fifo work (drain fifo?)
648 /* flush fifo (our way) */
649 ret = rc632_reg_write(handle, RC632_REG_CONTROL,
650 RC632_CONTROL_FIFO_FLUSH);
652 ret = rc632_reg_write(handle, RC632_REG_TX_CONTROL,
653 (RC632_TXCTRL_TX1_RF_EN |
654 RC632_TXCTRL_TX2_RF_EN |
655 RC632_TXCTRL_TX2_INV |
656 RC632_TXCTRL_FORCE_100_ASK |
657 RC632_TXCTRL_MOD_SRC_INT));
661 ret = rc632_reg_write(handle, RC632_REG_CW_CONDUCTANCE,
662 CM5121_CW_CONDUCTANCE);
666 /* Since FORCE_100_ASK is set (cf mc073930.pdf), this line may be left out? */
667 ret = rc632_reg_write(handle, RC632_REG_MOD_CONDUCTANCE,
668 CM5121_MOD_CONDUCTANCE);
672 ret = rc632_reg_write(handle, RC632_REG_CODER_CONTROL,
673 (RC632_CDRCTRL_TXCD_14443A |
674 RC632_CDRCTRL_RATE_106K));
678 ret = rc632_reg_write(handle, RC632_REG_MOD_WIDTH, 0x13);
682 ret = rc632_reg_write(handle, RC632_REG_MOD_WIDTH_SOF, 0x3f);
686 ret = rc632_reg_write(handle, RC632_REG_TYPE_B_FRAMING, 0x00);
690 ret = rc632_reg_write(handle, RC632_REG_RX_CONTROL1,
691 (RC632_RXCTRL1_GAIN_35DB |
692 RC632_RXCTRL1_ISO14443 |
693 RC632_RXCTRL1_SUBCP_8));
697 ret = rc632_reg_write(handle, RC632_REG_DECODER_CONTROL,
698 (RC632_DECCTRL_MANCHESTER |
699 RC632_DECCTRL_RXFR_14443A));
703 ret = rc632_reg_write(handle, RC632_REG_BIT_PHASE,
704 CM5121_14443A_BITPHASE);
708 ret = rc632_reg_write(handle, RC632_REG_RX_THRESHOLD,
709 CM5121_14443A_THRESHOLD);
713 ret = rc632_reg_write(handle, RC632_REG_BPSK_DEM_CONTROL, 0x00);
717 ret = rc632_reg_write(handle, RC632_REG_RX_CONTROL2,
718 (RC632_RXCTRL2_DECSRC_INT |
719 RC632_RXCTRL2_CLK_Q));
723 /* Omnikey proprietary driver has 0x03, but 0x06 is the default reset value ?!? */
724 ret = rc632_reg_write(handle, RC632_REG_RX_WAIT, 0x06);
728 ret = rc632_reg_write(handle, RC632_REG_CHANNEL_REDUNDANCY,
729 (RC632_CR_PARITY_ENABLE |
730 RC632_CR_PARITY_ODD));
734 ret = rc632_reg_write(handle, RC632_REG_CRC_PRESET_LSB, 0x63);
738 ret = rc632_reg_write(handle, RC632_REG_CRC_PRESET_MSB, 0x63);
746 rc632_iso14443a_fini(struct iso14443a_handle *handle_14443)
750 ret = rc632_turn_off_rf(handle);
760 /* issue a 14443-3 A PCD -> PICC command in a short frame, such as REQA, WUPA */
762 rc632_iso14443a_transceive_sf(struct rfid_asic_handle *handle,
764 struct iso14443a_atqa *atqa)
770 memset(atqa, 0, sizeof(*atqa));
774 /* transfer only 7 bits of last byte in frame */
775 ret = rc632_reg_write(handle, RC632_REG_BIT_FRAMING, 0x07);
779 ret = rc632_clear_bits(handle, RC632_REG_CONTROL,
780 RC632_CONTROL_CRYPTO1_ON);
785 ret = rc632_reg_write(handle, RC632_REG_CHANNEL_REDUNDANCY,
786 (RC632_CR_PARITY_ENABLE |
787 RC632_CR_PARITY_ODD));
789 ret = rc632_clear_bits(handle, RC632_REG_CHANNEL_REDUNDANCY,
790 RC632_CR_RX_CRC_ENABLE|RC632_CR_TX_CRC_ENABLE);
796 ret = rc632_transceive(handle, tx_buf, sizeof(tx_buf),
797 (u_int8_t *)atqa, &rx_len,
798 ISO14443A_FDT_ANTICOL_LAST1, 0);
800 DEBUGP("error during rc632_transceive()\n");
804 /* switch back to normal 8bit last byte */
805 ret = rc632_reg_write(handle, RC632_REG_BIT_FRAMING, 0x00);
810 DEBUGP("rx_len(%d) != 2\n", rx_len);
817 /* transceive regular frame */
819 rc632_iso14443ab_transceive(struct rfid_asic_handle *handle,
820 unsigned int frametype,
821 const u_int8_t *tx_buf, unsigned int tx_len,
822 u_int8_t *rx_buf, unsigned int *rx_len,
823 u_int64_t timeout, unsigned int flags)
827 u_int8_t channel_red;
834 memset(rx_buf, 0, *rx_len);
837 case RFID_14443A_FRAME_REGULAR:
838 case RFID_MIFARE_FRAME:
839 channel_red = RC632_CR_RX_CRC_ENABLE|RC632_CR_TX_CRC_ENABLE
840 |RC632_CR_PARITY_ENABLE|RC632_CR_PARITY_ODD;
842 case RFID_14443B_FRAME_REGULAR:
843 channel_red = RC632_CR_RX_CRC_ENABLE|RC632_CR_TX_CRC_ENABLE
847 case RFID_MIFARE_FRAME:
848 channel_red = RC632_CR_PARITY_ENABLE|RC632_CR_PARITY_ODD;
855 ret = rc632_reg_write(handle, RC632_REG_CHANNEL_REDUNDANCY,
860 ret = rc632_transceive(handle, tx_buf, tx_len, rx_buf, &rxl, timeout, 0);
869 /* transceive anti collission bitframe */
871 rc632_iso14443a_transceive_acf(struct rfid_asic_handle *handle,
872 struct iso14443a_anticol_cmd *acf,
873 unsigned int *bit_of_col)
877 u_int8_t rx_len = sizeof(rx_buf);
878 u_int8_t rx_align = 0, tx_last_bits, tx_bytes, tx_bytes_total;
881 *bit_of_col = ISO14443A_BITOFCOL_NONE;
882 memset(rx_buf, 0, sizeof(rx_buf));
884 /* disable mifare cryto */
885 ret = rc632_clear_bits(handle, RC632_REG_CONTROL,
886 RC632_CONTROL_CRYPTO1_ON);
890 /* disable CRC summing */
892 ret = rc632_reg_write(handle, RC632_REG_CHANNEL_REDUNDANCY,
893 (RC632_CR_PARITY_ENABLE |
894 RC632_CR_PARITY_ODD));
896 ret = rc632_clear_bits(handle, RC632_REG_CHANNEL_REDUNDANCY,
897 RC632_CR_TX_CRC_ENABLE|RC632_CR_TX_CRC_ENABLE);
902 tx_last_bits = acf->nvb & 0x07; /* lower nibble indicates bits */
903 tx_bytes = ( acf->nvb >> 4 ) & 0x07;
905 tx_bytes_total = tx_bytes+1;
906 rx_align = tx_last_bits & 0x07; /* rx frame complements tx */
909 tx_bytes_total = tx_bytes;
911 /* set RxAlign and TxLastBits*/
912 ret = rc632_reg_write(handle, RC632_REG_BIT_FRAMING,
913 (rx_align << 4) | (tx_last_bits));
917 ret = rc632_transceive(handle, (u_int8_t *)acf, tx_bytes_total,
918 rx_buf, &rx_len, 0x32, 0);
922 /* bitwise-OR the two halves of the split byte */
923 acf->uid_bits[tx_bytes-2] = (
924 (acf->uid_bits[tx_bytes-2] & (0xff >> (8-tx_last_bits)))
929 memcpy(&acf->uid_bits[tx_bytes-1], &rx_buf[1], rx_len-1);
931 /* determine whether there was a collission */
932 ret = rc632_reg_read(handle, RC632_REG_ERROR_FLAG, &error_flag);
936 if (error_flag & RC632_ERR_FLAG_COL_ERR) {
937 /* retrieve bit of collission */
938 ret = rc632_reg_read(handle, RC632_REG_COLL_POS, &boc);
942 /* bit of collission relative to start of part 1 of
943 * anticollision frame (!) */
944 *bit_of_col = 2*8 + boc;
951 RC632_RATE_106 = 0x00,
952 RC632_RATE_212 = 0x01,
953 RC632_RATE_424 = 0x02,
954 RC632_RATE_848 = 0x03,
958 u_int8_t subc_pulses;
960 u_int8_t rx_threshold;
961 u_int8_t bpsk_dem_ctrl;
969 static struct rx_config rx_configs[] = {
971 .subc_pulses = RC632_RXCTRL1_SUBCP_8,
972 .rx_coding = RC632_DECCTRL_MANCHESTER,
973 .rx_threshold = 0x88,
974 .bpsk_dem_ctrl = 0x00,
977 .subc_pulses = RC632_RXCTRL1_SUBCP_4,
978 .rx_coding = RC632_DECCTRL_BPSK,
979 .rx_threshold = 0x50,
980 .bpsk_dem_ctrl = 0x0c,
983 .subc_pulses = RC632_RXCTRL1_SUBCP_2,
984 .rx_coding = RC632_DECCTRL_BPSK,
985 .rx_threshold = 0x50,
986 .bpsk_dem_ctrl = 0x0c,
989 .subc_pulses = RC632_RXCTRL1_SUBCP_1,
990 .rx_coding = RC632_DECCTRL_BPSK,
991 .rx_threshold = 0x50,
992 .bpsk_dem_ctrl = 0x0c,
996 static struct tx_config tx_configs[] = {
998 .rate = RC632_CDRCTRL_RATE_106K,
1002 .rate = RC632_CDRCTRL_RATE_212K,
1006 .rate = RC632_CDRCTRL_RATE_424K,
1010 .rate = RC632_CDRCTRL_RATE_848K,
1015 static int rc632_iso14443a_set_speed(struct rfid_asic_handle *handle,
1016 unsigned int tx, unsigned int rate)
1024 if (rate > ARRAY_SIZE(rx_configs))
1027 rc = rc632_set_bit_mask(handle, RC632_REG_RX_CONTROL1,
1028 RC632_RXCTRL1_SUBCP_MASK,
1029 rx_configs[rate].subc_pulses);
1033 rc = rc632_set_bit_mask(handle, RC632_REG_DECODER_CONTROL,
1035 rx_configs[rate].rx_coding);
1039 rc = rc632_reg_write(handle, RC632_REG_RX_THRESHOLD,
1040 rx_configs[rate].rx_threshold);
1044 if (rx_configs[rate].rx_coding == RC632_DECCTRL_BPSK) {
1045 rc = rc632_reg_write(handle,
1046 RC632_REG_BPSK_DEM_CONTROL,
1047 rx_configs[rate].bpsk_dem_ctrl);
1053 if (rate > ARRAY_SIZE(tx_configs))
1056 rc = rc632_set_bit_mask(handle, RC632_REG_CODER_CONTROL,
1057 RC632_CDRCTRL_RATE_MASK,
1058 tx_configs[rate].rate);
1062 rc = rc632_reg_write(handle, RC632_REG_MOD_WIDTH,
1063 tx_configs[rate].mod_width);
1071 static int rc632_iso14443b_init(struct rfid_asic_handle *handle)
1075 // FIXME: some FIFO work
1077 /* flush fifo (our way) */
1078 ret = rc632_reg_write(handle, RC632_REG_CONTROL,
1079 RC632_CONTROL_FIFO_FLUSH);
1083 ret = rc632_reg_write(handle, RC632_REG_TX_CONTROL,
1084 (RC632_TXCTRL_TX1_RF_EN |
1085 RC632_TXCTRL_TX2_RF_EN |
1086 RC632_TXCTRL_TX2_INV |
1087 RC632_TXCTRL_MOD_SRC_INT));
1091 ret = rc632_reg_write(handle, RC632_REG_CW_CONDUCTANCE, 0x3f);
1095 ret = rc632_reg_write(handle, RC632_REG_MOD_CONDUCTANCE, 0x04);
1099 ret = rc632_reg_write(handle, RC632_REG_CODER_CONTROL,
1100 (RC632_CDRCTRL_TXCD_NRZ |
1101 RC632_CDRCTRL_RATE_14443B));
1105 ret = rc632_reg_write(handle, RC632_REG_MOD_WIDTH, 0x13);
1109 ret = rc632_reg_write(handle, RC632_REG_MOD_WIDTH_SOF, 0x3f);
1113 ret = rc632_reg_write(handle, RC632_REG_TYPE_B_FRAMING,
1114 (RC632_TBFRAMING_SOF_11L_3H |
1115 (6 << RC632_TBFRAMING_SPACE_SHIFT) |
1116 RC632_TBFRAMING_EOF_11));
1120 ret = rc632_reg_write(handle, RC632_REG_RX_CONTROL1,
1121 (RC632_RXCTRL1_GAIN_35DB |
1122 RC632_RXCTRL1_ISO14443 |
1123 RC632_RXCTRL1_SUBCP_8));
1127 ret = rc632_reg_write(handle, RC632_REG_DECODER_CONTROL,
1128 (RC632_DECCTRL_BPSK |
1129 RC632_DECCTRL_RXFR_14443B));
1133 ret = rc632_reg_write(handle, RC632_REG_BIT_PHASE,
1134 CM5121_14443B_BITPHASE);
1138 ret = rc632_reg_write(handle, RC632_REG_RX_THRESHOLD,
1139 CM5121_14443B_THRESHOLD);
1143 ret = rc632_reg_write(handle, RC632_REG_BPSK_DEM_CONTROL,
1144 ((0x2 & RC632_BPSKD_TAUB_MASK)<<RC632_BPSKD_TAUB_SHIFT |
1145 (0x3 & RC632_BPSKD_TAUD_MASK)<<RC632_BPSKD_TAUD_SHIFT |
1146 RC632_BPSKD_FILTER_AMP_DETECT |
1147 RC632_BPSKD_NO_RX_EOF |
1148 RC632_BPSKD_NO_RX_EGT));
1152 ret = rc632_reg_write(handle, RC632_REG_RX_CONTROL2,
1153 (RC632_RXCTRL2_AUTO_PD |
1154 RC632_RXCTRL2_DECSRC_INT));
1158 ret = rc632_reg_write(handle, RC632_REG_RX_WAIT, 0x03);
1162 ret = rc632_reg_write(handle, RC632_REG_CHANNEL_REDUNDANCY,
1163 (RC632_CR_TX_CRC_ENABLE |
1164 RC632_CR_RX_CRC_ENABLE |
1169 ret = rc632_reg_write(handle, RC632_REG_CRC_PRESET_LSB, 0xff);
1173 ret = rc632_reg_write(handle, RC632_REG_CRC_PRESET_MSB, 0xff);
1181 rc632_iso15693_init(struct rfid_asic_handle *h)
1185 ret = rc632_reg_write(h, RC632_REG_TX_CONTROL,
1186 (RC632_TXCTRL_MOD_SRC_INT |
1187 RC632_TXCTRL_TX2_INV |
1188 RC632_TXCTRL_TX2_RF_EN |
1189 RC632_TXCTRL_TX1_RF_EN));
1193 ret = rc632_reg_write(h, RC632_REG_CW_CONDUCTANCE, 0x3f);
1197 ret = rc632_reg_write(h, RC632_REG_MOD_CONDUCTANCE, 0x03);
1201 ret = rc632_reg_write(h, RC632_REG_CODER_CONTROL,
1202 (RC632_CDRCTRL_RATE_15693 |
1207 ret = rc632_reg_write(h, RC632_REG_MOD_WIDTH, 0x3f);
1211 ret = rc632_reg_write(h, RC632_REG_MOD_WIDTH_SOF, 0x3f);
1215 ret = rc632_reg_write(h, RC632_REG_TYPE_B_FRAMING, 0x00);
1219 ret = rc632_reg_write(h, RC632_REG_RX_CONTROL1,
1220 (RC632_RXCTRL1_SUBCP_16 |
1221 RC632_RXCTRL1_ISO15693 |
1222 RC632_RXCTRL1_GAIN_35DB));
1226 ret = rc632_reg_write(h, RC632_REG_DECODER_CONTROL,
1227 (RC632_DECCTRL_RXFR_15693 |
1228 RC632_DECCTRL_RX_INVERT));
1232 ret = rc632_reg_write(h, RC632_REG_BIT_PHASE, 0xe0);
1236 ret = rc632_reg_write(h, RC632_REG_RX_THRESHOLD, 0xff);
1240 ret = rc632_reg_write(h, RC632_REG_BPSK_DEM_CONTROL, 0x00);
1244 ret = rc632_reg_write(h, RC632_REG_RX_CONTROL2,
1245 (RC632_RXCTRL2_AUTO_PD |
1246 RC632_RXCTRL2_DECSRC_INT));
1250 ret = rc632_reg_write(h, RC632_REG_CHANNEL_REDUNDANCY,
1252 RC632_CR_RX_CRC_ENABLE |
1253 RC632_CR_TX_CRC_ENABLE));
1257 ret = rc632_reg_write(h, RC632_REG_CRC_PRESET_LSB, 0xff);
1261 ret = rc632_reg_write(h, RC632_REG_CRC_PRESET_MSB, 0xff);
1269 rc632_iso15693_icode_init(struct rfid_asic_handle *h)
1273 ret = rc632_reg_write(h, RC632_REG_TX_CONTROL,
1274 (RC632_TXCTRL_MOD_SRC_INT |
1275 RC632_TXCTRL_TX2_INV |
1276 RC632_TXCTRL_TX2_RF_EN |
1277 RC632_TXCTRL_TX1_RF_EN));
1281 ret = rc632_reg_write(h, RC632_REG_CW_CONDUCTANCE, 0x3f);
1285 ret = rc632_reg_write(h, RC632_REG_MOD_CONDUCTANCE, 0x02);
1289 ret = rc632_reg_write(h, RC632_REG_CODER_CONTROL, 0x2c);
1293 ret = rc632_reg_write(h, RC632_REG_MOD_WIDTH, 0x3f);
1297 ret = rc632_reg_write(h, RC632_REG_MOD_WIDTH_SOF, 0x3f);
1301 ret = rc632_reg_write(h, RC632_REG_MOD_WIDTH_SOF, 0x3f);
1305 ret = rc632_reg_write(h, RC632_REG_TYPE_B_FRAMING, 0x00);
1309 ret = rc632_reg_write(h, RC632_REG_RX_CONTROL1, 0x8b); /* FIXME */
1313 ret = rc632_reg_write(h, RC632_REG_DECODER_CONTROL, 0x00);
1317 ret = rc632_reg_write(h, RC632_REG_BIT_PHASE, 0x52);
1321 ret = rc632_reg_write(h, RC632_REG_RX_THRESHOLD, 0x66);
1325 ret = rc632_reg_write(h, RC632_REG_BPSK_DEM_CONTROL, 0x00);
1329 ret = rc632_reg_write(h, RC632_REG_RX_CONTROL2,
1330 RC632_RXCTRL2_DECSRC_INT);
1334 ret = rc632_reg_write(h, RC632_REG_CHANNEL_REDUNDANCY,
1335 (RC632_CR_RX_CRC_ENABLE |
1336 RC632_CR_TX_CRC_ENABLE));
1337 ret = rc632_reg_write(h, RC632_REG_CRC_PRESET_LSB, 0xfe);
1341 ret = rc632_reg_write(h, RC632_REG_CRC_PRESET_MSB, 0xff);
1349 rc632_iso15693_icl_init(struct rfid_asic_handle *h)
1355 ret = rc632_reg_write(h, RC632_REG_TX_CONTROL,
1356 (RC632_TXCTRL_MOD_SRC_INT |
1357 RC632_TXCTRL_TX2_INV |
1358 RC632_TXCTRL_TX2_RF_EN |
1359 RC632_TXCTRL_TX1_RF_EN));
1363 ret = rc632_reg_write(h, RC632_REG_CW_CONDUCTANCE, 0x3f);
1367 ret = rc632_reg_write(h, RC632_REG_MOD_CONDUCTANCE, 0x11);
1371 ret = rc632_reg_write(h, RC632_REG_CODER_CONTROL,
1372 (RC632_CDRCTRL_RATE_15693 |
1373 RC632_CDRCTRL_TXCD_ICODE_STD |
1378 ret = rc632_reg_write(h, RC632_REG_MOD_WIDTH, 0x3f);
1382 ret = rc632_reg_write(h, RC632_REG_MOD_WIDTH_SOF, 0x3f);
1385 ret = rc632_reg_write(h, RC632_REG_RX_CONTROL1,
1386 (RC632_RXCTRL1_SUBCP_16|
1387 RC632_RXCTRL1_ISO15693|
1388 RC632_RXCTRL1_GAIN_35DB));
1391 ret = rc632_reg_write(h, RC632_REG_DECODER_CONTROL,
1392 (RC632_DECCTRL_RX_INVERT|
1393 RC632_DECCTRL_RXFR_15693));
1397 ret = rc632_reg_write(h, RC632_REG_BIT_PHASE, 0xbd);
1401 ret = rc632_reg_write(h, RC632_REG_RX_THRESHOLD, 0xff);
1405 ret = rc632_reg_write(h, RC632_REG_BPSK_DEM_CONTROL, 0x00);
1409 ret = rc632_reg_write(h, RC632_REG_RX_CONTROL2,
1410 RC632_RXCTRL2_DECSRC_INT);
1414 ret = rc632_reg_write(h, RC632_REG_CHANNEL_REDUNDANCY, 0x00);
1418 ret = rc632_reg_write(h, RC632_REG_CRC_PRESET_LSB, 0x12);
1422 ret = rc632_reg_write(h, RC632_REG_CRC_PRESET_MSB, 0xe0);
1429 struct mifare_authcmd {
1431 u_int8_t block_address;
1432 u_int32_t serno; /* lsb 1 2 msb */
1433 } __attribute__ ((packed));
1436 #define RFID_MIFARE_KEY_LEN 6
1437 #define RFID_MIFARE_KEY_CODED_LEN 12
1439 /* Transform crypto1 key from generic 6byte into rc632 specific 12byte */
1441 rc632_mifare_transform_key(const u_int8_t *key6, u_int8_t *key12)
1447 for (i = 0; i < RFID_MIFARE_KEY_LEN; i++) {
1448 ln = key6[i] & 0x0f;
1450 key12[i * 2 + 1] = (~ln << 4) | ln;
1451 key12[i * 2] = (~hn << 4) | hn;
1457 rc632_mifare_set_key(struct rfid_asic_handle *h, const u_int8_t *key)
1459 u_int8_t coded_key[RFID_MIFARE_KEY_CODED_LEN];
1463 ret = rc632_mifare_transform_key(key, coded_key);
1467 /* Terminate probably running command */
1468 ret = rc632_reg_write(h, RC632_REG_COMMAND, RC632_CMD_IDLE);
1472 ret = rc632_fifo_write(h, RFID_MIFARE_KEY_CODED_LEN, coded_key, 0x03);
1476 ret = rc632_reg_write(h, RC632_REG_COMMAND, RC632_CMD_LOAD_KEY);
1480 ret = rc632_wait_idle(h, RC632_TMO_AUTH1);
1484 ret = rc632_reg_read(h, RC632_REG_ERROR_FLAG, ®);
1488 if (reg & RC632_ERR_FLAG_KEY_ERR)
1495 rc632_mifare_auth(struct rfid_asic_handle *h, u_int8_t cmd, u_int32_t serno,
1499 struct mifare_authcmd acmd;
1502 if (cmd != RFID_CMD_MIFARE_AUTH1A && cmd != RFID_CMD_MIFARE_AUTH1B) {
1503 DEBUGP("invalid auth command\n");
1507 /* Initialize acmd */
1508 acmd.block_address = block & 0xff;
1509 acmd.auth_cmd = cmd;
1510 //acmd.serno = htonl(serno);
1515 ret = rc632_clear_bits(h, RC632_REG_CHANNEL_REDUNDANCY,
1516 RC632_CR_RX_CRC_ENABLE);
1518 /* Clear Rx CRC, Set Tx CRC and Odd Parity */
1519 ret = rc632_reg_write(h, RC632_REG_CHANNEL_REDUNDANCY,
1520 RC632_CR_TX_CRC_ENABLE | RC632_CR_PARITY_ODD |
1521 RC632_CR_PARITY_ENABLE);
1526 /* Send Authent1 Command */
1527 ret = rc632_fifo_write(h, sizeof(acmd), (unsigned char *)&acmd, 0x03);
1531 ret = rc632_reg_write(h, RC632_REG_COMMAND, RC632_CMD_AUTHENT1);
1533 DEBUGP("error during AUTHENT1");
1537 /* Wait until transmitter is idle */
1538 ret = rc632_wait_idle(h, RC632_TMO_AUTH1);
1542 ret = rc632_reg_read(h, RC632_REG_SECONDARY_STATUS, ®);
1546 DEBUGP("bitframe?");
1551 ret = rc632_clear_bits(h, RC632_REG_CHANNEL_REDUNDANCY,
1552 RC632_CR_TX_CRC_ENABLE);
1556 /* Send Authent2 Command */
1557 ret = rc632_reg_write(h, RC632_REG_COMMAND, RC632_CMD_AUTHENT2);
1561 /* Wait until transmitter is idle */
1562 ret = rc632_wait_idle(h, RC632_TMO_AUTH1);
1566 /* Check whether authentication was successful */
1567 ret = rc632_reg_read(h, RC632_REG_CONTROL, ®);
1571 if (!(reg & RC632_CONTROL_CRYPTO1_ON)) {
1572 DEBUGP("authentication not successful");
1579 /* transceive regular frame */
1581 rc632_mifare_transceive(struct rfid_asic_handle *handle,
1582 const u_int8_t *tx_buf, unsigned int tx_len,
1583 u_int8_t *rx_buf, unsigned int *rx_len,
1584 u_int64_t timeout, unsigned int flags)
1587 u_int8_t rxl = *rx_len & 0xff;
1589 DEBUGP("entered\n");
1590 memset(rx_buf, 0, *rx_len);
1593 ret = rc632_reg_write(handle, RC632_REG_CHANNEL_REDUNDANCY,
1594 (RC632_CR_PARITY_ENABLE |
1595 RC632_CR_PARITY_ODD |
1596 RC632_CR_TX_CRC_ENABLE |
1597 RC632_CR_RX_CRC_ENABLE));
1599 ret = rc632_clear_bits(handle, RC632_REG_CHANNEL_REDUNDANCY,
1600 RC632_CR_RX_CRC_ENABLE|RC632_CR_TX_CRC_ENABLE);
1605 ret = rc632_transceive(handle, tx_buf, tx_len, rx_buf, &rxl, 0x32, 0);
1614 const struct rfid_asic rc632 = {
1615 .name = "Philips CL RC632",
1616 .fc = ISO14443_FREQ_CARRIER,
1619 .power_up = &rc632_power_up,
1620 .power_down = &rc632_power_down,
1621 .turn_on_rf = &rc632_turn_on_rf,
1622 .turn_off_rf = &rc632_turn_off_rf,
1623 .transceive = &rc632_iso14443ab_transceive,
1625 .init = &rc632_iso14443a_init,
1626 .transceive_sf = &rc632_iso14443a_transceive_sf,
1627 .transceive_acf = &rc632_iso14443a_transceive_acf,
1628 .set_speed = &rc632_iso14443a_set_speed,
1631 .init = &rc632_iso14443b_init,
1634 .init = &rc632_iso15693_init,
1637 .setkey = &rc632_mifare_set_key,
1638 .auth = &rc632_mifare_auth,