git.rot13.org Git - linux/blob - arch/arm/mach-tegra/cpuidle-tegra20.c

   1 /*
   2  * CPU idle driver for Tegra CPUs
   3  *
   4  * Copyright (c) 2010-2012, NVIDIA Corporation.
   5  * Copyright (c) 2011 Google, Inc.
   6  * Author: Colin Cross <ccross@android.com>
   7  *         Gary King <gking@nvidia.com>
   8  *
   9  * Rework for 3.3 by Peter De Schrijver <pdeschrijver@nvidia.com>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful, but WITHOUT
  17  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19  * more details.
  20  */
  21
  22 #include <linux/clk/tegra.h>
  23 #include <linux/tick.h>
  24 #include <linux/cpuidle.h>
  25 #include <linux/cpu_pm.h>
  26 #include <linux/kernel.h>
  27 #include <linux/module.h>
  28
  29 #include <soc/tegra/flowctrl.h>
  30
  31 #include <asm/cpuidle.h>
  32 #include <asm/smp_plat.h>
  33 #include <asm/suspend.h>
  34
  35 #include "cpuidle.h"
  36 #include "iomap.h"
  37 #include "irq.h"
  38 #include "pm.h"
  39 #include "reset.h"
  40 #include "sleep.h"
  41
  42 #ifdef CONFIG_PM_SLEEP
  43 static bool abort_flag;
  44 static atomic_t abort_barrier;
  45 static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev,
  46                                     struct cpuidle_driver *drv,
  47                                     int index);
  48 #define TEGRA20_MAX_STATES 2
  49 #else
  50 #define TEGRA20_MAX_STATES 1
  51 #endif
  52
  53 static struct cpuidle_driver tegra_idle_driver = {
  54         .name = "tegra_idle",
  55         .owner = THIS_MODULE,
  56         .states = {
  57                 ARM_CPUIDLE_WFI_STATE_PWR(600),
  58 #ifdef CONFIG_PM_SLEEP
  59                 {
  60                         .enter            = tegra20_idle_lp2_coupled,
  61                         .exit_latency     = 5000,
  62                         .target_residency = 10000,
  63                         .power_usage      = 0,
  64                         .flags            = CPUIDLE_FLAG_COUPLED |
  65                                             CPUIDLE_FLAG_TIMER_STOP,
  66                         .name             = "powered-down",
  67                         .desc             = "CPU power gated",
  68                 },
  69 #endif
  70         },
  71         .state_count = TEGRA20_MAX_STATES,
  72         .safe_state_index = 0,
  73 };
  74
  75 #ifdef CONFIG_PM_SLEEP
  76 #ifdef CONFIG_SMP
  77 static int tegra20_reset_sleeping_cpu_1(void)
  78 {
  79         int ret = 0;
  80
  81         tegra_pen_lock();
  82
  83         if (readb(tegra20_cpu1_resettable_status) == CPU_RESETTABLE)
  84                 tegra20_cpu_shutdown(1);
  85         else
  86                 ret = -EINVAL;
  87
  88         tegra_pen_unlock();
  89
  90         return ret;
  91 }
  92
  93 static void tegra20_wake_cpu1_from_reset(void)
  94 {
  95         tegra_pen_lock();
  96
  97         tegra20_cpu_clear_resettable();
  98
  99         /* enable cpu clock on cpu */
 100         tegra_enable_cpu_clock(1);
 101
 102         /* take the CPU out of reset */
 103         tegra_cpu_out_of_reset(1);
 104
 105         /* unhalt the cpu */
 106         flowctrl_write_cpu_halt(1, 0);
 107
 108         tegra_pen_unlock();
 109 }
 110
 111 static int tegra20_reset_cpu_1(void)
 112 {
 113         if (!cpu_online(1) || !tegra20_reset_sleeping_cpu_1())
 114                 return 0;
 115
 116         tegra20_wake_cpu1_from_reset();
 117         return -EBUSY;
 118 }
 119 #else
 120 static inline void tegra20_wake_cpu1_from_reset(void)
 121 {
 122 }
 123
 124 static inline int tegra20_reset_cpu_1(void)
 125 {
 126         return 0;
 127 }
 128 #endif
 129
 130 static bool tegra20_cpu_cluster_power_down(struct cpuidle_device *dev,
 131                                            struct cpuidle_driver *drv,
 132                                            int index)
 133 {
 134         while (tegra20_cpu_is_resettable_soon())
 135                 cpu_relax();
 136
 137         if (tegra20_reset_cpu_1() || !tegra_cpu_rail_off_ready())
 138                 return false;
 139
 140         tegra_idle_lp2_last();
 141
 142         if (cpu_online(1))
 143                 tegra20_wake_cpu1_from_reset();
 144
 145         return true;
 146 }
 147
 148 #ifdef CONFIG_SMP
 149 static bool tegra20_idle_enter_lp2_cpu_1(struct cpuidle_device *dev,
 150                                          struct cpuidle_driver *drv,
 151                                          int index)
 152 {
 153         cpu_suspend(0, tegra20_sleep_cpu_secondary_finish);
 154
 155         tegra20_cpu_clear_resettable();
 156
 157         return true;
 158 }
 159 #else
 160 static inline bool tegra20_idle_enter_lp2_cpu_1(struct cpuidle_device *dev,
 161                                                 struct cpuidle_driver *drv,
 162                                                 int index)
 163 {
 164         return true;
 165 }
 166 #endif
 167
 168 static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev,
 169                                     struct cpuidle_driver *drv,
 170                                     int index)
 171 {
 172         bool entered_lp2 = false;
 173
 174         if (tegra_pending_sgi())
 175                 WRITE_ONCE(abort_flag, true);
 176
 177         cpuidle_coupled_parallel_barrier(dev, &abort_barrier);
 178
 179         if (abort_flag) {
 180                 cpuidle_coupled_parallel_barrier(dev, &abort_barrier);
 181                 abort_flag = false;     /* clean flag for next coming */
 182                 return -EINTR;
 183         }
 184
 185         local_fiq_disable();
 186
 187         tegra_set_cpu_in_lp2();
 188         cpu_pm_enter();
 189
 190         if (dev->cpu == 0)
 191                 entered_lp2 = tegra20_cpu_cluster_power_down(dev, drv, index);
 192         else
 193                 entered_lp2 = tegra20_idle_enter_lp2_cpu_1(dev, drv, index);
 194
 195         cpu_pm_exit();
 196         tegra_clear_cpu_in_lp2();
 197
 198         local_fiq_enable();
 199
 200         smp_rmb();
 201
 202         return entered_lp2 ? index : 0;
 203 }
 204 #endif
 205
 206 /*
 207  * Tegra20 HW appears to have a bug such that PCIe device interrupts, whether
 208  * they are legacy IRQs or MSI, are lost when LP2 is enabled. To work around
 209  * this, simply disable LP2 if the PCI driver and DT node are both enabled.
 210  */
 211 void tegra20_cpuidle_pcie_irqs_in_use(void)
 212 {
 213         pr_info_once(
 214                 "Disabling cpuidle LP2 state, since PCIe IRQs are in use\n");
 215         tegra_idle_driver.states[1].disabled = true;
 216 }
 217
 218 int __init tegra20_cpuidle_init(void)
 219 {
 220         return cpuidle_register(&tegra_idle_driver, cpu_possible_mask);
 221 }