git.rot13.org Git - linux/blob - drivers/dma/tegra20-apb-dma.c

   1 /*
   2  * DMA driver for Nvidia's Tegra20 APB DMA controller.
   3  *
   4  * Copyright (c) 2012-2013, NVIDIA CORPORATION.  All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #include <linux/bitops.h>
  20 #include <linux/clk.h>
  21 #include <linux/delay.h>
  22 #include <linux/dmaengine.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/err.h>
  25 #include <linux/init.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/io.h>
  28 #include <linux/mm.h>
  29 #include <linux/module.h>
  30 #include <linux/of.h>
  31 #include <linux/of_device.h>
  32 #include <linux/of_dma.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/pm.h>
  35 #include <linux/pm_runtime.h>
  36 #include <linux/reset.h>
  37 #include <linux/slab.h>
  38
  39 #include "dmaengine.h"
  40
  41 #define CREATE_TRACE_POINTS
  42 #include <trace/events/tegra_apb_dma.h>
  43
  44 #define TEGRA_APBDMA_GENERAL                    0x0
  45 #define TEGRA_APBDMA_GENERAL_ENABLE             BIT(31)
  46
  47 #define TEGRA_APBDMA_CONTROL                    0x010
  48 #define TEGRA_APBDMA_IRQ_MASK                   0x01c
  49 #define TEGRA_APBDMA_IRQ_MASK_SET               0x020
  50
  51 /* CSR register */
  52 #define TEGRA_APBDMA_CHAN_CSR                   0x00
  53 #define TEGRA_APBDMA_CSR_ENB                    BIT(31)
  54 #define TEGRA_APBDMA_CSR_IE_EOC                 BIT(30)
  55 #define TEGRA_APBDMA_CSR_HOLD                   BIT(29)
  56 #define TEGRA_APBDMA_CSR_DIR                    BIT(28)
  57 #define TEGRA_APBDMA_CSR_ONCE                   BIT(27)
  58 #define TEGRA_APBDMA_CSR_FLOW                   BIT(21)
  59 #define TEGRA_APBDMA_CSR_REQ_SEL_SHIFT          16
  60 #define TEGRA_APBDMA_CSR_REQ_SEL_MASK           0x1F
  61 #define TEGRA_APBDMA_CSR_WCOUNT_MASK            0xFFFC
  62
  63 /* STATUS register */
  64 #define TEGRA_APBDMA_CHAN_STATUS                0x004
  65 #define TEGRA_APBDMA_STATUS_BUSY                BIT(31)
  66 #define TEGRA_APBDMA_STATUS_ISE_EOC             BIT(30)
  67 #define TEGRA_APBDMA_STATUS_HALT                BIT(29)
  68 #define TEGRA_APBDMA_STATUS_PING_PONG           BIT(28)
  69 #define TEGRA_APBDMA_STATUS_COUNT_SHIFT         2
  70 #define TEGRA_APBDMA_STATUS_COUNT_MASK          0xFFFC
  71
  72 #define TEGRA_APBDMA_CHAN_CSRE                  0x00C
  73 #define TEGRA_APBDMA_CHAN_CSRE_PAUSE            (1 << 31)
  74
  75 /* AHB memory address */
  76 #define TEGRA_APBDMA_CHAN_AHBPTR                0x010
  77
  78 /* AHB sequence register */
  79 #define TEGRA_APBDMA_CHAN_AHBSEQ                0x14
  80 #define TEGRA_APBDMA_AHBSEQ_INTR_ENB            BIT(31)
  81 #define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_8         (0 << 28)
  82 #define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_16        (1 << 28)
  83 #define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32        (2 << 28)
  84 #define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_64        (3 << 28)
  85 #define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_128       (4 << 28)
  86 #define TEGRA_APBDMA_AHBSEQ_DATA_SWAP           BIT(27)
  87 #define TEGRA_APBDMA_AHBSEQ_BURST_1             (4 << 24)
  88 #define TEGRA_APBDMA_AHBSEQ_BURST_4             (5 << 24)
  89 #define TEGRA_APBDMA_AHBSEQ_BURST_8             (6 << 24)
  90 #define TEGRA_APBDMA_AHBSEQ_DBL_BUF             BIT(19)
  91 #define TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT          16
  92 #define TEGRA_APBDMA_AHBSEQ_WRAP_NONE           0
  93
  94 /* APB address */
  95 #define TEGRA_APBDMA_CHAN_APBPTR                0x018
  96
  97 /* APB sequence register */
  98 #define TEGRA_APBDMA_CHAN_APBSEQ                0x01c
  99 #define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_8         (0 << 28)
 100 #define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_16        (1 << 28)
 101 #define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_32        (2 << 28)
 102 #define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_64        (3 << 28)
 103 #define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_128       (4 << 28)
 104 #define TEGRA_APBDMA_APBSEQ_DATA_SWAP           BIT(27)
 105 #define TEGRA_APBDMA_APBSEQ_WRAP_WORD_1         (1 << 16)
 106
 107 /* Tegra148 specific registers */
 108 #define TEGRA_APBDMA_CHAN_WCOUNT                0x20
 109
 110 #define TEGRA_APBDMA_CHAN_WORD_TRANSFER         0x24
 111
 112 /*
 113  * If any burst is in flight and DMA paused then this is the time to complete
 114  * on-flight burst and update DMA status register.
 115  */
 116 #define TEGRA_APBDMA_BURST_COMPLETE_TIME        20
 117
 118 /* Channel base address offset from APBDMA base address */
 119 #define TEGRA_APBDMA_CHANNEL_BASE_ADD_OFFSET    0x1000
 120
 121 #define TEGRA_APBDMA_SLAVE_ID_INVALID   (TEGRA_APBDMA_CSR_REQ_SEL_MASK + 1)
 122
 123 struct tegra_dma;
 124
 125 /*
 126  * tegra_dma_chip_data Tegra chip specific DMA data
 127  * @nr_channels: Number of channels available in the controller.
 128  * @channel_reg_size: Channel register size/stride.
 129  * @max_dma_count: Maximum DMA transfer count supported by DMA controller.
 130  * @support_channel_pause: Support channel wise pause of dma.
 131  * @support_separate_wcount_reg: Support separate word count register.
 132  */
 133 struct tegra_dma_chip_data {
 134         int nr_channels;
 135         int channel_reg_size;
 136         int max_dma_count;
 137         bool support_channel_pause;
 138         bool support_separate_wcount_reg;
 139 };
 140
 141 /* DMA channel registers */
 142 struct tegra_dma_channel_regs {
 143         unsigned long   csr;
 144         unsigned long   ahb_ptr;
 145         unsigned long   apb_ptr;
 146         unsigned long   ahb_seq;
 147         unsigned long   apb_seq;
 148         unsigned long   wcount;
 149 };
 150
 151 /*
 152  * tegra_dma_sg_req: DMA request details to configure hardware. This
 153  * contains the details for one transfer to configure DMA hw.
 154  * The client's request for data transfer can be broken into multiple
 155  * sub-transfer as per requester details and hw support.
 156  * This sub transfer get added in the list of transfer and point to Tegra
 157  * DMA descriptor which manages the transfer details.
 158  */
 159 struct tegra_dma_sg_req {
 160         struct tegra_dma_channel_regs   ch_regs;
 161         unsigned int                    req_len;
 162         bool                            configured;
 163         bool                            last_sg;
 164         struct list_head                node;
 165         struct tegra_dma_desc           *dma_desc;
 166 };
 167
 168 /*
 169  * tegra_dma_desc: Tegra DMA descriptors which manages the client requests.
 170  * This descriptor keep track of transfer status, callbacks and request
 171  * counts etc.
 172  */
 173 struct tegra_dma_desc {
 174         struct dma_async_tx_descriptor  txd;
 175         unsigned int                    bytes_requested;
 176         unsigned int                    bytes_transferred;
 177         enum dma_status                 dma_status;
 178         struct list_head                node;
 179         struct list_head                tx_list;
 180         struct list_head                cb_node;
 181         int                             cb_count;
 182 };
 183
 184 struct tegra_dma_channel;
 185
 186 typedef void (*dma_isr_handler)(struct tegra_dma_channel *tdc,
 187                                 bool to_terminate);
 188
 189 /* tegra_dma_channel: Channel specific information */
 190 struct tegra_dma_channel {
 191         struct dma_chan         dma_chan;
 192         char                    name[12];
 193         bool                    config_init;
 194         int                     id;
 195         int                     irq;
 196         void __iomem            *chan_addr;
 197         spinlock_t              lock;
 198         bool                    busy;
 199         struct tegra_dma        *tdma;
 200         bool                    cyclic;
 201
 202         /* Different lists for managing the requests */
 203         struct list_head        free_sg_req;
 204         struct list_head        pending_sg_req;
 205         struct list_head        free_dma_desc;
 206         struct list_head        cb_desc;
 207
 208         /* ISR handler and tasklet for bottom half of isr handling */
 209         dma_isr_handler         isr_handler;
 210         struct tasklet_struct   tasklet;
 211
 212         /* Channel-slave specific configuration */
 213         unsigned int slave_id;
 214         struct dma_slave_config dma_sconfig;
 215         struct tegra_dma_channel_regs   channel_reg;
 216 };
 217
 218 /* tegra_dma: Tegra DMA specific information */
 219 struct tegra_dma {
 220         struct dma_device               dma_dev;
 221         struct device                   *dev;
 222         struct clk                      *dma_clk;
 223         struct reset_control            *rst;
 224         spinlock_t                      global_lock;
 225         void __iomem                    *base_addr;
 226         const struct tegra_dma_chip_data *chip_data;
 227
 228         /*
 229          * Counter for managing global pausing of the DMA controller.
 230          * Only applicable for devices that don't support individual
 231          * channel pausing.
 232          */
 233         u32                             global_pause_count;
 234
 235         /* Some register need to be cache before suspend */
 236         u32                             reg_gen;
 237
 238         /* Last member of the structure */
 239         struct tegra_dma_channel channels[0];
 240 };
 241
 242 static inline void tdma_write(struct tegra_dma *tdma, u32 reg, u32 val)
 243 {
 244         writel(val, tdma->base_addr + reg);
 245 }
 246
 247 static inline u32 tdma_read(struct tegra_dma *tdma, u32 reg)
 248 {
 249         return readl(tdma->base_addr + reg);
 250 }
 251
 252 static inline void tdc_write(struct tegra_dma_channel *tdc,
 253                 u32 reg, u32 val)
 254 {
 255         writel(val, tdc->chan_addr + reg);
 256 }
 257
 258 static inline u32 tdc_read(struct tegra_dma_channel *tdc, u32 reg)
 259 {
 260         return readl(tdc->chan_addr + reg);
 261 }
 262
 263 static inline struct tegra_dma_channel *to_tegra_dma_chan(struct dma_chan *dc)
 264 {
 265         return container_of(dc, struct tegra_dma_channel, dma_chan);
 266 }
 267
 268 static inline struct tegra_dma_desc *txd_to_tegra_dma_desc(
 269                 struct dma_async_tx_descriptor *td)
 270 {
 271         return container_of(td, struct tegra_dma_desc, txd);
 272 }
 273
 274 static inline struct device *tdc2dev(struct tegra_dma_channel *tdc)
 275 {
 276         return &tdc->dma_chan.dev->device;
 277 }
 278
 279 static dma_cookie_t tegra_dma_tx_submit(struct dma_async_tx_descriptor *tx);
 280 static int tegra_dma_runtime_suspend(struct device *dev);
 281 static int tegra_dma_runtime_resume(struct device *dev);
 282
 283 /* Get DMA desc from free list, if not there then allocate it.  */
 284 static struct tegra_dma_desc *tegra_dma_desc_get(
 285                 struct tegra_dma_channel *tdc)
 286 {
 287         struct tegra_dma_desc *dma_desc;
 288         unsigned long flags;
 289
 290         spin_lock_irqsave(&tdc->lock, flags);
 291
 292         /* Do not allocate if desc are waiting for ack */
 293         list_for_each_entry(dma_desc, &tdc->free_dma_desc, node) {
 294                 if (async_tx_test_ack(&dma_desc->txd)) {
 295                         list_del(&dma_desc->node);
 296                         spin_unlock_irqrestore(&tdc->lock, flags);
 297                         dma_desc->txd.flags = 0;
 298                         return dma_desc;
 299                 }
 300         }
 301
 302         spin_unlock_irqrestore(&tdc->lock, flags);
 303
 304         /* Allocate DMA desc */
 305         dma_desc = kzalloc(sizeof(*dma_desc), GFP_NOWAIT);
 306         if (!dma_desc)
 307                 return NULL;
 308
 309         dma_async_tx_descriptor_init(&dma_desc->txd, &tdc->dma_chan);
 310         dma_desc->txd.tx_submit = tegra_dma_tx_submit;
 311         dma_desc->txd.flags = 0;
 312         return dma_desc;
 313 }
 314
 315 static void tegra_dma_desc_put(struct tegra_dma_channel *tdc,
 316                 struct tegra_dma_desc *dma_desc)
 317 {
 318         unsigned long flags;
 319
 320         spin_lock_irqsave(&tdc->lock, flags);
 321         if (!list_empty(&dma_desc->tx_list))
 322                 list_splice_init(&dma_desc->tx_list, &tdc->free_sg_req);
 323         list_add_tail(&dma_desc->node, &tdc->free_dma_desc);
 324         spin_unlock_irqrestore(&tdc->lock, flags);
 325 }
 326
 327 static struct tegra_dma_sg_req *tegra_dma_sg_req_get(
 328                 struct tegra_dma_channel *tdc)
 329 {
 330         struct tegra_dma_sg_req *sg_req = NULL;
 331         unsigned long flags;
 332
 333         spin_lock_irqsave(&tdc->lock, flags);
 334         if (!list_empty(&tdc->free_sg_req)) {
 335                 sg_req = list_first_entry(&tdc->free_sg_req,
 336                                         typeof(*sg_req), node);
 337                 list_del(&sg_req->node);
 338                 spin_unlock_irqrestore(&tdc->lock, flags);
 339                 return sg_req;
 340         }
 341         spin_unlock_irqrestore(&tdc->lock, flags);
 342
 343         sg_req = kzalloc(sizeof(struct tegra_dma_sg_req), GFP_NOWAIT);
 344
 345         return sg_req;
 346 }
 347
 348 static int tegra_dma_slave_config(struct dma_chan *dc,
 349                 struct dma_slave_config *sconfig)
 350 {
 351         struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
 352
 353         if (!list_empty(&tdc->pending_sg_req)) {
 354                 dev_err(tdc2dev(tdc), "Configuration not allowed\n");
 355                 return -EBUSY;
 356         }
 357
 358         memcpy(&tdc->dma_sconfig, sconfig, sizeof(*sconfig));
 359         if (tdc->slave_id == TEGRA_APBDMA_SLAVE_ID_INVALID &&
 360             sconfig->device_fc) {
 361                 if (sconfig->slave_id > TEGRA_APBDMA_CSR_REQ_SEL_MASK)
 362                         return -EINVAL;
 363                 tdc->slave_id = sconfig->slave_id;
 364         }
 365         tdc->config_init = true;
 366         return 0;
 367 }
 368
 369 static void tegra_dma_global_pause(struct tegra_dma_channel *tdc,
 370         bool wait_for_burst_complete)
 371 {
 372         struct tegra_dma *tdma = tdc->tdma;
 373
 374         spin_lock(&tdma->global_lock);
 375
 376         if (tdc->tdma->global_pause_count == 0) {
 377                 tdma_write(tdma, TEGRA_APBDMA_GENERAL, 0);
 378                 if (wait_for_burst_complete)
 379                         udelay(TEGRA_APBDMA_BURST_COMPLETE_TIME);
 380         }
 381
 382         tdc->tdma->global_pause_count++;
 383
 384         spin_unlock(&tdma->global_lock);
 385 }
 386
 387 static void tegra_dma_global_resume(struct tegra_dma_channel *tdc)
 388 {
 389         struct tegra_dma *tdma = tdc->tdma;
 390
 391         spin_lock(&tdma->global_lock);
 392
 393         if (WARN_ON(tdc->tdma->global_pause_count == 0))
 394                 goto out;
 395
 396         if (--tdc->tdma->global_pause_count == 0)
 397                 tdma_write(tdma, TEGRA_APBDMA_GENERAL,
 398                            TEGRA_APBDMA_GENERAL_ENABLE);
 399
 400 out:
 401         spin_unlock(&tdma->global_lock);
 402 }
 403
 404 static void tegra_dma_pause(struct tegra_dma_channel *tdc,
 405         bool wait_for_burst_complete)
 406 {
 407         struct tegra_dma *tdma = tdc->tdma;
 408
 409         if (tdma->chip_data->support_channel_pause) {
 410                 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSRE,
 411                                 TEGRA_APBDMA_CHAN_CSRE_PAUSE);
 412                 if (wait_for_burst_complete)
 413                         udelay(TEGRA_APBDMA_BURST_COMPLETE_TIME);
 414         } else {
 415                 tegra_dma_global_pause(tdc, wait_for_burst_complete);
 416         }
 417 }
 418
 419 static void tegra_dma_resume(struct tegra_dma_channel *tdc)
 420 {
 421         struct tegra_dma *tdma = tdc->tdma;
 422
 423         if (tdma->chip_data->support_channel_pause) {
 424                 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSRE, 0);
 425         } else {
 426                 tegra_dma_global_resume(tdc);
 427         }
 428 }
 429
 430 static void tegra_dma_stop(struct tegra_dma_channel *tdc)
 431 {
 432         u32 csr;
 433         u32 status;
 434
 435         /* Disable interrupts */
 436         csr = tdc_read(tdc, TEGRA_APBDMA_CHAN_CSR);
 437         csr &= ~TEGRA_APBDMA_CSR_IE_EOC;
 438         tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, csr);
 439
 440         /* Disable DMA */
 441         csr &= ~TEGRA_APBDMA_CSR_ENB;
 442         tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, csr);
 443
 444         /* Clear interrupt status if it is there */
 445         status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
 446         if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
 447                 dev_dbg(tdc2dev(tdc), "%s():clearing interrupt\n", __func__);
 448                 tdc_write(tdc, TEGRA_APBDMA_CHAN_STATUS, status);
 449         }
 450         tdc->busy = false;
 451 }
 452
 453 static void tegra_dma_start(struct tegra_dma_channel *tdc,
 454                 struct tegra_dma_sg_req *sg_req)
 455 {
 456         struct tegra_dma_channel_regs *ch_regs = &sg_req->ch_regs;
 457
 458         tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, ch_regs->csr);
 459         tdc_write(tdc, TEGRA_APBDMA_CHAN_APBSEQ, ch_regs->apb_seq);
 460         tdc_write(tdc, TEGRA_APBDMA_CHAN_APBPTR, ch_regs->apb_ptr);
 461         tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBSEQ, ch_regs->ahb_seq);
 462         tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBPTR, ch_regs->ahb_ptr);
 463         if (tdc->tdma->chip_data->support_separate_wcount_reg)
 464                 tdc_write(tdc, TEGRA_APBDMA_CHAN_WCOUNT, ch_regs->wcount);
 465
 466         /* Start DMA */
 467         tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR,
 468                                 ch_regs->csr | TEGRA_APBDMA_CSR_ENB);
 469 }
 470
 471 static void tegra_dma_configure_for_next(struct tegra_dma_channel *tdc,
 472                 struct tegra_dma_sg_req *nsg_req)
 473 {
 474         unsigned long status;
 475
 476         /*
 477          * The DMA controller reloads the new configuration for next transfer
 478          * after last burst of current transfer completes.
 479          * If there is no IEC status then this makes sure that last burst
 480          * has not be completed. There may be case that last burst is on
 481          * flight and so it can complete but because DMA is paused, it
 482          * will not generates interrupt as well as not reload the new
 483          * configuration.
 484          * If there is already IEC status then interrupt handler need to
 485          * load new configuration.
 486          */
 487         tegra_dma_pause(tdc, false);
 488         status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
 489
 490         /*
 491          * If interrupt is pending then do nothing as the ISR will handle
 492          * the programing for new request.
 493          */
 494         if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
 495                 dev_err(tdc2dev(tdc),
 496                         "Skipping new configuration as interrupt is pending\n");
 497                 tegra_dma_resume(tdc);
 498                 return;
 499         }
 500
 501         /* Safe to program new configuration */
 502         tdc_write(tdc, TEGRA_APBDMA_CHAN_APBPTR, nsg_req->ch_regs.apb_ptr);
 503         tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBPTR, nsg_req->ch_regs.ahb_ptr);
 504         if (tdc->tdma->chip_data->support_separate_wcount_reg)
 505                 tdc_write(tdc, TEGRA_APBDMA_CHAN_WCOUNT,
 506                                                 nsg_req->ch_regs.wcount);
 507         tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR,
 508                                 nsg_req->ch_regs.csr | TEGRA_APBDMA_CSR_ENB);
 509         nsg_req->configured = true;
 510
 511         tegra_dma_resume(tdc);
 512 }
 513
 514 static void tdc_start_head_req(struct tegra_dma_channel *tdc)
 515 {
 516         struct tegra_dma_sg_req *sg_req;
 517
 518         if (list_empty(&tdc->pending_sg_req))
 519                 return;
 520
 521         sg_req = list_first_entry(&tdc->pending_sg_req,
 522                                         typeof(*sg_req), node);
 523         tegra_dma_start(tdc, sg_req);
 524         sg_req->configured = true;
 525         tdc->busy = true;
 526 }
 527
 528 static void tdc_configure_next_head_desc(struct tegra_dma_channel *tdc)
 529 {
 530         struct tegra_dma_sg_req *hsgreq;
 531         struct tegra_dma_sg_req *hnsgreq;
 532
 533         if (list_empty(&tdc->pending_sg_req))
 534                 return;
 535
 536         hsgreq = list_first_entry(&tdc->pending_sg_req, typeof(*hsgreq), node);
 537         if (!list_is_last(&hsgreq->node, &tdc->pending_sg_req)) {
 538                 hnsgreq = list_first_entry(&hsgreq->node,
 539                                         typeof(*hnsgreq), node);
 540                 tegra_dma_configure_for_next(tdc, hnsgreq);
 541         }
 542 }
 543
 544 static inline int get_current_xferred_count(struct tegra_dma_channel *tdc,
 545         struct tegra_dma_sg_req *sg_req, unsigned long status)
 546 {
 547         return sg_req->req_len - (status & TEGRA_APBDMA_STATUS_COUNT_MASK) - 4;
 548 }
 549
 550 static void tegra_dma_abort_all(struct tegra_dma_channel *tdc)
 551 {
 552         struct tegra_dma_sg_req *sgreq;
 553         struct tegra_dma_desc *dma_desc;
 554
 555         while (!list_empty(&tdc->pending_sg_req)) {
 556                 sgreq = list_first_entry(&tdc->pending_sg_req,
 557                                                 typeof(*sgreq), node);
 558                 list_move_tail(&sgreq->node, &tdc->free_sg_req);
 559                 if (sgreq->last_sg) {
 560                         dma_desc = sgreq->dma_desc;
 561                         dma_desc->dma_status = DMA_ERROR;
 562                         list_add_tail(&dma_desc->node, &tdc->free_dma_desc);
 563
 564                         /* Add in cb list if it is not there. */
 565                         if (!dma_desc->cb_count)
 566                                 list_add_tail(&dma_desc->cb_node,
 567                                                         &tdc->cb_desc);
 568                         dma_desc->cb_count++;
 569                 }
 570         }
 571         tdc->isr_handler = NULL;
 572 }
 573
 574 static bool handle_continuous_head_request(struct tegra_dma_channel *tdc,
 575                 struct tegra_dma_sg_req *last_sg_req, bool to_terminate)
 576 {
 577         struct tegra_dma_sg_req *hsgreq = NULL;
 578
 579         if (list_empty(&tdc->pending_sg_req)) {
 580                 dev_err(tdc2dev(tdc), "DMA is running without req\n");
 581                 tegra_dma_stop(tdc);
 582                 return false;
 583         }
 584
 585         /*
 586          * Check that head req on list should be in flight.
 587          * If it is not in flight then abort transfer as
 588          * looping of transfer can not continue.
 589          */
 590         hsgreq = list_first_entry(&tdc->pending_sg_req, typeof(*hsgreq), node);
 591         if (!hsgreq->configured) {
 592                 tegra_dma_stop(tdc);
 593                 dev_err(tdc2dev(tdc), "Error in DMA transfer, aborting DMA\n");
 594                 tegra_dma_abort_all(tdc);
 595                 return false;
 596         }
 597
 598         /* Configure next request */
 599         if (!to_terminate)
 600                 tdc_configure_next_head_desc(tdc);
 601         return true;
 602 }
 603
 604 static void handle_once_dma_done(struct tegra_dma_channel *tdc,
 605         bool to_terminate)
 606 {
 607         struct tegra_dma_sg_req *sgreq;
 608         struct tegra_dma_desc *dma_desc;
 609
 610         tdc->busy = false;
 611         sgreq = list_first_entry(&tdc->pending_sg_req, typeof(*sgreq), node);
 612         dma_desc = sgreq->dma_desc;
 613         dma_desc->bytes_transferred += sgreq->req_len;
 614
 615         list_del(&sgreq->node);
 616         if (sgreq->last_sg) {
 617                 dma_desc->dma_status = DMA_COMPLETE;
 618                 dma_cookie_complete(&dma_desc->txd);
 619                 if (!dma_desc->cb_count)
 620                         list_add_tail(&dma_desc->cb_node, &tdc->cb_desc);
 621                 dma_desc->cb_count++;
 622                 list_add_tail(&dma_desc->node, &tdc->free_dma_desc);
 623         }
 624         list_add_tail(&sgreq->node, &tdc->free_sg_req);
 625
 626         /* Do not start DMA if it is going to be terminate */
 627         if (to_terminate || list_empty(&tdc->pending_sg_req))
 628                 return;
 629
 630         tdc_start_head_req(tdc);
 631 }
 632
 633 static void handle_cont_sngl_cycle_dma_done(struct tegra_dma_channel *tdc,
 634                 bool to_terminate)
 635 {
 636         struct tegra_dma_sg_req *sgreq;
 637         struct tegra_dma_desc *dma_desc;
 638         bool st;
 639
 640         sgreq = list_first_entry(&tdc->pending_sg_req, typeof(*sgreq), node);
 641         dma_desc = sgreq->dma_desc;
 642         /* if we dma for long enough the transfer count will wrap */
 643         dma_desc->bytes_transferred =
 644                 (dma_desc->bytes_transferred + sgreq->req_len) %
 645                 dma_desc->bytes_requested;
 646
 647         /* Callback need to be call */
 648         if (!dma_desc->cb_count)
 649                 list_add_tail(&dma_desc->cb_node, &tdc->cb_desc);
 650         dma_desc->cb_count++;
 651
 652         /* If not last req then put at end of pending list */
 653         if (!list_is_last(&sgreq->node, &tdc->pending_sg_req)) {
 654                 list_move_tail(&sgreq->node, &tdc->pending_sg_req);
 655                 sgreq->configured = false;
 656                 st = handle_continuous_head_request(tdc, sgreq, to_terminate);
 657                 if (!st)
 658                         dma_desc->dma_status = DMA_ERROR;
 659         }
 660 }
 661
 662 static void tegra_dma_tasklet(unsigned long data)
 663 {
 664         struct tegra_dma_channel *tdc = (struct tegra_dma_channel *)data;
 665         struct dmaengine_desc_callback cb;
 666         struct tegra_dma_desc *dma_desc;
 667         unsigned long flags;
 668         int cb_count;
 669
 670         spin_lock_irqsave(&tdc->lock, flags);
 671         while (!list_empty(&tdc->cb_desc)) {
 672                 dma_desc  = list_first_entry(&tdc->cb_desc,
 673                                         typeof(*dma_desc), cb_node);
 674                 list_del(&dma_desc->cb_node);
 675                 dmaengine_desc_get_callback(&dma_desc->txd, &cb);
 676                 cb_count = dma_desc->cb_count;
 677                 dma_desc->cb_count = 0;
 678                 trace_tegra_dma_complete_cb(&tdc->dma_chan, cb_count,
 679                                             cb.callback);
 680                 spin_unlock_irqrestore(&tdc->lock, flags);
 681                 while (cb_count--)
 682                         dmaengine_desc_callback_invoke(&cb, NULL);
 683                 spin_lock_irqsave(&tdc->lock, flags);
 684         }
 685         spin_unlock_irqrestore(&tdc->lock, flags);
 686 }
 687
 688 static irqreturn_t tegra_dma_isr(int irq, void *dev_id)
 689 {
 690         struct tegra_dma_channel *tdc = dev_id;
 691         unsigned long status;
 692         unsigned long flags;
 693
 694         spin_lock_irqsave(&tdc->lock, flags);
 695
 696         trace_tegra_dma_isr(&tdc->dma_chan, irq);
 697         status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
 698         if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
 699                 tdc_write(tdc, TEGRA_APBDMA_CHAN_STATUS, status);
 700                 tdc->isr_handler(tdc, false);
 701                 tasklet_schedule(&tdc->tasklet);
 702                 spin_unlock_irqrestore(&tdc->lock, flags);
 703                 return IRQ_HANDLED;
 704         }
 705
 706         spin_unlock_irqrestore(&tdc->lock, flags);
 707         dev_info(tdc2dev(tdc),
 708                 "Interrupt already served status 0x%08lx\n", status);
 709         return IRQ_NONE;
 710 }
 711
 712 static dma_cookie_t tegra_dma_tx_submit(struct dma_async_tx_descriptor *txd)
 713 {
 714         struct tegra_dma_desc *dma_desc = txd_to_tegra_dma_desc(txd);
 715         struct tegra_dma_channel *tdc = to_tegra_dma_chan(txd->chan);
 716         unsigned long flags;
 717         dma_cookie_t cookie;
 718
 719         spin_lock_irqsave(&tdc->lock, flags);
 720         dma_desc->dma_status = DMA_IN_PROGRESS;
 721         cookie = dma_cookie_assign(&dma_desc->txd);
 722         list_splice_tail_init(&dma_desc->tx_list, &tdc->pending_sg_req);
 723         spin_unlock_irqrestore(&tdc->lock, flags);
 724         return cookie;
 725 }
 726
 727 static void tegra_dma_issue_pending(struct dma_chan *dc)
 728 {
 729         struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
 730         unsigned long flags;
 731
 732         spin_lock_irqsave(&tdc->lock, flags);
 733         if (list_empty(&tdc->pending_sg_req)) {
 734                 dev_err(tdc2dev(tdc), "No DMA request\n");
 735                 goto end;
 736         }
 737         if (!tdc->busy) {
 738                 tdc_start_head_req(tdc);
 739
 740                 /* Continuous single mode: Configure next req */
 741                 if (tdc->cyclic) {
 742                         /*
 743                          * Wait for 1 burst time for configure DMA for
 744                          * next transfer.
 745                          */
 746                         udelay(TEGRA_APBDMA_BURST_COMPLETE_TIME);
 747                         tdc_configure_next_head_desc(tdc);
 748                 }
 749         }
 750 end:
 751         spin_unlock_irqrestore(&tdc->lock, flags);
 752 }
 753
 754 static int tegra_dma_terminate_all(struct dma_chan *dc)
 755 {
 756         struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
 757         struct tegra_dma_sg_req *sgreq;
 758         struct tegra_dma_desc *dma_desc;
 759         unsigned long flags;
 760         unsigned long status;
 761         unsigned long wcount;
 762         bool was_busy;
 763
 764         spin_lock_irqsave(&tdc->lock, flags);
 765         if (list_empty(&tdc->pending_sg_req)) {
 766                 spin_unlock_irqrestore(&tdc->lock, flags);
 767                 return 0;
 768         }
 769
 770         if (!tdc->busy)
 771                 goto skip_dma_stop;
 772
 773         /* Pause DMA before checking the queue status */
 774         tegra_dma_pause(tdc, true);
 775
 776         status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
 777         if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
 778                 dev_dbg(tdc2dev(tdc), "%s():handling isr\n", __func__);
 779                 tdc->isr_handler(tdc, true);
 780                 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
 781         }
 782         if (tdc->tdma->chip_data->support_separate_wcount_reg)
 783                 wcount = tdc_read(tdc, TEGRA_APBDMA_CHAN_WORD_TRANSFER);
 784         else
 785                 wcount = status;
 786
 787         was_busy = tdc->busy;
 788         tegra_dma_stop(tdc);
 789
 790         if (!list_empty(&tdc->pending_sg_req) && was_busy) {
 791                 sgreq = list_first_entry(&tdc->pending_sg_req,
 792                                         typeof(*sgreq), node);
 793                 sgreq->dma_desc->bytes_transferred +=
 794                                 get_current_xferred_count(tdc, sgreq, wcount);
 795         }
 796         tegra_dma_resume(tdc);
 797
 798 skip_dma_stop:
 799         tegra_dma_abort_all(tdc);
 800
 801         while (!list_empty(&tdc->cb_desc)) {
 802                 dma_desc  = list_first_entry(&tdc->cb_desc,
 803                                         typeof(*dma_desc), cb_node);
 804                 list_del(&dma_desc->cb_node);
 805                 dma_desc->cb_count = 0;
 806         }
 807         spin_unlock_irqrestore(&tdc->lock, flags);
 808         return 0;
 809 }
 810
 811 static unsigned int tegra_dma_update_residual(struct tegra_dma_channel *tdc,
 812                                               struct tegra_dma_sg_req *sg_req,
 813                                               struct tegra_dma_desc *dma_desc,
 814                                               unsigned int residual)
 815 {
 816         unsigned long status;
 817         unsigned int result;
 818         int done;
 819
 820         /* if we're not the current request, then don't alter the residual */
 821         if (sg_req != list_first_entry(&tdc->pending_sg_req,
 822                                        struct tegra_dma_sg_req, node))
 823                 return residual;
 824
 825         status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
 826
 827         /* if we've got an interrupt pending on the channel, don't
 828          * try and deal with the residue as the hardware has likely
 829          * moved on to the next buffer. return all data moved.
 830          */
 831         if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
 832                 result = residual - sg_req->req_len;
 833                 goto out;
 834         }
 835
 836         if (tdc->tdma->chip_data->support_separate_wcount_reg)
 837                 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_WORD_TRANSFER);
 838
 839         /*
 840          * If the request is at the full point, then there is a
 841          * chance that we have read the status register in the
 842          * middle of the hardware reloading the next buffer.
 843          *
 844          * The sequence seems to be at the end of the buffer, to
 845          * load the new word count before raising the EOC flag (or
 846          * changing the ping-pong flag which could have also been
 847          * used to determine a new buffer). This  means there is a
 848          * small window where we cannot determine zero-done for the
 849          * current buffer, or moved to next buffer.
 850          */
 851         done = get_current_xferred_count(tdc, sg_req, status);
 852
 853         udelay(TEGRA_APBDMA_BURST_COMPLETE_TIME);
 854
 855         status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
 856
 857         if (status & TEGRA_APBDMA_STATUS_ISE_EOC)
 858                 result = residual - sg_req->req_len;
 859         else
 860                 result = residual - done;
 861 out:
 862 #ifdef DEBUG
 863         ahbptr = tdc_read(tdc, TEGRA_APBDMA_CHAN_AHBPTR);
 864
 865         dev_dbg(tdc2dev(tdc), "residual: req %08lx, ahb@%08lx, wcount %08lx, done %d\n",
 866                 sg_req->ch_regs.ahb_ptr, ahbptr, wcount, done);
 867 #endif
 868
 869         return result;
 870 }
 871
 872 static enum dma_status tegra_dma_tx_status(struct dma_chan *dc,
 873         dma_cookie_t cookie, struct dma_tx_state *txstate)
 874 {
 875         struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
 876         struct tegra_dma_desc *dma_desc;
 877         struct tegra_dma_sg_req *sg_req = NULL;
 878         enum dma_status ret;
 879         unsigned long flags;
 880         unsigned int residual;
 881
 882         ret = dma_cookie_status(dc, cookie, txstate);
 883         if (ret == DMA_COMPLETE)
 884                 return ret;
 885
 886         spin_lock_irqsave(&tdc->lock, flags);
 887
 888         /* Check on wait_ack desc status */
 889         list_for_each_entry(dma_desc, &tdc->free_dma_desc, node) {
 890                 if (dma_desc->txd.cookie == cookie) {
 891                         ret = dma_desc->dma_status;
 892                         goto found;
 893                 }
 894         }
 895
 896         /* Check in pending list */
 897         list_for_each_entry(sg_req, &tdc->pending_sg_req, node) {
 898                 dma_desc = sg_req->dma_desc;
 899                 if (dma_desc->txd.cookie == cookie) {
 900                         ret = dma_desc->dma_status;
 901                         goto found;
 902                 }
 903         }
 904
 905         dev_dbg(tdc2dev(tdc), "cookie %d not found\n", cookie);
 906         dma_desc = NULL;
 907
 908 found:
 909         if (dma_desc && txstate) {
 910                 residual = dma_desc->bytes_requested -
 911                            (dma_desc->bytes_transferred %
 912                             dma_desc->bytes_requested);
 913                 residual = tegra_dma_update_residual(tdc, sg_req, dma_desc, residual);
 914                 dma_set_residue(txstate, residual);
 915         }
 916
 917         trace_tegra_dma_tx_status(&tdc->dma_chan, cookie, txstate);
 918         spin_unlock_irqrestore(&tdc->lock, flags);
 919         return ret;
 920 }
 921
 922 static inline int get_bus_width(struct tegra_dma_channel *tdc,
 923                 enum dma_slave_buswidth slave_bw)
 924 {
 925         switch (slave_bw) {
 926         case DMA_SLAVE_BUSWIDTH_1_BYTE:
 927                 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_8;
 928         case DMA_SLAVE_BUSWIDTH_2_BYTES:
 929                 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_16;
 930         case DMA_SLAVE_BUSWIDTH_4_BYTES:
 931                 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_32;
 932         case DMA_SLAVE_BUSWIDTH_8_BYTES:
 933                 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_64;
 934         default:
 935                 dev_warn(tdc2dev(tdc),
 936                         "slave bw is not supported, using 32bits\n");
 937                 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_32;
 938         }
 939 }
 940
 941 static inline int get_burst_size(struct tegra_dma_channel *tdc,
 942         u32 burst_size, enum dma_slave_buswidth slave_bw, int len)
 943 {
 944         int burst_byte;
 945         int burst_ahb_width;
 946
 947         /*
 948          * burst_size from client is in terms of the bus_width.
 949          * convert them into AHB memory width which is 4 byte.
 950          */
 951         burst_byte = burst_size * slave_bw;
 952         burst_ahb_width = burst_byte / 4;
 953
 954         /* If burst size is 0 then calculate the burst size based on length */
 955         if (!burst_ahb_width) {
 956                 if (len & 0xF)
 957                         return TEGRA_APBDMA_AHBSEQ_BURST_1;
 958                 else if ((len >> 4) & 0x1)
 959                         return TEGRA_APBDMA_AHBSEQ_BURST_4;
 960                 else
 961                         return TEGRA_APBDMA_AHBSEQ_BURST_8;
 962         }
 963         if (burst_ahb_width < 4)
 964                 return TEGRA_APBDMA_AHBSEQ_BURST_1;
 965         else if (burst_ahb_width < 8)
 966                 return TEGRA_APBDMA_AHBSEQ_BURST_4;
 967         else
 968                 return TEGRA_APBDMA_AHBSEQ_BURST_8;
 969 }
 970
 971 static int get_transfer_param(struct tegra_dma_channel *tdc,
 972         enum dma_transfer_direction direction, unsigned long *apb_addr,
 973         unsigned long *apb_seq, unsigned long *csr, unsigned int *burst_size,
 974         enum dma_slave_buswidth *slave_bw)
 975 {
 976         switch (direction) {
 977         case DMA_MEM_TO_DEV:
 978                 *apb_addr = tdc->dma_sconfig.dst_addr;
 979                 *apb_seq = get_bus_width(tdc, tdc->dma_sconfig.dst_addr_width);
 980                 *burst_size = tdc->dma_sconfig.dst_maxburst;
 981                 *slave_bw = tdc->dma_sconfig.dst_addr_width;
 982                 *csr = TEGRA_APBDMA_CSR_DIR;
 983                 return 0;
 984
 985         case DMA_DEV_TO_MEM:
 986                 *apb_addr = tdc->dma_sconfig.src_addr;
 987                 *apb_seq = get_bus_width(tdc, tdc->dma_sconfig.src_addr_width);
 988                 *burst_size = tdc->dma_sconfig.src_maxburst;
 989                 *slave_bw = tdc->dma_sconfig.src_addr_width;
 990                 *csr = 0;
 991                 return 0;
 992
 993         default:
 994                 dev_err(tdc2dev(tdc), "DMA direction is not supported\n");
 995                 return -EINVAL;
 996         }
 997         return -EINVAL;
 998 }
 999
1000 static void tegra_dma_prep_wcount(struct tegra_dma_channel *tdc,
1001         struct tegra_dma_channel_regs *ch_regs, u32 len)
1002 {
1003         u32 len_field = (len - 4) & 0xFFFC;
1004
1005         if (tdc->tdma->chip_data->support_separate_wcount_reg)
1006                 ch_regs->wcount = len_field;
1007         else
1008                 ch_regs->csr |= len_field;
1009 }
1010
1011 static struct dma_async_tx_descriptor *tegra_dma_prep_slave_sg(
1012         struct dma_chan *dc, struct scatterlist *sgl, unsigned int sg_len,
1013         enum dma_transfer_direction direction, unsigned long flags,
1014         void *context)
1015 {
1016         struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
1017         struct tegra_dma_desc *dma_desc;
1018         unsigned int i;
1019         struct scatterlist *sg;
1020         unsigned long csr, ahb_seq, apb_ptr, apb_seq;
1021         struct list_head req_list;
1022         struct tegra_dma_sg_req  *sg_req = NULL;
1023         u32 burst_size;
1024         enum dma_slave_buswidth slave_bw;
1025
1026         if (!tdc->config_init) {
1027                 dev_err(tdc2dev(tdc), "DMA channel is not configured\n");
1028                 return NULL;
1029         }
1030         if (sg_len < 1) {
1031                 dev_err(tdc2dev(tdc), "Invalid segment length %d\n", sg_len);
1032                 return NULL;
1033         }
1034
1035         if (get_transfer_param(tdc, direction, &apb_ptr, &apb_seq, &csr,
1036                                 &burst_size, &slave_bw) < 0)
1037                 return NULL;
1038
1039         INIT_LIST_HEAD(&req_list);
1040
1041         ahb_seq = TEGRA_APBDMA_AHBSEQ_INTR_ENB;
1042         ahb_seq |= TEGRA_APBDMA_AHBSEQ_WRAP_NONE <<
1043                                         TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT;
1044         ahb_seq |= TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32;
1045
1046         csr |= TEGRA_APBDMA_CSR_ONCE;
1047
1048         if (tdc->slave_id != TEGRA_APBDMA_SLAVE_ID_INVALID) {
1049                 csr |= TEGRA_APBDMA_CSR_FLOW;
1050                 csr |= tdc->slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT;
1051         }
1052
1053         if (flags & DMA_PREP_INTERRUPT)
1054                 csr |= TEGRA_APBDMA_CSR_IE_EOC;
1055
1056         apb_seq |= TEGRA_APBDMA_APBSEQ_WRAP_WORD_1;
1057
1058         dma_desc = tegra_dma_desc_get(tdc);
1059         if (!dma_desc) {
1060                 dev_err(tdc2dev(tdc), "DMA descriptors not available\n");
1061                 return NULL;
1062         }
1063         INIT_LIST_HEAD(&dma_desc->tx_list);
1064         INIT_LIST_HEAD(&dma_desc->cb_node);
1065         dma_desc->cb_count = 0;
1066         dma_desc->bytes_requested = 0;
1067         dma_desc->bytes_transferred = 0;
1068         dma_desc->dma_status = DMA_IN_PROGRESS;
1069
1070         /* Make transfer requests */
1071         for_each_sg(sgl, sg, sg_len, i) {
1072                 u32 len, mem;
1073
1074                 mem = sg_dma_address(sg);
1075                 len = sg_dma_len(sg);
1076
1077                 if ((len & 3) || (mem & 3) ||
1078                                 (len > tdc->tdma->chip_data->max_dma_count)) {
1079                         dev_err(tdc2dev(tdc),
1080                                 "DMA length/memory address is not supported\n");
1081                         tegra_dma_desc_put(tdc, dma_desc);
1082                         return NULL;
1083                 }
1084
1085                 sg_req = tegra_dma_sg_req_get(tdc);
1086                 if (!sg_req) {
1087                         dev_err(tdc2dev(tdc), "DMA sg-req not available\n");
1088                         tegra_dma_desc_put(tdc, dma_desc);
1089                         return NULL;
1090                 }
1091
1092                 ahb_seq |= get_burst_size(tdc, burst_size, slave_bw, len);
1093                 dma_desc->bytes_requested += len;
1094
1095                 sg_req->ch_regs.apb_ptr = apb_ptr;
1096                 sg_req->ch_regs.ahb_ptr = mem;
1097                 sg_req->ch_regs.csr = csr;
1098                 tegra_dma_prep_wcount(tdc, &sg_req->ch_regs, len);
1099                 sg_req->ch_regs.apb_seq = apb_seq;
1100                 sg_req->ch_regs.ahb_seq = ahb_seq;
1101                 sg_req->configured = false;
1102                 sg_req->last_sg = false;
1103                 sg_req->dma_desc = dma_desc;
1104                 sg_req->req_len = len;
1105
1106                 list_add_tail(&sg_req->node, &dma_desc->tx_list);
1107         }
1108         sg_req->last_sg = true;
1109         if (flags & DMA_CTRL_ACK)
1110                 dma_desc->txd.flags = DMA_CTRL_ACK;
1111
1112         /*
1113          * Make sure that mode should not be conflicting with currently
1114          * configured mode.
1115          */
1116         if (!tdc->isr_handler) {
1117                 tdc->isr_handler = handle_once_dma_done;
1118                 tdc->cyclic = false;
1119         } else {
1120                 if (tdc->cyclic) {
1121                         dev_err(tdc2dev(tdc), "DMA configured in cyclic mode\n");
1122                         tegra_dma_desc_put(tdc, dma_desc);
1123                         return NULL;
1124                 }
1125         }
1126
1127         return &dma_desc->txd;
1128 }
1129
1130 static struct dma_async_tx_descriptor *tegra_dma_prep_dma_cyclic(
1131         struct dma_chan *dc, dma_addr_t buf_addr, size_t buf_len,
1132         size_t period_len, enum dma_transfer_direction direction,
1133         unsigned long flags)
1134 {
1135         struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
1136         struct tegra_dma_desc *dma_desc = NULL;
1137         struct tegra_dma_sg_req *sg_req = NULL;
1138         unsigned long csr, ahb_seq, apb_ptr, apb_seq;
1139         int len;
1140         size_t remain_len;
1141         dma_addr_t mem = buf_addr;
1142         u32 burst_size;
1143         enum dma_slave_buswidth slave_bw;
1144
1145         if (!buf_len || !period_len) {
1146                 dev_err(tdc2dev(tdc), "Invalid buffer/period len\n");
1147                 return NULL;
1148         }
1149
1150         if (!tdc->config_init) {
1151                 dev_err(tdc2dev(tdc), "DMA slave is not configured\n");
1152                 return NULL;
1153         }
1154
1155         /*
1156          * We allow to take more number of requests till DMA is
1157          * not started. The driver will loop over all requests.
1158          * Once DMA is started then new requests can be queued only after
1159          * terminating the DMA.
1160          */
1161         if (tdc->busy) {
1162                 dev_err(tdc2dev(tdc), "Request not allowed when DMA running\n");
1163                 return NULL;
1164         }
1165
1166         /*
1167          * We only support cycle transfer when buf_len is multiple of
1168          * period_len.
1169          */
1170         if (buf_len % period_len) {
1171                 dev_err(tdc2dev(tdc), "buf_len is not multiple of period_len\n");
1172                 return NULL;
1173         }
1174
1175         len = period_len;
1176         if ((len & 3) || (buf_addr & 3) ||
1177                         (len > tdc->tdma->chip_data->max_dma_count)) {
1178                 dev_err(tdc2dev(tdc), "Req len/mem address is not correct\n");
1179                 return NULL;
1180         }
1181
1182         if (get_transfer_param(tdc, direction, &apb_ptr, &apb_seq, &csr,
1183                                 &burst_size, &slave_bw) < 0)
1184                 return NULL;
1185
1186         ahb_seq = TEGRA_APBDMA_AHBSEQ_INTR_ENB;
1187         ahb_seq |= TEGRA_APBDMA_AHBSEQ_WRAP_NONE <<
1188                                         TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT;
1189         ahb_seq |= TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32;
1190
1191         if (tdc->slave_id != TEGRA_APBDMA_SLAVE_ID_INVALID) {
1192                 csr |= TEGRA_APBDMA_CSR_FLOW;
1193                 csr |= tdc->slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT;
1194         }
1195
1196         if (flags & DMA_PREP_INTERRUPT)
1197                 csr |= TEGRA_APBDMA_CSR_IE_EOC;
1198
1199         apb_seq |= TEGRA_APBDMA_APBSEQ_WRAP_WORD_1;
1200
1201         dma_desc = tegra_dma_desc_get(tdc);
1202         if (!dma_desc) {
1203                 dev_err(tdc2dev(tdc), "not enough descriptors available\n");
1204                 return NULL;
1205         }
1206
1207         INIT_LIST_HEAD(&dma_desc->tx_list);
1208         INIT_LIST_HEAD(&dma_desc->cb_node);
1209         dma_desc->cb_count = 0;
1210
1211         dma_desc->bytes_transferred = 0;
1212         dma_desc->bytes_requested = buf_len;
1213         remain_len = buf_len;
1214
1215         /* Split transfer equal to period size */
1216         while (remain_len) {
1217                 sg_req = tegra_dma_sg_req_get(tdc);
1218                 if (!sg_req) {
1219                         dev_err(tdc2dev(tdc), "DMA sg-req not available\n");
1220                         tegra_dma_desc_put(tdc, dma_desc);
1221                         return NULL;
1222                 }
1223
1224                 ahb_seq |= get_burst_size(tdc, burst_size, slave_bw, len);
1225                 sg_req->ch_regs.apb_ptr = apb_ptr;
1226                 sg_req->ch_regs.ahb_ptr = mem;
1227                 sg_req->ch_regs.csr = csr;
1228                 tegra_dma_prep_wcount(tdc, &sg_req->ch_regs, len);
1229                 sg_req->ch_regs.apb_seq = apb_seq;
1230                 sg_req->ch_regs.ahb_seq = ahb_seq;
1231                 sg_req->configured = false;
1232                 sg_req->last_sg = false;
1233                 sg_req->dma_desc = dma_desc;
1234                 sg_req->req_len = len;
1235
1236                 list_add_tail(&sg_req->node, &dma_desc->tx_list);
1237                 remain_len -= len;
1238                 mem += len;
1239         }
1240         sg_req->last_sg = true;
1241         if (flags & DMA_CTRL_ACK)
1242                 dma_desc->txd.flags = DMA_CTRL_ACK;
1243
1244         /*
1245          * Make sure that mode should not be conflicting with currently
1246          * configured mode.
1247          */
1248         if (!tdc->isr_handler) {
1249                 tdc->isr_handler = handle_cont_sngl_cycle_dma_done;
1250                 tdc->cyclic = true;
1251         } else {
1252                 if (!tdc->cyclic) {
1253                         dev_err(tdc2dev(tdc), "DMA configuration conflict\n");
1254                         tegra_dma_desc_put(tdc, dma_desc);
1255                         return NULL;
1256                 }
1257         }
1258
1259         return &dma_desc->txd;
1260 }
1261
1262 static int tegra_dma_alloc_chan_resources(struct dma_chan *dc)
1263 {
1264         struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
1265         struct tegra_dma *tdma = tdc->tdma;
1266         int ret;
1267
1268         dma_cookie_init(&tdc->dma_chan);
1269         tdc->config_init = false;
1270
1271         ret = pm_runtime_get_sync(tdma->dev);
1272         if (ret < 0)
1273                 return ret;
1274
1275         return 0;
1276 }
1277
1278 static void tegra_dma_free_chan_resources(struct dma_chan *dc)
1279 {
1280         struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
1281         struct tegra_dma *tdma = tdc->tdma;
1282         struct tegra_dma_desc *dma_desc;
1283         struct tegra_dma_sg_req *sg_req;
1284         struct list_head dma_desc_list;
1285         struct list_head sg_req_list;
1286         unsigned long flags;
1287
1288         INIT_LIST_HEAD(&dma_desc_list);
1289         INIT_LIST_HEAD(&sg_req_list);
1290
1291         dev_dbg(tdc2dev(tdc), "Freeing channel %d\n", tdc->id);
1292
1293         if (tdc->busy)
1294                 tegra_dma_terminate_all(dc);
1295
1296         spin_lock_irqsave(&tdc->lock, flags);
1297         list_splice_init(&tdc->pending_sg_req, &sg_req_list);
1298         list_splice_init(&tdc->free_sg_req, &sg_req_list);
1299         list_splice_init(&tdc->free_dma_desc, &dma_desc_list);
1300         INIT_LIST_HEAD(&tdc->cb_desc);
1301         tdc->config_init = false;
1302         tdc->isr_handler = NULL;
1303         spin_unlock_irqrestore(&tdc->lock, flags);
1304
1305         while (!list_empty(&dma_desc_list)) {
1306                 dma_desc = list_first_entry(&dma_desc_list,
1307                                         typeof(*dma_desc), node);
1308                 list_del(&dma_desc->node);
1309                 kfree(dma_desc);
1310         }
1311
1312         while (!list_empty(&sg_req_list)) {
1313                 sg_req = list_first_entry(&sg_req_list, typeof(*sg_req), node);
1314                 list_del(&sg_req->node);
1315                 kfree(sg_req);
1316         }
1317         pm_runtime_put(tdma->dev);
1318
1319         tdc->slave_id = TEGRA_APBDMA_SLAVE_ID_INVALID;
1320 }
1321
1322 static struct dma_chan *tegra_dma_of_xlate(struct of_phandle_args *dma_spec,
1323                                            struct of_dma *ofdma)
1324 {
1325         struct tegra_dma *tdma = ofdma->of_dma_data;
1326         struct dma_chan *chan;
1327         struct tegra_dma_channel *tdc;
1328
1329         if (dma_spec->args[0] > TEGRA_APBDMA_CSR_REQ_SEL_MASK) {
1330                 dev_err(tdma->dev, "Invalid slave id: %d\n", dma_spec->args[0]);
1331                 return NULL;
1332         }
1333
1334         chan = dma_get_any_slave_channel(&tdma->dma_dev);
1335         if (!chan)
1336                 return NULL;
1337
1338         tdc = to_tegra_dma_chan(chan);
1339         tdc->slave_id = dma_spec->args[0];
1340
1341         return chan;
1342 }
1343
1344 /* Tegra20 specific DMA controller information */
1345 static const struct tegra_dma_chip_data tegra20_dma_chip_data = {
1346         .nr_channels            = 16,
1347         .channel_reg_size       = 0x20,
1348         .max_dma_count          = 1024UL * 64,
1349         .support_channel_pause  = false,
1350         .support_separate_wcount_reg = false,
1351 };
1352
1353 /* Tegra30 specific DMA controller information */
1354 static const struct tegra_dma_chip_data tegra30_dma_chip_data = {
1355         .nr_channels            = 32,
1356         .channel_reg_size       = 0x20,
1357         .max_dma_count          = 1024UL * 64,
1358         .support_channel_pause  = false,
1359         .support_separate_wcount_reg = false,
1360 };
1361
1362 /* Tegra114 specific DMA controller information */
1363 static const struct tegra_dma_chip_data tegra114_dma_chip_data = {
1364         .nr_channels            = 32,
1365         .channel_reg_size       = 0x20,
1366         .max_dma_count          = 1024UL * 64,
1367         .support_channel_pause  = true,
1368         .support_separate_wcount_reg = false,
1369 };
1370
1371 /* Tegra148 specific DMA controller information */
1372 static const struct tegra_dma_chip_data tegra148_dma_chip_data = {
1373         .nr_channels            = 32,
1374         .channel_reg_size       = 0x40,
1375         .max_dma_count          = 1024UL * 64,
1376         .support_channel_pause  = true,
1377         .support_separate_wcount_reg = true,
1378 };
1379
1380 static int tegra_dma_probe(struct platform_device *pdev)
1381 {
1382         struct resource *res;
1383         struct tegra_dma *tdma;
1384         int ret;
1385         int i;
1386         const struct tegra_dma_chip_data *cdata;
1387
1388         cdata = of_device_get_match_data(&pdev->dev);
1389         if (!cdata) {
1390                 dev_err(&pdev->dev, "Error: No device match data found\n");
1391                 return -ENODEV;
1392         }
1393
1394         tdma = devm_kzalloc(&pdev->dev,
1395                             struct_size(tdma, channels, cdata->nr_channels),
1396                             GFP_KERNEL);
1397         if (!tdma)
1398                 return -ENOMEM;
1399
1400         tdma->dev = &pdev->dev;
1401         tdma->chip_data = cdata;
1402         platform_set_drvdata(pdev, tdma);
1403
1404         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1405         tdma->base_addr = devm_ioremap_resource(&pdev->dev, res);
1406         if (IS_ERR(tdma->base_addr))
1407                 return PTR_ERR(tdma->base_addr);
1408
1409         tdma->dma_clk = devm_clk_get(&pdev->dev, NULL);
1410         if (IS_ERR(tdma->dma_clk)) {
1411                 dev_err(&pdev->dev, "Error: Missing controller clock\n");
1412                 return PTR_ERR(tdma->dma_clk);
1413         }
1414
1415         tdma->rst = devm_reset_control_get(&pdev->dev, "dma");
1416         if (IS_ERR(tdma->rst)) {
1417                 dev_err(&pdev->dev, "Error: Missing reset\n");
1418                 return PTR_ERR(tdma->rst);
1419         }
1420
1421         spin_lock_init(&tdma->global_lock);
1422
1423         pm_runtime_enable(&pdev->dev);
1424         if (!pm_runtime_enabled(&pdev->dev))
1425                 ret = tegra_dma_runtime_resume(&pdev->dev);
1426         else
1427                 ret = pm_runtime_get_sync(&pdev->dev);
1428
1429         if (ret < 0) {
1430                 pm_runtime_disable(&pdev->dev);
1431                 return ret;
1432         }
1433
1434         /* Reset DMA controller */
1435         reset_control_assert(tdma->rst);
1436         udelay(2);
1437         reset_control_deassert(tdma->rst);
1438
1439         /* Enable global DMA registers */
1440         tdma_write(tdma, TEGRA_APBDMA_GENERAL, TEGRA_APBDMA_GENERAL_ENABLE);
1441         tdma_write(tdma, TEGRA_APBDMA_CONTROL, 0);
1442         tdma_write(tdma, TEGRA_APBDMA_IRQ_MASK_SET, 0xFFFFFFFFul);
1443
1444         pm_runtime_put(&pdev->dev);
1445
1446         INIT_LIST_HEAD(&tdma->dma_dev.channels);
1447         for (i = 0; i < cdata->nr_channels; i++) {
1448                 struct tegra_dma_channel *tdc = &tdma->channels[i];
1449
1450                 tdc->chan_addr = tdma->base_addr +
1451                                  TEGRA_APBDMA_CHANNEL_BASE_ADD_OFFSET +
1452                                  (i * cdata->channel_reg_size);
1453
1454                 res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
1455                 if (!res) {
1456                         ret = -EINVAL;
1457                         dev_err(&pdev->dev, "No irq resource for chan %d\n", i);
1458                         goto err_irq;
1459                 }
1460                 tdc->irq = res->start;
1461                 snprintf(tdc->name, sizeof(tdc->name), "apbdma.%d", i);
1462                 ret = request_irq(tdc->irq, tegra_dma_isr, 0, tdc->name, tdc);
1463                 if (ret) {
1464                         dev_err(&pdev->dev,
1465                                 "request_irq failed with err %d channel %d\n",
1466                                 ret, i);
1467                         goto err_irq;
1468                 }
1469
1470                 tdc->dma_chan.device = &tdma->dma_dev;
1471                 dma_cookie_init(&tdc->dma_chan);
1472                 list_add_tail(&tdc->dma_chan.device_node,
1473                                 &tdma->dma_dev.channels);
1474                 tdc->tdma = tdma;
1475                 tdc->id = i;
1476                 tdc->slave_id = TEGRA_APBDMA_SLAVE_ID_INVALID;
1477
1478                 tasklet_init(&tdc->tasklet, tegra_dma_tasklet,
1479                                 (unsigned long)tdc);
1480                 spin_lock_init(&tdc->lock);
1481
1482                 INIT_LIST_HEAD(&tdc->pending_sg_req);
1483                 INIT_LIST_HEAD(&tdc->free_sg_req);
1484                 INIT_LIST_HEAD(&tdc->free_dma_desc);
1485                 INIT_LIST_HEAD(&tdc->cb_desc);
1486         }
1487
1488         dma_cap_set(DMA_SLAVE, tdma->dma_dev.cap_mask);
1489         dma_cap_set(DMA_PRIVATE, tdma->dma_dev.cap_mask);
1490         dma_cap_set(DMA_CYCLIC, tdma->dma_dev.cap_mask);
1491
1492         tdma->global_pause_count = 0;
1493         tdma->dma_dev.dev = &pdev->dev;
1494         tdma->dma_dev.device_alloc_chan_resources =
1495                                         tegra_dma_alloc_chan_resources;
1496         tdma->dma_dev.device_free_chan_resources =
1497                                         tegra_dma_free_chan_resources;
1498         tdma->dma_dev.device_prep_slave_sg = tegra_dma_prep_slave_sg;
1499         tdma->dma_dev.device_prep_dma_cyclic = tegra_dma_prep_dma_cyclic;
1500         tdma->dma_dev.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
1501                 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
1502                 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
1503                 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES);
1504         tdma->dma_dev.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
1505                 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
1506                 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
1507                 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES);
1508         tdma->dma_dev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
1509         tdma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
1510         tdma->dma_dev.device_config = tegra_dma_slave_config;
1511         tdma->dma_dev.device_terminate_all = tegra_dma_terminate_all;
1512         tdma->dma_dev.device_tx_status = tegra_dma_tx_status;
1513         tdma->dma_dev.device_issue_pending = tegra_dma_issue_pending;
1514
1515         ret = dma_async_device_register(&tdma->dma_dev);
1516         if (ret < 0) {
1517                 dev_err(&pdev->dev,
1518                         "Tegra20 APB DMA driver registration failed %d\n", ret);
1519                 goto err_irq;
1520         }
1521
1522         ret = of_dma_controller_register(pdev->dev.of_node,
1523                                          tegra_dma_of_xlate, tdma);
1524         if (ret < 0) {
1525                 dev_err(&pdev->dev,
1526                         "Tegra20 APB DMA OF registration failed %d\n", ret);
1527                 goto err_unregister_dma_dev;
1528         }
1529
1530         dev_info(&pdev->dev, "Tegra20 APB DMA driver register %d channels\n",
1531                         cdata->nr_channels);
1532         return 0;
1533
1534 err_unregister_dma_dev:
1535         dma_async_device_unregister(&tdma->dma_dev);
1536 err_irq:
1537         while (--i >= 0) {
1538                 struct tegra_dma_channel *tdc = &tdma->channels[i];
1539
1540                 free_irq(tdc->irq, tdc);
1541                 tasklet_kill(&tdc->tasklet);
1542         }
1543
1544         pm_runtime_disable(&pdev->dev);
1545         if (!pm_runtime_status_suspended(&pdev->dev))
1546                 tegra_dma_runtime_suspend(&pdev->dev);
1547         return ret;
1548 }
1549
1550 static int tegra_dma_remove(struct platform_device *pdev)
1551 {
1552         struct tegra_dma *tdma = platform_get_drvdata(pdev);
1553         int i;
1554         struct tegra_dma_channel *tdc;
1555
1556         dma_async_device_unregister(&tdma->dma_dev);
1557
1558         for (i = 0; i < tdma->chip_data->nr_channels; ++i) {
1559                 tdc = &tdma->channels[i];
1560                 free_irq(tdc->irq, tdc);
1561                 tasklet_kill(&tdc->tasklet);
1562         }
1563
1564         pm_runtime_disable(&pdev->dev);
1565         if (!pm_runtime_status_suspended(&pdev->dev))
1566                 tegra_dma_runtime_suspend(&pdev->dev);
1567
1568         return 0;
1569 }
1570
1571 static int tegra_dma_runtime_suspend(struct device *dev)
1572 {
1573         struct tegra_dma *tdma = dev_get_drvdata(dev);
1574         int i;
1575
1576         tdma->reg_gen = tdma_read(tdma, TEGRA_APBDMA_GENERAL);
1577         for (i = 0; i < tdma->chip_data->nr_channels; i++) {
1578                 struct tegra_dma_channel *tdc = &tdma->channels[i];
1579                 struct tegra_dma_channel_regs *ch_reg = &tdc->channel_reg;
1580
1581                 /* Only save the state of DMA channels that are in use */
1582                 if (!tdc->config_init)
1583                         continue;
1584
1585                 ch_reg->csr = tdc_read(tdc, TEGRA_APBDMA_CHAN_CSR);
1586                 ch_reg->ahb_ptr = tdc_read(tdc, TEGRA_APBDMA_CHAN_AHBPTR);
1587                 ch_reg->apb_ptr = tdc_read(tdc, TEGRA_APBDMA_CHAN_APBPTR);
1588                 ch_reg->ahb_seq = tdc_read(tdc, TEGRA_APBDMA_CHAN_AHBSEQ);
1589                 ch_reg->apb_seq = tdc_read(tdc, TEGRA_APBDMA_CHAN_APBSEQ);
1590                 if (tdma->chip_data->support_separate_wcount_reg)
1591                         ch_reg->wcount = tdc_read(tdc,
1592                                                   TEGRA_APBDMA_CHAN_WCOUNT);
1593         }
1594
1595         clk_disable_unprepare(tdma->dma_clk);
1596
1597         return 0;
1598 }
1599
1600 static int tegra_dma_runtime_resume(struct device *dev)
1601 {
1602         struct tegra_dma *tdma = dev_get_drvdata(dev);
1603         int i, ret;
1604
1605         ret = clk_prepare_enable(tdma->dma_clk);
1606         if (ret < 0) {
1607                 dev_err(dev, "clk_enable failed: %d\n", ret);
1608                 return ret;
1609         }
1610
1611         tdma_write(tdma, TEGRA_APBDMA_GENERAL, tdma->reg_gen);
1612         tdma_write(tdma, TEGRA_APBDMA_CONTROL, 0);
1613         tdma_write(tdma, TEGRA_APBDMA_IRQ_MASK_SET, 0xFFFFFFFFul);
1614
1615         for (i = 0; i < tdma->chip_data->nr_channels; i++) {
1616                 struct tegra_dma_channel *tdc = &tdma->channels[i];
1617                 struct tegra_dma_channel_regs *ch_reg = &tdc->channel_reg;
1618
1619                 /* Only restore the state of DMA channels that are in use */
1620                 if (!tdc->config_init)
1621                         continue;
1622
1623                 if (tdma->chip_data->support_separate_wcount_reg)
1624                         tdc_write(tdc, TEGRA_APBDMA_CHAN_WCOUNT,
1625                                   ch_reg->wcount);
1626                 tdc_write(tdc, TEGRA_APBDMA_CHAN_APBSEQ, ch_reg->apb_seq);
1627                 tdc_write(tdc, TEGRA_APBDMA_CHAN_APBPTR, ch_reg->apb_ptr);
1628                 tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBSEQ, ch_reg->ahb_seq);
1629                 tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBPTR, ch_reg->ahb_ptr);
1630                 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR,
1631                         (ch_reg->csr & ~TEGRA_APBDMA_CSR_ENB));
1632         }
1633
1634         return 0;
1635 }
1636
1637 static const struct dev_pm_ops tegra_dma_dev_pm_ops = {
1638         SET_RUNTIME_PM_OPS(tegra_dma_runtime_suspend, tegra_dma_runtime_resume,
1639                            NULL)
1640         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1641                                 pm_runtime_force_resume)
1642 };
1643
1644 static const struct of_device_id tegra_dma_of_match[] = {
1645         {
1646                 .compatible = "nvidia,tegra148-apbdma",
1647                 .data = &tegra148_dma_chip_data,
1648         }, {
1649                 .compatible = "nvidia,tegra114-apbdma",
1650                 .data = &tegra114_dma_chip_data,
1651         }, {
1652                 .compatible = "nvidia,tegra30-apbdma",
1653                 .data = &tegra30_dma_chip_data,
1654         }, {
1655                 .compatible = "nvidia,tegra20-apbdma",
1656                 .data = &tegra20_dma_chip_data,
1657         }, {
1658         },
1659 };
1660 MODULE_DEVICE_TABLE(of, tegra_dma_of_match);
1661
1662 static struct platform_driver tegra_dmac_driver = {
1663         .driver = {
1664                 .name   = "tegra-apbdma",
1665                 .pm     = &tegra_dma_dev_pm_ops,
1666                 .of_match_table = tegra_dma_of_match,
1667         },
1668         .probe          = tegra_dma_probe,
1669         .remove         = tegra_dma_remove,
1670 };
1671
1672 module_platform_driver(tegra_dmac_driver);
1673
1674 MODULE_ALIAS("platform:tegra20-apbdma");
1675 MODULE_DESCRIPTION("NVIDIA Tegra APB DMA Controller driver");
1676 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
1677 MODULE_LICENSE("GPL v2");