3 * Copyright (C) Igor Sysoev
7 #include <ngx_config.h>
11 #if (( __i386__ || __amd64__ ) && ( __GNUC__ || __INTEL_COMPILER ))
14 static ngx_inline void ngx_cpuid(uint32_t i, uint32_t *buf);
19 static ngx_inline void
20 ngx_cpuid(uint32_t i, uint32_t *buf)
24 * we could not use %ebx as output parameter if gcc builds PIC,
25 * and we could not save %ebx on stack, because %esp is used,
26 * when the -fomit-frame-pointer optimization is specified.
37 " mov %%ecx, 12(%1); "
41 : : "a" (i), "D" (buf) : "ecx", "edx", "esi", "memory" );
48 static ngx_inline void
49 ngx_cpuid(uint32_t i, uint32_t *buf)
51 uint32_t eax, ebx, ecx, edx;
57 : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx) : "a" (i) );
69 /* auto detect the L2 cache line size of modern and widespread CPUs */
75 uint32_t vbuf[5], cpu[4];
85 vendor = (u_char *) &vbuf[1];
93 if (ngx_strcmp(vendor, "GenuineIntel") == 0) {
95 switch ((cpu[0] & 0xf00) >> 8) {
99 ngx_cacheline_size = 32;
102 /* Pentium Pro, II, III */
104 ngx_cacheline_size = 32;
106 if ((cpu[0] & 0xf0) >= 0xd0) {
108 ngx_cacheline_size = 64;
114 * Pentium 4, although its cache line size is 64 bytes,
115 * it prefetches up to two cache lines during memory read
118 ngx_cacheline_size = 128;
122 } else if (ngx_strcmp(vendor, "AuthenticAMD") == 0) {
123 ngx_cacheline_size = 64;