#include <comm/sercomm.h>
#include <calypso/irq.h>
-#include <calypso/uart.h>
+#include <uart.h>
#define BASE_ADDR_UART_MODEM 0xffff5000
#define OFFSET_IRDA 0x800
#define LCR7BIT 0x80
#define LCRBFBIT 0x40
#define MCR6BIT 0x20
-#define REG_OFFS(m) ((m) &= ~(LCR7BIT|LCRBFBIT|MCR6BIT))
+#define REG_OFFS(m) ((m) & ~(LCR7BIT|LCRBFBIT|MCR6BIT))
/* read access LCR[7] = 0 */
enum uart_reg {
RHR = 0,
static uint8_t old_lcr;
static void uart_set_lcr_bf(int uart, int on)
{
- old_lcr = readb(UART_REG(uart, LCR));
-
- if (on)
+ if (on) {
+ old_lcr = readb(UART_REG(uart, LCR));
writeb(0xBF, UART_REG(uart, LCR));
- else
+ } else {
writeb(old_lcr, UART_REG(uart, LCR));
+ }
}
/* Enable or disable the TCR_TLR latch bit in MCR[6] */
writeb(UART_REG_UIR, 0x00);
}
#endif
+
+ /* if we don't initialize these, we get strange corruptions in the
+ received data... :-( */
+ uart_reg_write(uart, MDR1, 0x07); /* turn off UART */
+ uart_reg_write(uart, XON1, 0x00); /* Xon1/Addr Register */
+ uart_reg_write(uart, XON2, 0x00); /* Xon2/Addr Register */
+ uart_reg_write(uart, XOFF1, 0x00); /* Xoff1 Register */
+ uart_reg_write(uart, XOFF2, 0x00); /* Xoff2 Register */
+ uart_reg_write(uart, EFR, 0x00); /* Enhanced Features Register */
+
/* select UART mode */
uart_reg_write(uart, MDR1, 0);
/* no XON/XOFF flow control, ENHANCED_EN, no auto-RTS/CTS */
{
uint16_t div;
- if (bdrt > ARRAY_SIZE(divider))
+ if (bdrt >= ARRAY_SIZE(divider))
return -1;
div = divider[bdrt];