2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <linux/crc32.h>
26 #include <linux/kernel.h>
27 #include <linux/version.h>
28 #include <linux/module.h>
29 #include <linux/netdevice.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/etherdevice.h>
32 #include <linux/ethtool.h>
33 #include <linux/pci.h>
35 #include <linux/tcp.h>
37 #include <linux/delay.h>
38 #include <linux/workqueue.h>
39 #include <linux/if_vlan.h>
40 #include <linux/prefetch.h>
41 #include <linux/mii.h>
45 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
46 #define SKY2_VLAN_TAG_USED 1
51 #define DRV_NAME "sky2"
52 #define DRV_VERSION "1.12"
53 #define PFX DRV_NAME " "
56 * The Yukon II chipset takes 64 bit command blocks (called list elements)
57 * that are organized into three (receive, transmit, status) different rings
61 #define RX_LE_SIZE 1024
62 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
63 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
64 #define RX_DEF_PENDING RX_MAX_PENDING
65 #define RX_SKB_ALIGN 8
66 #define RX_BUF_WRITE 16
68 #define TX_RING_SIZE 512
69 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
70 #define TX_MIN_PENDING 64
71 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
73 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
74 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
75 #define TX_WATCHDOG (5 * HZ)
76 #define NAPI_WEIGHT 64
77 #define PHY_RETRIES 1000
79 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
81 static const u32 default_msg =
82 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
83 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
84 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
86 static int debug = -1; /* defaults above */
87 module_param(debug, int, 0);
88 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
90 static int copybreak __read_mostly = 128;
91 module_param(copybreak, int, 0);
92 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
94 static int disable_msi = 0;
95 module_param(disable_msi, int, 0);
96 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
98 static int idle_timeout = 0;
99 module_param(idle_timeout, int, 0);
100 MODULE_PARM_DESC(idle_timeout, "Watchdog timer for lost interrupts (ms)");
102 static const struct pci_device_id sky2_id_table[] = {
103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
136 MODULE_DEVICE_TABLE(pci, sky2_id_table);
138 /* Avoid conditionals by using array */
139 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
140 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
141 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
143 /* This driver supports yukon2 chipset only */
144 static const char *yukon2_name[] = {
146 "EC Ultra", /* 0xb4 */
147 "Extreme", /* 0xb5 */
152 /* Access to external PHY */
153 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
157 gma_write16(hw, port, GM_SMI_DATA, val);
158 gma_write16(hw, port, GM_SMI_CTRL,
159 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
161 for (i = 0; i < PHY_RETRIES; i++) {
162 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
167 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
171 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
175 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
176 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
178 for (i = 0; i < PHY_RETRIES; i++) {
179 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
180 *val = gma_read16(hw, port, GM_SMI_DATA);
190 static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
194 if (__gm_phy_read(hw, port, reg, &v) != 0)
195 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
200 static void sky2_power_on(struct sky2_hw *hw)
202 /* switch power to VCC (WA for VAUX problem) */
203 sky2_write8(hw, B0_POWER_CTRL,
204 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
206 /* disable Core Clock Division, */
207 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
209 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
210 /* enable bits are inverted */
211 sky2_write8(hw, B2_Y2_CLK_GATE,
212 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
213 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
214 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
216 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
218 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
221 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
222 reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);
223 reg1 &= P_ASPM_CONTROL_MSK;
224 sky2_pci_write32(hw, PCI_DEV_REG4, reg1);
225 sky2_pci_write32(hw, PCI_DEV_REG5, 0);
229 static void sky2_power_aux(struct sky2_hw *hw)
231 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
232 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
234 /* enable bits are inverted */
235 sky2_write8(hw, B2_Y2_CLK_GATE,
236 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
237 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
238 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
240 /* switch power to VAUX */
241 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
242 sky2_write8(hw, B0_POWER_CTRL,
243 (PC_VAUX_ENA | PC_VCC_ENA |
244 PC_VAUX_ON | PC_VCC_OFF));
247 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
251 /* disable all GMAC IRQ's */
252 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
253 /* disable PHY IRQs */
254 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
256 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
257 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
258 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
259 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
261 reg = gma_read16(hw, port, GM_RX_CTRL);
262 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
263 gma_write16(hw, port, GM_RX_CTRL, reg);
266 /* flow control to advertise bits */
267 static const u16 copper_fc_adv[] = {
269 [FC_TX] = PHY_M_AN_ASP,
270 [FC_RX] = PHY_M_AN_PC,
271 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
274 /* flow control to advertise bits when using 1000BaseX */
275 static const u16 fiber_fc_adv[] = {
276 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
277 [FC_TX] = PHY_M_P_ASYM_MD_X,
278 [FC_RX] = PHY_M_P_SYM_MD_X,
279 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
282 /* flow control to GMA disable bits */
283 static const u16 gm_fc_disable[] = {
284 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
285 [FC_TX] = GM_GPCR_FC_RX_DIS,
286 [FC_RX] = GM_GPCR_FC_TX_DIS,
291 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
293 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
294 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
296 if (sky2->autoneg == AUTONEG_ENABLE
297 && !(hw->chip_id == CHIP_ID_YUKON_XL
298 || hw->chip_id == CHIP_ID_YUKON_EC_U
299 || hw->chip_id == CHIP_ID_YUKON_EX)) {
300 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
302 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
304 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
306 if (hw->chip_id == CHIP_ID_YUKON_EC)
307 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
309 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
311 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
314 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
315 if (sky2_is_copper(hw)) {
316 if (hw->chip_id == CHIP_ID_YUKON_FE) {
317 /* enable automatic crossover */
318 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
320 /* disable energy detect */
321 ctrl &= ~PHY_M_PC_EN_DET_MSK;
323 /* enable automatic crossover */
324 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
326 if (sky2->autoneg == AUTONEG_ENABLE
327 && (hw->chip_id == CHIP_ID_YUKON_XL
328 || hw->chip_id == CHIP_ID_YUKON_EC_U
329 || hw->chip_id == CHIP_ID_YUKON_EX)) {
330 ctrl &= ~PHY_M_PC_DSC_MSK;
331 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
335 /* workaround for deviation #4.88 (CRC errors) */
336 /* disable Automatic Crossover */
338 ctrl &= ~PHY_M_PC_MDIX_MSK;
341 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
343 /* special setup for PHY 88E1112 Fiber */
344 if (hw->chip_id == CHIP_ID_YUKON_XL && !sky2_is_copper(hw)) {
345 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
347 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
348 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
349 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
350 ctrl &= ~PHY_M_MAC_MD_MSK;
351 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
352 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
354 if (hw->pmd_type == 'P') {
355 /* select page 1 to access Fiber registers */
356 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
358 /* for SFP-module set SIGDET polarity to low */
359 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
360 ctrl |= PHY_M_FIB_SIGD_POL;
361 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
364 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
372 if (sky2->autoneg == AUTONEG_ENABLE) {
373 if (sky2_is_copper(hw)) {
374 if (sky2->advertising & ADVERTISED_1000baseT_Full)
375 ct1000 |= PHY_M_1000C_AFD;
376 if (sky2->advertising & ADVERTISED_1000baseT_Half)
377 ct1000 |= PHY_M_1000C_AHD;
378 if (sky2->advertising & ADVERTISED_100baseT_Full)
379 adv |= PHY_M_AN_100_FD;
380 if (sky2->advertising & ADVERTISED_100baseT_Half)
381 adv |= PHY_M_AN_100_HD;
382 if (sky2->advertising & ADVERTISED_10baseT_Full)
383 adv |= PHY_M_AN_10_FD;
384 if (sky2->advertising & ADVERTISED_10baseT_Half)
385 adv |= PHY_M_AN_10_HD;
387 adv |= copper_fc_adv[sky2->flow_mode];
388 } else { /* special defines for FIBER (88E1040S only) */
389 if (sky2->advertising & ADVERTISED_1000baseT_Full)
390 adv |= PHY_M_AN_1000X_AFD;
391 if (sky2->advertising & ADVERTISED_1000baseT_Half)
392 adv |= PHY_M_AN_1000X_AHD;
394 adv |= fiber_fc_adv[sky2->flow_mode];
397 /* Restart Auto-negotiation */
398 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
400 /* forced speed/duplex settings */
401 ct1000 = PHY_M_1000C_MSE;
403 /* Disable auto update for duplex flow control and speed */
404 reg |= GM_GPCR_AU_ALL_DIS;
406 switch (sky2->speed) {
408 ctrl |= PHY_CT_SP1000;
409 reg |= GM_GPCR_SPEED_1000;
412 ctrl |= PHY_CT_SP100;
413 reg |= GM_GPCR_SPEED_100;
417 if (sky2->duplex == DUPLEX_FULL) {
418 reg |= GM_GPCR_DUP_FULL;
419 ctrl |= PHY_CT_DUP_MD;
420 } else if (sky2->speed < SPEED_1000)
421 sky2->flow_mode = FC_NONE;
424 reg |= gm_fc_disable[sky2->flow_mode];
426 /* Forward pause packets to GMAC? */
427 if (sky2->flow_mode & FC_RX)
428 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
430 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
433 gma_write16(hw, port, GM_GP_CTRL, reg);
435 if (hw->chip_id != CHIP_ID_YUKON_FE)
436 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
438 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
439 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
441 /* Setup Phy LED's */
442 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
445 switch (hw->chip_id) {
446 case CHIP_ID_YUKON_FE:
447 /* on 88E3082 these bits are at 11..9 (shifted left) */
448 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
450 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
452 /* delete ACT LED control bits */
453 ctrl &= ~PHY_M_FELP_LED1_MSK;
454 /* change ACT LED control to blink mode */
455 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
456 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
459 case CHIP_ID_YUKON_XL:
460 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
462 /* select page 3 to access LED control register */
463 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
465 /* set LED Function Control register */
466 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
467 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
468 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
469 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
470 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
472 /* set Polarity Control register */
473 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
474 (PHY_M_POLC_LS1_P_MIX(4) |
475 PHY_M_POLC_IS0_P_MIX(4) |
476 PHY_M_POLC_LOS_CTRL(2) |
477 PHY_M_POLC_INIT_CTRL(2) |
478 PHY_M_POLC_STA1_CTRL(2) |
479 PHY_M_POLC_STA0_CTRL(2)));
481 /* restore page register */
482 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
485 case CHIP_ID_YUKON_EC_U:
486 case CHIP_ID_YUKON_EX:
487 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
489 /* select page 3 to access LED control register */
490 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
492 /* set LED Function Control register */
493 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
494 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
495 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
496 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
497 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
499 /* set Blink Rate in LED Timer Control Register */
500 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
501 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
502 /* restore page register */
503 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
507 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
508 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
509 /* turn off the Rx LED (LED_RX) */
510 ledover &= ~PHY_M_LED_MO_RX;
513 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == CHIP_REV_YU_EC_A1) {
514 /* apply fixes in PHY AFE */
515 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
516 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
518 /* increase differential signal amplitude in 10BASE-T */
519 gm_phy_write(hw, port, 0x18, 0xaa99);
520 gm_phy_write(hw, port, 0x17, 0x2011);
522 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
523 gm_phy_write(hw, port, 0x18, 0xa204);
524 gm_phy_write(hw, port, 0x17, 0x2002);
526 /* set page register to 0 */
527 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
528 } else if (hw->chip_id != CHIP_ID_YUKON_EX) {
529 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
531 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
532 /* turn on 100 Mbps LED (LED_LINK100) */
533 ledover |= PHY_M_LED_MO_100;
537 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
541 /* Enable phy interrupt on auto-negotiation complete (or link up) */
542 if (sky2->autoneg == AUTONEG_ENABLE)
543 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
545 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
548 static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
551 static const u32 phy_power[]
552 = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
554 /* looks like this XL is back asswards .. */
555 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
558 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
559 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
561 /* Turn off phy power saving */
562 reg1 &= ~phy_power[port];
564 reg1 |= phy_power[port];
566 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
567 sky2_pci_read32(hw, PCI_DEV_REG1);
568 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
572 /* Force a renegotiation */
573 static void sky2_phy_reinit(struct sky2_port *sky2)
575 spin_lock_bh(&sky2->phy_lock);
576 sky2_phy_init(sky2->hw, sky2->port);
577 spin_unlock_bh(&sky2->phy_lock);
580 /* Put device in state to listen for Wake On Lan */
581 static void sky2_wol_init(struct sky2_port *sky2)
583 struct sky2_hw *hw = sky2->hw;
584 unsigned port = sky2->port;
585 enum flow_control save_mode;
589 /* Bring hardware out of reset */
590 sky2_write16(hw, B0_CTST, CS_RST_CLR);
591 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
593 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
594 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
597 * sky2_reset will re-enable on resume
599 save_mode = sky2->flow_mode;
600 ctrl = sky2->advertising;
602 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
603 sky2->flow_mode = FC_NONE;
604 sky2_phy_power(hw, port, 1);
605 sky2_phy_reinit(sky2);
607 sky2->flow_mode = save_mode;
608 sky2->advertising = ctrl;
610 /* Set GMAC to no flow control and auto update for speed/duplex */
611 gma_write16(hw, port, GM_GP_CTRL,
612 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
613 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
615 /* Set WOL address */
616 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
617 sky2->netdev->dev_addr, ETH_ALEN);
619 /* Turn on appropriate WOL control bits */
620 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
622 if (sky2->wol & WAKE_PHY)
623 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
625 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
627 if (sky2->wol & WAKE_MAGIC)
628 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
630 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
632 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
633 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
635 /* Turn on legacy PCI-Express PME mode */
636 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
637 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
638 reg1 |= PCI_Y2_PME_LEGACY;
639 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
640 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
643 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
647 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
649 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
652 const u8 *addr = hw->dev[port]->dev_addr;
654 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
655 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
657 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
659 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
660 /* WA DEV_472 -- looks like crossed wires on port 2 */
661 /* clear GMAC 1 Control reset */
662 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
664 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
665 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
666 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
667 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
668 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
671 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
673 /* Enable Transmit FIFO Underrun */
674 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
676 spin_lock_bh(&sky2->phy_lock);
677 sky2_phy_init(hw, port);
678 spin_unlock_bh(&sky2->phy_lock);
681 reg = gma_read16(hw, port, GM_PHY_ADDR);
682 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
684 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
685 gma_read16(hw, port, i);
686 gma_write16(hw, port, GM_PHY_ADDR, reg);
688 /* transmit control */
689 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
691 /* receive control reg: unicast + multicast + no FCS */
692 gma_write16(hw, port, GM_RX_CTRL,
693 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
695 /* transmit flow control */
696 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
698 /* transmit parameter */
699 gma_write16(hw, port, GM_TX_PARAM,
700 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
701 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
702 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
703 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
705 /* serial mode register */
706 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
707 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
709 if (hw->dev[port]->mtu > ETH_DATA_LEN)
710 reg |= GM_SMOD_JUMBO_ENA;
712 gma_write16(hw, port, GM_SERIAL_MODE, reg);
714 /* virtual address for data */
715 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
717 /* physical address: used for pause frames */
718 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
720 /* ignore counter overflows */
721 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
722 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
723 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
725 /* Configure Rx MAC FIFO */
726 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
727 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
728 GMF_OPER_ON | GMF_RX_F_FL_ON);
730 /* Flush Rx MAC FIFO on any flow control or error */
731 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
733 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
734 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
736 /* Configure Tx MAC FIFO */
737 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
738 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
740 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
741 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
742 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
743 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
744 /* set Tx GMAC FIFO Almost Empty Threshold */
745 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
746 /* Disable Store & Forward mode for TX */
747 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
753 /* Assign Ram Buffer allocation to queue */
754 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
758 /* convert from K bytes to qwords used for hw register */
761 end = start + space - 1;
763 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
764 sky2_write32(hw, RB_ADDR(q, RB_START), start);
765 sky2_write32(hw, RB_ADDR(q, RB_END), end);
766 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
767 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
769 if (q == Q_R1 || q == Q_R2) {
770 u32 tp = space - space/4;
772 /* On receive queue's set the thresholds
773 * give receiver priority when > 3/4 full
774 * send pause when down to 2K
776 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
777 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
780 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
781 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
783 /* Enable store & forward on Tx queue's because
784 * Tx FIFO is only 1K on Yukon
786 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
789 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
790 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
793 /* Setup Bus Memory Interface */
794 static void sky2_qset(struct sky2_hw *hw, u16 q)
796 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
797 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
798 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
799 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
802 /* Setup prefetch unit registers. This is the interface between
803 * hardware and driver list elements
805 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
808 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
809 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
810 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
811 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
812 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
813 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
815 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
818 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
820 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
822 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
827 static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
828 struct sky2_tx_le *le)
830 return sky2->tx_ring + (le - sky2->tx_le);
833 /* Update chip's next pointer */
834 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
836 q = Y2_QADDR(q, PREF_UNIT_PUT_IDX);
838 sky2_write16(hw, q, idx);
843 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
845 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
846 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
851 /* Return high part of DMA address (could be 32 or 64 bit) */
852 static inline u32 high32(dma_addr_t a)
854 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
857 /* Build description to hardware for one receive segment */
858 static void sky2_rx_add(struct sky2_port *sky2, u8 op,
859 dma_addr_t map, unsigned len)
861 struct sky2_rx_le *le;
862 u32 hi = high32(map);
864 if (sky2->rx_addr64 != hi) {
865 le = sky2_next_rx(sky2);
866 le->addr = cpu_to_le32(hi);
867 le->opcode = OP_ADDR64 | HW_OWNER;
868 sky2->rx_addr64 = high32(map + len);
871 le = sky2_next_rx(sky2);
872 le->addr = cpu_to_le32((u32) map);
873 le->length = cpu_to_le16(len);
874 le->opcode = op | HW_OWNER;
877 /* Build description to hardware for one possibly fragmented skb */
878 static void sky2_rx_submit(struct sky2_port *sky2,
879 const struct rx_ring_info *re)
883 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
885 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
886 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
890 static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
893 struct sk_buff *skb = re->skb;
896 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
897 pci_unmap_len_set(re, data_size, size);
899 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
900 re->frag_addr[i] = pci_map_page(pdev,
901 skb_shinfo(skb)->frags[i].page,
902 skb_shinfo(skb)->frags[i].page_offset,
903 skb_shinfo(skb)->frags[i].size,
907 static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
909 struct sk_buff *skb = re->skb;
912 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
915 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
916 pci_unmap_page(pdev, re->frag_addr[i],
917 skb_shinfo(skb)->frags[i].size,
921 /* Tell chip where to start receive checksum.
922 * Actually has two checksums, but set both same to avoid possible byte
925 static void rx_set_checksum(struct sky2_port *sky2)
927 struct sky2_rx_le *le;
929 le = sky2_next_rx(sky2);
930 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
932 le->opcode = OP_TCPSTART | HW_OWNER;
934 sky2_write32(sky2->hw,
935 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
936 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
941 * The RX Stop command will not work for Yukon-2 if the BMU does not
942 * reach the end of packet and since we can't make sure that we have
943 * incoming data, we must reset the BMU while it is not doing a DMA
944 * transfer. Since it is possible that the RX path is still active,
945 * the RX RAM buffer will be stopped first, so any possible incoming
946 * data will not trigger a DMA. After the RAM buffer is stopped, the
947 * BMU is polled until any DMA in progress is ended and only then it
950 static void sky2_rx_stop(struct sky2_port *sky2)
952 struct sky2_hw *hw = sky2->hw;
953 unsigned rxq = rxqaddr[sky2->port];
956 /* disable the RAM Buffer receive queue */
957 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
959 for (i = 0; i < 0xffff; i++)
960 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
961 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
964 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
967 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
969 /* reset the Rx prefetch unit */
970 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
973 /* Clean out receive buffer area, assumes receiver hardware stopped */
974 static void sky2_rx_clean(struct sky2_port *sky2)
978 memset(sky2->rx_le, 0, RX_LE_BYTES);
979 for (i = 0; i < sky2->rx_pending; i++) {
980 struct rx_ring_info *re = sky2->rx_ring + i;
983 sky2_rx_unmap_skb(sky2->hw->pdev, re);
990 /* Basic MII support */
991 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
993 struct mii_ioctl_data *data = if_mii(ifr);
994 struct sky2_port *sky2 = netdev_priv(dev);
995 struct sky2_hw *hw = sky2->hw;
996 int err = -EOPNOTSUPP;
998 if (!netif_running(dev))
999 return -ENODEV; /* Phy still in reset */
1003 data->phy_id = PHY_ADDR_MARV;
1009 spin_lock_bh(&sky2->phy_lock);
1010 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
1011 spin_unlock_bh(&sky2->phy_lock);
1013 data->val_out = val;
1018 if (!capable(CAP_NET_ADMIN))
1021 spin_lock_bh(&sky2->phy_lock);
1022 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1024 spin_unlock_bh(&sky2->phy_lock);
1030 #ifdef SKY2_VLAN_TAG_USED
1031 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1033 struct sky2_port *sky2 = netdev_priv(dev);
1034 struct sky2_hw *hw = sky2->hw;
1035 u16 port = sky2->port;
1037 netif_tx_lock_bh(dev);
1039 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
1040 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
1043 netif_tx_unlock_bh(dev);
1046 static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
1048 struct sky2_port *sky2 = netdev_priv(dev);
1049 struct sky2_hw *hw = sky2->hw;
1050 u16 port = sky2->port;
1052 netif_tx_lock_bh(dev);
1054 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
1055 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
1057 sky2->vlgrp->vlan_devices[vid] = NULL;
1059 netif_tx_unlock_bh(dev);
1064 * Allocate an skb for receiving. If the MTU is large enough
1065 * make the skb non-linear with a fragment list of pages.
1067 * It appears the hardware has a bug in the FIFO logic that
1068 * cause it to hang if the FIFO gets overrun and the receive buffer
1069 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
1070 * aligned except if slab debugging is enabled.
1072 static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
1074 struct sk_buff *skb;
1078 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + RX_SKB_ALIGN);
1082 p = (unsigned long) skb->data;
1083 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
1085 for (i = 0; i < sky2->rx_nfrags; i++) {
1086 struct page *page = alloc_page(GFP_ATOMIC);
1090 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
1101 * Allocate and setup receiver buffer pool.
1102 * Normal case this ends up creating one list element for skb
1103 * in the receive ring. Worst case if using large MTU and each
1104 * allocation falls on a different 64 bit region, that results
1105 * in 6 list elements per ring entry.
1106 * One element is used for checksum enable/disable, and one
1107 * extra to avoid wrap.
1109 static int sky2_rx_start(struct sky2_port *sky2)
1111 struct sky2_hw *hw = sky2->hw;
1112 struct rx_ring_info *re;
1113 unsigned rxq = rxqaddr[sky2->port];
1114 unsigned i, size, space, thresh;
1116 sky2->rx_put = sky2->rx_next = 0;
1119 /* On PCI express lowering the watermark gives better performance */
1120 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1121 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1123 /* These chips have no ram buffer?
1124 * MAC Rx RAM Read is controlled by hardware */
1125 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1126 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1127 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
1128 sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
1130 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1132 rx_set_checksum(sky2);
1134 /* Space needed for frame data + headers rounded up */
1135 size = ALIGN(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8)
1138 /* Stopping point for hardware truncation */
1139 thresh = (size - 8) / sizeof(u32);
1141 /* Account for overhead of skb - to avoid order > 0 allocation */
1142 space = SKB_DATA_ALIGN(size) + NET_SKB_PAD
1143 + sizeof(struct skb_shared_info);
1145 sky2->rx_nfrags = space >> PAGE_SHIFT;
1146 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1148 if (sky2->rx_nfrags != 0) {
1149 /* Compute residue after pages */
1150 space = sky2->rx_nfrags << PAGE_SHIFT;
1157 /* Optimize to handle small packets and headers */
1158 if (size < copybreak)
1160 if (size < ETH_HLEN)
1163 sky2->rx_data_size = size;
1166 for (i = 0; i < sky2->rx_pending; i++) {
1167 re = sky2->rx_ring + i;
1169 re->skb = sky2_rx_alloc(sky2);
1173 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1174 sky2_rx_submit(sky2, re);
1178 * The receiver hangs if it receives frames larger than the
1179 * packet buffer. As a workaround, truncate oversize frames, but
1180 * the register is limited to 9 bits, so if you do frames > 2052
1181 * you better get the MTU right!
1184 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1186 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1187 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1190 /* Tell chip about available buffers */
1191 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
1194 sky2_rx_clean(sky2);
1198 /* Bring up network interface. */
1199 static int sky2_up(struct net_device *dev)
1201 struct sky2_port *sky2 = netdev_priv(dev);
1202 struct sky2_hw *hw = sky2->hw;
1203 unsigned port = sky2->port;
1205 int cap, err = -ENOMEM;
1206 struct net_device *otherdev = hw->dev[sky2->port^1];
1209 * On dual port PCI-X card, there is an problem where status
1210 * can be received out of order due to split transactions
1212 if (otherdev && netif_running(otherdev) &&
1213 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1214 struct sky2_port *osky2 = netdev_priv(otherdev);
1217 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1218 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1219 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1225 if (netif_msg_ifup(sky2))
1226 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1228 /* must be power of 2 */
1229 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1231 sizeof(struct sky2_tx_le),
1236 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
1240 sky2->tx_prod = sky2->tx_cons = 0;
1242 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1246 memset(sky2->rx_le, 0, RX_LE_BYTES);
1248 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1253 sky2_phy_power(hw, port, 1);
1255 sky2_mac_init(hw, port);
1257 /* Register is number of 4K blocks on internal RAM buffer. */
1258 ramsize = sky2_read8(hw, B2_E_0) * 4;
1259 printk(KERN_INFO PFX "%s: ram buffer %dK\n", dev->name, ramsize);
1265 rxspace = ramsize / 2;
1267 rxspace = 8 + (2*(ramsize - 16))/3;
1269 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1270 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1272 /* Make sure SyncQ is disabled */
1273 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1277 sky2_qset(hw, txqaddr[port]);
1279 /* Set almost empty threshold */
1280 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1281 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
1282 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
1284 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1287 err = sky2_rx_start(sky2);
1291 /* Enable interrupts from phy/mac for port */
1292 imask = sky2_read32(hw, B0_IMSK);
1293 imask |= portirq_msk[port];
1294 sky2_write32(hw, B0_IMSK, imask);
1300 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1301 sky2->rx_le, sky2->rx_le_map);
1305 pci_free_consistent(hw->pdev,
1306 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1307 sky2->tx_le, sky2->tx_le_map);
1310 kfree(sky2->tx_ring);
1311 kfree(sky2->rx_ring);
1313 sky2->tx_ring = NULL;
1314 sky2->rx_ring = NULL;
1318 /* Modular subtraction in ring */
1319 static inline int tx_dist(unsigned tail, unsigned head)
1321 return (head - tail) & (TX_RING_SIZE - 1);
1324 /* Number of list elements available for next tx */
1325 static inline int tx_avail(const struct sky2_port *sky2)
1327 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
1330 /* Estimate of number of transmit list elements required */
1331 static unsigned tx_le_req(const struct sk_buff *skb)
1335 count = sizeof(dma_addr_t) / sizeof(u32);
1336 count += skb_shinfo(skb)->nr_frags * count;
1338 if (skb_is_gso(skb))
1341 if (skb->ip_summed == CHECKSUM_PARTIAL)
1348 * Put one packet in ring for transmit.
1349 * A single packet can generate multiple list elements, and
1350 * the number of ring elements will probably be less than the number
1351 * of list elements used.
1353 static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1355 struct sky2_port *sky2 = netdev_priv(dev);
1356 struct sky2_hw *hw = sky2->hw;
1357 struct sky2_tx_le *le = NULL;
1358 struct tx_ring_info *re;
1365 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1366 return NETDEV_TX_BUSY;
1368 if (unlikely(netif_msg_tx_queued(sky2)))
1369 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1370 dev->name, sky2->tx_prod, skb->len);
1372 len = skb_headlen(skb);
1373 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1374 addr64 = high32(mapping);
1376 /* Send high bits if changed or crosses boundary */
1377 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
1378 le = get_tx_le(sky2);
1379 le->addr = cpu_to_le32(addr64);
1380 le->opcode = OP_ADDR64 | HW_OWNER;
1381 sky2->tx_addr64 = high32(mapping + len);
1384 /* Check for TCP Segmentation Offload */
1385 mss = skb_shinfo(skb)->gso_size;
1387 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1388 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1391 if (mss != sky2->tx_last_mss) {
1392 le = get_tx_le(sky2);
1393 le->addr = cpu_to_le32(mss);
1394 le->opcode = OP_LRGLEN | HW_OWNER;
1395 sky2->tx_last_mss = mss;
1400 #ifdef SKY2_VLAN_TAG_USED
1401 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1402 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1404 le = get_tx_le(sky2);
1406 le->opcode = OP_VLAN|HW_OWNER;
1408 le->opcode |= OP_VLAN;
1409 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1414 /* Handle TCP checksum offload */
1415 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1416 unsigned offset = skb->h.raw - skb->data;
1419 tcpsum = offset << 16; /* sum start */
1420 tcpsum |= offset + skb->csum_offset; /* sum write */
1422 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1423 if (skb->nh.iph->protocol == IPPROTO_UDP)
1426 if (tcpsum != sky2->tx_tcpsum) {
1427 sky2->tx_tcpsum = tcpsum;
1429 le = get_tx_le(sky2);
1430 le->addr = cpu_to_le32(tcpsum);
1431 le->length = 0; /* initial checksum value */
1432 le->ctrl = 1; /* one packet */
1433 le->opcode = OP_TCPLISW | HW_OWNER;
1437 le = get_tx_le(sky2);
1438 le->addr = cpu_to_le32((u32) mapping);
1439 le->length = cpu_to_le16(len);
1441 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1443 re = tx_le_re(sky2, le);
1445 pci_unmap_addr_set(re, mapaddr, mapping);
1446 pci_unmap_len_set(re, maplen, len);
1448 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1449 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1451 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1452 frag->size, PCI_DMA_TODEVICE);
1453 addr64 = high32(mapping);
1454 if (addr64 != sky2->tx_addr64) {
1455 le = get_tx_le(sky2);
1456 le->addr = cpu_to_le32(addr64);
1458 le->opcode = OP_ADDR64 | HW_OWNER;
1459 sky2->tx_addr64 = addr64;
1462 le = get_tx_le(sky2);
1463 le->addr = cpu_to_le32((u32) mapping);
1464 le->length = cpu_to_le16(frag->size);
1466 le->opcode = OP_BUFFER | HW_OWNER;
1468 re = tx_le_re(sky2, le);
1470 pci_unmap_addr_set(re, mapaddr, mapping);
1471 pci_unmap_len_set(re, maplen, frag->size);
1476 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1477 netif_stop_queue(dev);
1479 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1481 dev->trans_start = jiffies;
1482 return NETDEV_TX_OK;
1486 * Free ring elements from starting at tx_cons until "done"
1488 * NB: the hardware will tell us about partial completion of multi-part
1489 * buffers so make sure not to free skb to early.
1491 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1493 struct net_device *dev = sky2->netdev;
1494 struct pci_dev *pdev = sky2->hw->pdev;
1497 BUG_ON(done >= TX_RING_SIZE);
1499 for (idx = sky2->tx_cons; idx != done;
1500 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1501 struct sky2_tx_le *le = sky2->tx_le + idx;
1502 struct tx_ring_info *re = sky2->tx_ring + idx;
1504 switch(le->opcode & ~HW_OWNER) {
1507 pci_unmap_single(pdev,
1508 pci_unmap_addr(re, mapaddr),
1509 pci_unmap_len(re, maplen),
1513 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1514 pci_unmap_len(re, maplen),
1519 if (le->ctrl & EOP) {
1520 if (unlikely(netif_msg_tx_done(sky2)))
1521 printk(KERN_DEBUG "%s: tx done %u\n",
1523 sky2->net_stats.tx_packets++;
1524 sky2->net_stats.tx_bytes += re->skb->len;
1526 dev_kfree_skb_any(re->skb);
1529 le->opcode = 0; /* paranoia */
1532 sky2->tx_cons = idx;
1533 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
1534 netif_wake_queue(dev);
1537 /* Cleanup all untransmitted buffers, assume transmitter not running */
1538 static void sky2_tx_clean(struct net_device *dev)
1540 struct sky2_port *sky2 = netdev_priv(dev);
1542 netif_tx_lock_bh(dev);
1543 sky2_tx_complete(sky2, sky2->tx_prod);
1544 netif_tx_unlock_bh(dev);
1547 /* Network shutdown */
1548 static int sky2_down(struct net_device *dev)
1550 struct sky2_port *sky2 = netdev_priv(dev);
1551 struct sky2_hw *hw = sky2->hw;
1552 unsigned port = sky2->port;
1556 /* Never really got started! */
1560 if (netif_msg_ifdown(sky2))
1561 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1563 /* Stop more packets from being queued */
1564 netif_stop_queue(dev);
1566 /* Disable port IRQ */
1567 imask = sky2_read32(hw, B0_IMSK);
1568 imask &= ~portirq_msk[port];
1569 sky2_write32(hw, B0_IMSK, imask);
1572 * Both ports share the NAPI poll on port 0, so if necessary undo the
1573 * the disable that is done in dev_close.
1575 if (sky2->port == 0 && hw->ports > 1)
1576 netif_poll_enable(dev);
1578 sky2_gmac_reset(hw, port);
1580 /* Stop transmitter */
1581 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1582 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1584 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1585 RB_RST_SET | RB_DIS_OP_MD);
1587 /* WA for dev. #4.209 */
1588 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1589 && (hw->chip_rev == CHIP_REV_YU_EC_U_A1 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
1590 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1591 sky2->speed != SPEED_1000 ?
1592 TX_STFW_ENA : TX_STFW_DIS);
1594 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1595 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1596 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1598 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1600 /* Workaround shared GMAC reset */
1601 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1602 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1603 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1605 /* Disable Force Sync bit and Enable Alloc bit */
1606 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1607 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1609 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1610 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1611 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1613 /* Reset the PCI FIFO of the async Tx queue */
1614 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1615 BMU_RST_SET | BMU_FIFO_RST);
1617 /* Reset the Tx prefetch units */
1618 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1621 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1625 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1626 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1628 sky2_phy_power(hw, port, 0);
1630 /* turn off LED's */
1631 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1633 synchronize_irq(hw->pdev->irq);
1636 sky2_rx_clean(sky2);
1638 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1639 sky2->rx_le, sky2->rx_le_map);
1640 kfree(sky2->rx_ring);
1642 pci_free_consistent(hw->pdev,
1643 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1644 sky2->tx_le, sky2->tx_le_map);
1645 kfree(sky2->tx_ring);
1650 sky2->rx_ring = NULL;
1651 sky2->tx_ring = NULL;
1656 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1658 if (!sky2_is_copper(hw))
1661 if (hw->chip_id == CHIP_ID_YUKON_FE)
1662 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1664 switch (aux & PHY_M_PS_SPEED_MSK) {
1665 case PHY_M_PS_SPEED_1000:
1667 case PHY_M_PS_SPEED_100:
1674 static void sky2_link_up(struct sky2_port *sky2)
1676 struct sky2_hw *hw = sky2->hw;
1677 unsigned port = sky2->port;
1679 static const char *fc_name[] = {
1687 reg = gma_read16(hw, port, GM_GP_CTRL);
1688 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1689 gma_write16(hw, port, GM_GP_CTRL, reg);
1691 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1693 netif_carrier_on(sky2->netdev);
1694 netif_wake_queue(sky2->netdev);
1696 /* Turn on link LED */
1697 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1698 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1700 if (hw->chip_id == CHIP_ID_YUKON_XL
1701 || hw->chip_id == CHIP_ID_YUKON_EC_U
1702 || hw->chip_id == CHIP_ID_YUKON_EX) {
1703 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
1704 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
1706 switch(sky2->speed) {
1708 led |= PHY_M_LEDC_INIT_CTRL(7);
1712 led |= PHY_M_LEDC_STA1_CTRL(7);
1716 led |= PHY_M_LEDC_STA0_CTRL(7);
1720 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
1721 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
1722 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1725 if (netif_msg_link(sky2))
1726 printk(KERN_INFO PFX
1727 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1728 sky2->netdev->name, sky2->speed,
1729 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1730 fc_name[sky2->flow_status]);
1733 static void sky2_link_down(struct sky2_port *sky2)
1735 struct sky2_hw *hw = sky2->hw;
1736 unsigned port = sky2->port;
1739 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1741 reg = gma_read16(hw, port, GM_GP_CTRL);
1742 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1743 gma_write16(hw, port, GM_GP_CTRL, reg);
1745 netif_carrier_off(sky2->netdev);
1746 netif_stop_queue(sky2->netdev);
1748 /* Turn on link LED */
1749 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1751 if (netif_msg_link(sky2))
1752 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1754 sky2_phy_init(hw, port);
1757 static enum flow_control sky2_flow(int rx, int tx)
1760 return tx ? FC_BOTH : FC_RX;
1762 return tx ? FC_TX : FC_NONE;
1765 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1767 struct sky2_hw *hw = sky2->hw;
1768 unsigned port = sky2->port;
1771 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1773 if (lpa & PHY_M_AN_RF) {
1774 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1778 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1779 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1780 sky2->netdev->name);
1784 sky2->speed = sky2_phy_speed(hw, aux);
1785 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1787 /* Pause bits are offset (9..8) */
1788 if (hw->chip_id == CHIP_ID_YUKON_XL
1789 || hw->chip_id == CHIP_ID_YUKON_EC_U
1790 || hw->chip_id == CHIP_ID_YUKON_EX)
1793 sky2->flow_status = sky2_flow(aux & PHY_M_PS_RX_P_EN,
1794 aux & PHY_M_PS_TX_P_EN);
1796 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
1797 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
1798 sky2->flow_status = FC_NONE;
1800 if (aux & PHY_M_PS_RX_P_EN)
1801 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1803 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1808 /* Interrupt from PHY */
1809 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
1811 struct net_device *dev = hw->dev[port];
1812 struct sky2_port *sky2 = netdev_priv(dev);
1813 u16 istatus, phystat;
1815 if (!netif_running(dev))
1818 spin_lock(&sky2->phy_lock);
1819 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1820 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1822 if (netif_msg_intr(sky2))
1823 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1824 sky2->netdev->name, istatus, phystat);
1826 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
1827 if (sky2_autoneg_done(sky2, phystat) == 0)
1832 if (istatus & PHY_M_IS_LSP_CHANGE)
1833 sky2->speed = sky2_phy_speed(hw, phystat);
1835 if (istatus & PHY_M_IS_DUP_CHANGE)
1837 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1839 if (istatus & PHY_M_IS_LST_CHANGE) {
1840 if (phystat & PHY_M_PS_LINK_UP)
1843 sky2_link_down(sky2);
1846 spin_unlock(&sky2->phy_lock);
1850 /* Transmit timeout is only called if we are running, carrier is up
1851 * and tx queue is full (stopped).
1852 * Called with netif_tx_lock held.
1854 static void sky2_tx_timeout(struct net_device *dev)
1856 struct sky2_port *sky2 = netdev_priv(dev);
1857 struct sky2_hw *hw = sky2->hw;
1860 if (netif_msg_timer(sky2))
1861 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1863 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
1864 dev->name, sky2->tx_cons, sky2->tx_prod,
1865 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
1866 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
1868 imask = sky2_read32(hw, B0_IMSK); /* block IRQ in hw */
1869 sky2_write32(hw, B0_IMSK, 0);
1870 sky2_read32(hw, B0_IMSK);
1872 netif_poll_disable(hw->dev[0]); /* stop NAPI poll */
1873 synchronize_irq(hw->pdev->irq);
1875 netif_start_queue(dev); /* don't wakeup during flush */
1876 sky2_tx_complete(sky2, sky2->tx_prod); /* Flush transmit queue */
1878 sky2_write32(hw, B0_IMSK, imask);
1880 sky2_phy_reinit(sky2); /* this clears flow control etc */
1883 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1885 struct sky2_port *sky2 = netdev_priv(dev);
1886 struct sky2_hw *hw = sky2->hw;
1891 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1894 /* TSO on Yukon Ultra and MTU > 1500 not supported */
1895 if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
1896 dev->features &= ~NETIF_F_TSO;
1898 if (!netif_running(dev)) {
1903 imask = sky2_read32(hw, B0_IMSK);
1904 sky2_write32(hw, B0_IMSK, 0);
1906 dev->trans_start = jiffies; /* prevent tx timeout */
1907 netif_stop_queue(dev);
1908 netif_poll_disable(hw->dev[0]);
1910 synchronize_irq(hw->pdev->irq);
1912 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1913 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1915 sky2_rx_clean(sky2);
1919 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1920 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1922 if (dev->mtu > ETH_DATA_LEN)
1923 mode |= GM_SMOD_JUMBO_ENA;
1925 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
1927 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
1929 err = sky2_rx_start(sky2);
1930 sky2_write32(hw, B0_IMSK, imask);
1935 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1937 netif_poll_enable(hw->dev[0]);
1938 netif_wake_queue(dev);
1944 /* For small just reuse existing skb for next receive */
1945 static struct sk_buff *receive_copy(struct sky2_port *sky2,
1946 const struct rx_ring_info *re,
1949 struct sk_buff *skb;
1951 skb = netdev_alloc_skb(sky2->netdev, length + 2);
1953 skb_reserve(skb, 2);
1954 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
1955 length, PCI_DMA_FROMDEVICE);
1956 memcpy(skb->data, re->skb->data, length);
1957 skb->ip_summed = re->skb->ip_summed;
1958 skb->csum = re->skb->csum;
1959 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
1960 length, PCI_DMA_FROMDEVICE);
1961 re->skb->ip_summed = CHECKSUM_NONE;
1962 skb_put(skb, length);
1967 /* Adjust length of skb with fragments to match received data */
1968 static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
1969 unsigned int length)
1974 /* put header into skb */
1975 size = min(length, hdr_space);
1980 num_frags = skb_shinfo(skb)->nr_frags;
1981 for (i = 0; i < num_frags; i++) {
1982 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1985 /* don't need this page */
1986 __free_page(frag->page);
1987 --skb_shinfo(skb)->nr_frags;
1989 size = min(length, (unsigned) PAGE_SIZE);
1992 skb->data_len += size;
1993 skb->truesize += size;
2000 /* Normal packet - take skb from ring element and put in a new one */
2001 static struct sk_buff *receive_new(struct sky2_port *sky2,
2002 struct rx_ring_info *re,
2003 unsigned int length)
2005 struct sk_buff *skb, *nskb;
2006 unsigned hdr_space = sky2->rx_data_size;
2008 pr_debug(PFX "receive new length=%d\n", length);
2010 /* Don't be tricky about reusing pages (yet) */
2011 nskb = sky2_rx_alloc(sky2);
2012 if (unlikely(!nskb))
2016 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2018 prefetch(skb->data);
2020 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
2022 if (skb_shinfo(skb)->nr_frags)
2023 skb_put_frags(skb, hdr_space, length);
2025 skb_put(skb, length);
2030 * Receive one packet.
2031 * For larger packets, get new buffer.
2033 static struct sk_buff *sky2_receive(struct net_device *dev,
2034 u16 length, u32 status)
2036 struct sky2_port *sky2 = netdev_priv(dev);
2037 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
2038 struct sk_buff *skb = NULL;
2040 if (unlikely(netif_msg_rx_status(sky2)))
2041 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
2042 dev->name, sky2->rx_next, status, length);
2044 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
2045 prefetch(sky2->rx_ring + sky2->rx_next);
2047 if (status & GMR_FS_ANY_ERR)
2050 if (!(status & GMR_FS_RX_OK))
2053 if (length > dev->mtu + ETH_HLEN)
2056 if (length < copybreak)
2057 skb = receive_copy(sky2, re, length);
2059 skb = receive_new(sky2, re, length);
2061 sky2_rx_submit(sky2, re);
2066 ++sky2->net_stats.rx_over_errors;
2070 ++sky2->net_stats.rx_errors;
2071 if (status & GMR_FS_RX_FF_OV) {
2072 sky2->net_stats.rx_fifo_errors++;
2076 if (netif_msg_rx_err(sky2) && net_ratelimit())
2077 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
2078 dev->name, status, length);
2080 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
2081 sky2->net_stats.rx_length_errors++;
2082 if (status & GMR_FS_FRAGMENT)
2083 sky2->net_stats.rx_frame_errors++;
2084 if (status & GMR_FS_CRC_ERR)
2085 sky2->net_stats.rx_crc_errors++;
2090 /* Transmit complete */
2091 static inline void sky2_tx_done(struct net_device *dev, u16 last)
2093 struct sky2_port *sky2 = netdev_priv(dev);
2095 if (netif_running(dev)) {
2097 sky2_tx_complete(sky2, last);
2098 netif_tx_unlock(dev);
2102 /* Process status response ring */
2103 static int sky2_status_intr(struct sky2_hw *hw, int to_do)
2105 struct sky2_port *sky2;
2107 unsigned buf_write[2] = { 0, 0 };
2108 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
2112 while (hw->st_idx != hwidx) {
2113 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2114 struct net_device *dev;
2115 struct sk_buff *skb;
2119 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
2121 BUG_ON(le->link >= 2);
2122 dev = hw->dev[le->link];
2124 sky2 = netdev_priv(dev);
2125 length = le16_to_cpu(le->length);
2126 status = le32_to_cpu(le->status);
2128 switch (le->opcode & ~HW_OWNER) {
2130 skb = sky2_receive(dev, length, status);
2134 skb->protocol = eth_type_trans(skb, dev);
2135 sky2->net_stats.rx_packets++;
2136 sky2->net_stats.rx_bytes += skb->len;
2137 dev->last_rx = jiffies;
2139 #ifdef SKY2_VLAN_TAG_USED
2140 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2141 vlan_hwaccel_receive_skb(skb,
2143 be16_to_cpu(sky2->rx_tag));
2146 netif_receive_skb(skb);
2148 /* Update receiver after 16 frames */
2149 if (++buf_write[le->link] == RX_BUF_WRITE) {
2151 sky2_put_idx(hw, rxqaddr[le->link], sky2->rx_put);
2152 buf_write[le->link] = 0;
2155 /* Stop after net poll weight */
2156 if (++work_done >= to_do)
2160 #ifdef SKY2_VLAN_TAG_USED
2162 sky2->rx_tag = length;
2166 sky2->rx_tag = length;
2170 skb = sky2->rx_ring[sky2->rx_next].skb;
2171 skb->ip_summed = CHECKSUM_COMPLETE;
2172 skb->csum = status & 0xffff;
2176 /* TX index reports status for both ports */
2177 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2178 sky2_tx_done(hw->dev[0], status & 0xfff);
2180 sky2_tx_done(hw->dev[1],
2181 ((status >> 24) & 0xff)
2182 | (u16)(length & 0xf) << 8);
2186 if (net_ratelimit())
2187 printk(KERN_WARNING PFX
2188 "unknown status opcode 0x%x\n", le->opcode);
2193 /* Fully processed status ring so clear irq */
2194 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2198 sky2 = netdev_priv(hw->dev[0]);
2199 sky2_put_idx(hw, Q_R1, sky2->rx_put);
2203 sky2 = netdev_priv(hw->dev[1]);
2204 sky2_put_idx(hw, Q_R2, sky2->rx_put);
2210 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2212 struct net_device *dev = hw->dev[port];
2214 if (net_ratelimit())
2215 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2218 if (status & Y2_IS_PAR_RD1) {
2219 if (net_ratelimit())
2220 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2223 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2226 if (status & Y2_IS_PAR_WR1) {
2227 if (net_ratelimit())
2228 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2231 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2234 if (status & Y2_IS_PAR_MAC1) {
2235 if (net_ratelimit())
2236 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
2237 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2240 if (status & Y2_IS_PAR_RX1) {
2241 if (net_ratelimit())
2242 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
2243 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2246 if (status & Y2_IS_TCP_TXA1) {
2247 if (net_ratelimit())
2248 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2250 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2254 static void sky2_hw_intr(struct sky2_hw *hw)
2256 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2258 if (status & Y2_IS_TIST_OV)
2259 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2261 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2264 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2265 if (net_ratelimit())
2266 dev_err(&hw->pdev->dev, "PCI hardware error (0x%x)\n",
2269 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2270 sky2_pci_write16(hw, PCI_STATUS,
2271 pci_err | PCI_STATUS_ERROR_BITS);
2272 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2275 if (status & Y2_IS_PCI_EXP) {
2276 /* PCI-Express uncorrectable Error occurred */
2279 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
2281 if (net_ratelimit())
2282 dev_err(&hw->pdev->dev, "PCI Express error (0x%x)\n",
2285 /* clear the interrupt */
2286 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2287 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
2289 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2291 if (pex_err & PEX_FATAL_ERRORS) {
2292 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2293 hwmsk &= ~Y2_IS_PCI_EXP;
2294 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2298 if (status & Y2_HWE_L1_MASK)
2299 sky2_hw_error(hw, 0, status);
2301 if (status & Y2_HWE_L1_MASK)
2302 sky2_hw_error(hw, 1, status);
2305 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2307 struct net_device *dev = hw->dev[port];
2308 struct sky2_port *sky2 = netdev_priv(dev);
2309 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2311 if (netif_msg_intr(sky2))
2312 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2315 if (status & GM_IS_RX_FF_OR) {
2316 ++sky2->net_stats.rx_fifo_errors;
2317 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2320 if (status & GM_IS_TX_FF_UR) {
2321 ++sky2->net_stats.tx_fifo_errors;
2322 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2326 /* This should never happen it is a fatal situation */
2327 static void sky2_descriptor_error(struct sky2_hw *hw, unsigned port,
2328 const char *rxtx, u32 mask)
2330 struct net_device *dev = hw->dev[port];
2331 struct sky2_port *sky2 = netdev_priv(dev);
2334 printk(KERN_ERR PFX "%s: %s descriptor error (hardware problem)\n",
2335 dev ? dev->name : "<not registered>", rxtx);
2337 imask = sky2_read32(hw, B0_IMSK);
2339 sky2_write32(hw, B0_IMSK, imask);
2342 spin_lock(&sky2->phy_lock);
2343 sky2_link_down(sky2);
2344 spin_unlock(&sky2->phy_lock);
2348 /* If idle then force a fake soft NAPI poll once a second
2349 * to work around cases where sharing an edge triggered interrupt.
2351 static inline void sky2_idle_start(struct sky2_hw *hw)
2353 if (idle_timeout > 0)
2354 mod_timer(&hw->idle_timer,
2355 jiffies + msecs_to_jiffies(idle_timeout));
2358 static void sky2_idle(unsigned long arg)
2360 struct sky2_hw *hw = (struct sky2_hw *) arg;
2361 struct net_device *dev = hw->dev[0];
2363 if (__netif_rx_schedule_prep(dev))
2364 __netif_rx_schedule(dev);
2366 mod_timer(&hw->idle_timer, jiffies + msecs_to_jiffies(idle_timeout));
2370 static int sky2_poll(struct net_device *dev0, int *budget)
2372 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
2373 int work_limit = min(dev0->quota, *budget);
2375 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2377 if (status & Y2_IS_HW_ERR)
2380 if (status & Y2_IS_IRQ_PHY1)
2381 sky2_phy_intr(hw, 0);
2383 if (status & Y2_IS_IRQ_PHY2)
2384 sky2_phy_intr(hw, 1);
2386 if (status & Y2_IS_IRQ_MAC1)
2387 sky2_mac_intr(hw, 0);
2389 if (status & Y2_IS_IRQ_MAC2)
2390 sky2_mac_intr(hw, 1);
2392 if (status & Y2_IS_CHK_RX1)
2393 sky2_descriptor_error(hw, 0, "receive", Y2_IS_CHK_RX1);
2395 if (status & Y2_IS_CHK_RX2)
2396 sky2_descriptor_error(hw, 1, "receive", Y2_IS_CHK_RX2);
2398 if (status & Y2_IS_CHK_TXA1)
2399 sky2_descriptor_error(hw, 0, "transmit", Y2_IS_CHK_TXA1);
2401 if (status & Y2_IS_CHK_TXA2)
2402 sky2_descriptor_error(hw, 1, "transmit", Y2_IS_CHK_TXA2);
2404 work_done = sky2_status_intr(hw, work_limit);
2405 if (work_done < work_limit) {
2406 netif_rx_complete(dev0);
2408 sky2_read32(hw, B0_Y2_SP_LISR);
2411 *budget -= work_done;
2412 dev0->quota -= work_done;
2417 static irqreturn_t sky2_intr(int irq, void *dev_id)
2419 struct sky2_hw *hw = dev_id;
2420 struct net_device *dev0 = hw->dev[0];
2423 /* Reading this mask interrupts as side effect */
2424 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2425 if (status == 0 || status == ~0)
2428 prefetch(&hw->st_le[hw->st_idx]);
2429 if (likely(__netif_rx_schedule_prep(dev0)))
2430 __netif_rx_schedule(dev0);
2435 #ifdef CONFIG_NET_POLL_CONTROLLER
2436 static void sky2_netpoll(struct net_device *dev)
2438 struct sky2_port *sky2 = netdev_priv(dev);
2439 struct net_device *dev0 = sky2->hw->dev[0];
2441 if (netif_running(dev) && __netif_rx_schedule_prep(dev0))
2442 __netif_rx_schedule(dev0);
2446 /* Chip internal frequency for clock calculations */
2447 static inline u32 sky2_mhz(const struct sky2_hw *hw)
2449 switch (hw->chip_id) {
2450 case CHIP_ID_YUKON_EC:
2451 case CHIP_ID_YUKON_EC_U:
2452 case CHIP_ID_YUKON_EX:
2453 return 125; /* 125 Mhz */
2454 case CHIP_ID_YUKON_FE:
2455 return 100; /* 100 Mhz */
2456 default: /* YUKON_XL */
2457 return 156; /* 156 Mhz */
2461 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2463 return sky2_mhz(hw) * us;
2466 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2468 return clk / sky2_mhz(hw);
2472 static int __devinit sky2_init(struct sky2_hw *hw)
2476 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2478 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2479 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
2480 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2485 if (hw->chip_id == CHIP_ID_YUKON_EX)
2486 dev_warn(&hw->pdev->dev, "this driver not yet tested on this chip type\n"
2487 "Please report success or failure to <netdev@vger.kernel.org>\n");
2489 /* Make sure and enable all clocks */
2490 if (hw->chip_id == CHIP_ID_YUKON_EX || hw->chip_id == CHIP_ID_YUKON_EC_U)
2491 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
2493 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2495 /* This rev is really old, and requires untested workarounds */
2496 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
2497 dev_err(&hw->pdev->dev, "unsupported revision Yukon-%s (0x%x) rev %d\n",
2498 yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
2499 hw->chip_id, hw->chip_rev);
2503 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2505 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2506 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2507 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2514 static void sky2_reset(struct sky2_hw *hw)
2520 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
2521 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2522 status = sky2_read16(hw, HCU_CCSR);
2523 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2524 HCU_CCSR_UC_STATE_MSK);
2525 sky2_write16(hw, HCU_CCSR, status);
2527 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2528 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2532 sky2_write8(hw, B0_CTST, CS_RST_SET);
2533 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2535 /* clear PCI errors, if any */
2536 status = sky2_pci_read16(hw, PCI_STATUS);
2538 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2539 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2542 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2544 /* clear any PEX errors */
2545 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
2546 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2551 for (i = 0; i < hw->ports; i++) {
2552 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2553 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2556 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2558 /* Clear I2C IRQ noise */
2559 sky2_write32(hw, B2_I2C_IRQ, 1);
2561 /* turn off hardware timer (unused) */
2562 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2563 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2565 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2567 /* Turn off descriptor polling */
2568 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
2570 /* Turn off receive timestamp */
2571 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
2572 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2574 /* enable the Tx Arbiters */
2575 for (i = 0; i < hw->ports; i++)
2576 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2578 /* Initialize ram interface */
2579 for (i = 0; i < hw->ports; i++) {
2580 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
2582 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2583 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2584 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2585 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2586 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2587 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2588 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2589 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2590 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2591 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2592 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2593 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2596 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
2598 for (i = 0; i < hw->ports; i++)
2599 sky2_gmac_reset(hw, i);
2601 memset(hw->st_le, 0, STATUS_LE_BYTES);
2604 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2605 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2607 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
2608 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
2610 /* Set the list last index */
2611 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
2613 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2614 sky2_write8(hw, STAT_FIFO_WM, 16);
2616 /* set Status-FIFO ISR watermark */
2617 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2618 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2620 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
2622 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
2623 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2624 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
2626 /* enable status unit */
2627 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2629 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2630 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2631 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2634 static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
2636 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
2639 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2641 const struct sky2_port *sky2 = netdev_priv(dev);
2643 wol->supported = sky2_wol_supported(sky2->hw);
2644 wol->wolopts = sky2->wol;
2647 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2649 struct sky2_port *sky2 = netdev_priv(dev);
2650 struct sky2_hw *hw = sky2->hw;
2652 if (wol->wolopts & ~sky2_wol_supported(sky2->hw))
2655 sky2->wol = wol->wolopts;
2657 if (hw->chip_id == CHIP_ID_YUKON_EC_U)
2658 sky2_write32(hw, B0_CTST, sky2->wol
2659 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
2661 if (!netif_running(dev))
2662 sky2_wol_init(sky2);
2666 static u32 sky2_supported_modes(const struct sky2_hw *hw)
2668 if (sky2_is_copper(hw)) {
2669 u32 modes = SUPPORTED_10baseT_Half
2670 | SUPPORTED_10baseT_Full
2671 | SUPPORTED_100baseT_Half
2672 | SUPPORTED_100baseT_Full
2673 | SUPPORTED_Autoneg | SUPPORTED_TP;
2675 if (hw->chip_id != CHIP_ID_YUKON_FE)
2676 modes |= SUPPORTED_1000baseT_Half
2677 | SUPPORTED_1000baseT_Full;
2680 return SUPPORTED_1000baseT_Half
2681 | SUPPORTED_1000baseT_Full
2686 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2688 struct sky2_port *sky2 = netdev_priv(dev);
2689 struct sky2_hw *hw = sky2->hw;
2691 ecmd->transceiver = XCVR_INTERNAL;
2692 ecmd->supported = sky2_supported_modes(hw);
2693 ecmd->phy_address = PHY_ADDR_MARV;
2694 if (sky2_is_copper(hw)) {
2695 ecmd->supported = SUPPORTED_10baseT_Half
2696 | SUPPORTED_10baseT_Full
2697 | SUPPORTED_100baseT_Half
2698 | SUPPORTED_100baseT_Full
2699 | SUPPORTED_1000baseT_Half
2700 | SUPPORTED_1000baseT_Full
2701 | SUPPORTED_Autoneg | SUPPORTED_TP;
2702 ecmd->port = PORT_TP;
2703 ecmd->speed = sky2->speed;
2705 ecmd->speed = SPEED_1000;
2706 ecmd->port = PORT_FIBRE;
2709 ecmd->advertising = sky2->advertising;
2710 ecmd->autoneg = sky2->autoneg;
2711 ecmd->duplex = sky2->duplex;
2715 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2717 struct sky2_port *sky2 = netdev_priv(dev);
2718 const struct sky2_hw *hw = sky2->hw;
2719 u32 supported = sky2_supported_modes(hw);
2721 if (ecmd->autoneg == AUTONEG_ENABLE) {
2722 ecmd->advertising = supported;
2728 switch (ecmd->speed) {
2730 if (ecmd->duplex == DUPLEX_FULL)
2731 setting = SUPPORTED_1000baseT_Full;
2732 else if (ecmd->duplex == DUPLEX_HALF)
2733 setting = SUPPORTED_1000baseT_Half;
2738 if (ecmd->duplex == DUPLEX_FULL)
2739 setting = SUPPORTED_100baseT_Full;
2740 else if (ecmd->duplex == DUPLEX_HALF)
2741 setting = SUPPORTED_100baseT_Half;
2747 if (ecmd->duplex == DUPLEX_FULL)
2748 setting = SUPPORTED_10baseT_Full;
2749 else if (ecmd->duplex == DUPLEX_HALF)
2750 setting = SUPPORTED_10baseT_Half;
2758 if ((setting & supported) == 0)
2761 sky2->speed = ecmd->speed;
2762 sky2->duplex = ecmd->duplex;
2765 sky2->autoneg = ecmd->autoneg;
2766 sky2->advertising = ecmd->advertising;
2768 if (netif_running(dev))
2769 sky2_phy_reinit(sky2);
2774 static void sky2_get_drvinfo(struct net_device *dev,
2775 struct ethtool_drvinfo *info)
2777 struct sky2_port *sky2 = netdev_priv(dev);
2779 strcpy(info->driver, DRV_NAME);
2780 strcpy(info->version, DRV_VERSION);
2781 strcpy(info->fw_version, "N/A");
2782 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2785 static const struct sky2_stat {
2786 char name[ETH_GSTRING_LEN];
2789 { "tx_bytes", GM_TXO_OK_HI },
2790 { "rx_bytes", GM_RXO_OK_HI },
2791 { "tx_broadcast", GM_TXF_BC_OK },
2792 { "rx_broadcast", GM_RXF_BC_OK },
2793 { "tx_multicast", GM_TXF_MC_OK },
2794 { "rx_multicast", GM_RXF_MC_OK },
2795 { "tx_unicast", GM_TXF_UC_OK },
2796 { "rx_unicast", GM_RXF_UC_OK },
2797 { "tx_mac_pause", GM_TXF_MPAUSE },
2798 { "rx_mac_pause", GM_RXF_MPAUSE },
2799 { "collisions", GM_TXF_COL },
2800 { "late_collision",GM_TXF_LAT_COL },
2801 { "aborted", GM_TXF_ABO_COL },
2802 { "single_collisions", GM_TXF_SNG_COL },
2803 { "multi_collisions", GM_TXF_MUL_COL },
2805 { "rx_short", GM_RXF_SHT },
2806 { "rx_runt", GM_RXE_FRAG },
2807 { "rx_64_byte_packets", GM_RXF_64B },
2808 { "rx_65_to_127_byte_packets", GM_RXF_127B },
2809 { "rx_128_to_255_byte_packets", GM_RXF_255B },
2810 { "rx_256_to_511_byte_packets", GM_RXF_511B },
2811 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
2812 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
2813 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
2814 { "rx_too_long", GM_RXF_LNG_ERR },
2815 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
2816 { "rx_jabber", GM_RXF_JAB_PKT },
2817 { "rx_fcs_error", GM_RXF_FCS_ERR },
2819 { "tx_64_byte_packets", GM_TXF_64B },
2820 { "tx_65_to_127_byte_packets", GM_TXF_127B },
2821 { "tx_128_to_255_byte_packets", GM_TXF_255B },
2822 { "tx_256_to_511_byte_packets", GM_TXF_511B },
2823 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
2824 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
2825 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
2826 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
2829 static u32 sky2_get_rx_csum(struct net_device *dev)
2831 struct sky2_port *sky2 = netdev_priv(dev);
2833 return sky2->rx_csum;
2836 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2838 struct sky2_port *sky2 = netdev_priv(dev);
2840 sky2->rx_csum = data;
2842 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2843 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2848 static u32 sky2_get_msglevel(struct net_device *netdev)
2850 struct sky2_port *sky2 = netdev_priv(netdev);
2851 return sky2->msg_enable;
2854 static int sky2_nway_reset(struct net_device *dev)
2856 struct sky2_port *sky2 = netdev_priv(dev);
2858 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
2861 sky2_phy_reinit(sky2);
2866 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
2868 struct sky2_hw *hw = sky2->hw;
2869 unsigned port = sky2->port;
2872 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2873 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
2874 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2875 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
2877 for (i = 2; i < count; i++)
2878 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2881 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2883 struct sky2_port *sky2 = netdev_priv(netdev);
2884 sky2->msg_enable = value;
2887 static int sky2_get_stats_count(struct net_device *dev)
2889 return ARRAY_SIZE(sky2_stats);
2892 static void sky2_get_ethtool_stats(struct net_device *dev,
2893 struct ethtool_stats *stats, u64 * data)
2895 struct sky2_port *sky2 = netdev_priv(dev);
2897 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
2900 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
2904 switch (stringset) {
2906 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2907 memcpy(data + i * ETH_GSTRING_LEN,
2908 sky2_stats[i].name, ETH_GSTRING_LEN);
2913 static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2915 struct sky2_port *sky2 = netdev_priv(dev);
2916 return &sky2->net_stats;
2919 static int sky2_set_mac_address(struct net_device *dev, void *p)
2921 struct sky2_port *sky2 = netdev_priv(dev);
2922 struct sky2_hw *hw = sky2->hw;
2923 unsigned port = sky2->port;
2924 const struct sockaddr *addr = p;
2926 if (!is_valid_ether_addr(addr->sa_data))
2927 return -EADDRNOTAVAIL;
2929 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
2930 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
2931 dev->dev_addr, ETH_ALEN);
2932 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
2933 dev->dev_addr, ETH_ALEN);
2935 /* virtual address for data */
2936 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
2938 /* physical address: used for pause frames */
2939 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
2944 static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
2948 bit = ether_crc(ETH_ALEN, addr) & 63;
2949 filter[bit >> 3] |= 1 << (bit & 7);
2952 static void sky2_set_multicast(struct net_device *dev)
2954 struct sky2_port *sky2 = netdev_priv(dev);
2955 struct sky2_hw *hw = sky2->hw;
2956 unsigned port = sky2->port;
2957 struct dev_mc_list *list = dev->mc_list;
2961 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
2963 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
2964 memset(filter, 0, sizeof(filter));
2966 reg = gma_read16(hw, port, GM_RX_CTRL);
2967 reg |= GM_RXCR_UCF_ENA;
2969 if (dev->flags & IFF_PROMISC) /* promiscuous */
2970 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2971 else if (dev->flags & IFF_ALLMULTI)
2972 memset(filter, 0xff, sizeof(filter));
2973 else if (dev->mc_count == 0 && !rx_pause)
2974 reg &= ~GM_RXCR_MCF_ENA;
2977 reg |= GM_RXCR_MCF_ENA;
2980 sky2_add_filter(filter, pause_mc_addr);
2982 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
2983 sky2_add_filter(filter, list->dmi_addr);
2986 gma_write16(hw, port, GM_MC_ADDR_H1,
2987 (u16) filter[0] | ((u16) filter[1] << 8));
2988 gma_write16(hw, port, GM_MC_ADDR_H2,
2989 (u16) filter[2] | ((u16) filter[3] << 8));
2990 gma_write16(hw, port, GM_MC_ADDR_H3,
2991 (u16) filter[4] | ((u16) filter[5] << 8));
2992 gma_write16(hw, port, GM_MC_ADDR_H4,
2993 (u16) filter[6] | ((u16) filter[7] << 8));
2995 gma_write16(hw, port, GM_RX_CTRL, reg);
2998 /* Can have one global because blinking is controlled by
2999 * ethtool and that is always under RTNL mutex
3001 static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
3005 switch (hw->chip_id) {
3006 case CHIP_ID_YUKON_XL:
3007 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3008 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3009 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3010 on ? (PHY_M_LEDC_LOS_CTRL(1) |
3011 PHY_M_LEDC_INIT_CTRL(7) |
3012 PHY_M_LEDC_STA1_CTRL(7) |
3013 PHY_M_LEDC_STA0_CTRL(7))
3016 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3020 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
3021 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3022 on ? PHY_M_LED_ALL : 0);
3026 /* blink LED's for finding board */
3027 static int sky2_phys_id(struct net_device *dev, u32 data)
3029 struct sky2_port *sky2 = netdev_priv(dev);
3030 struct sky2_hw *hw = sky2->hw;
3031 unsigned port = sky2->port;
3032 u16 ledctrl, ledover = 0;
3037 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
3038 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
3042 /* save initial values */
3043 spin_lock_bh(&sky2->phy_lock);
3044 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3045 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3046 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3047 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
3048 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3050 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
3051 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
3055 while (!interrupted && ms > 0) {
3056 sky2_led(hw, port, onoff);
3059 spin_unlock_bh(&sky2->phy_lock);
3060 interrupted = msleep_interruptible(250);
3061 spin_lock_bh(&sky2->phy_lock);
3066 /* resume regularly scheduled programming */
3067 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3068 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3069 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3070 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
3071 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3073 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
3074 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
3076 spin_unlock_bh(&sky2->phy_lock);
3081 static void sky2_get_pauseparam(struct net_device *dev,
3082 struct ethtool_pauseparam *ecmd)
3084 struct sky2_port *sky2 = netdev_priv(dev);
3086 switch (sky2->flow_mode) {
3088 ecmd->tx_pause = ecmd->rx_pause = 0;
3091 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3094 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3097 ecmd->tx_pause = ecmd->rx_pause = 1;
3100 ecmd->autoneg = sky2->autoneg;
3103 static int sky2_set_pauseparam(struct net_device *dev,
3104 struct ethtool_pauseparam *ecmd)
3106 struct sky2_port *sky2 = netdev_priv(dev);
3108 sky2->autoneg = ecmd->autoneg;
3109 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
3111 if (netif_running(dev))
3112 sky2_phy_reinit(sky2);
3117 static int sky2_get_coalesce(struct net_device *dev,
3118 struct ethtool_coalesce *ecmd)
3120 struct sky2_port *sky2 = netdev_priv(dev);
3121 struct sky2_hw *hw = sky2->hw;
3123 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3124 ecmd->tx_coalesce_usecs = 0;
3126 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3127 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3129 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3131 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3132 ecmd->rx_coalesce_usecs = 0;
3134 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3135 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3137 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3139 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3140 ecmd->rx_coalesce_usecs_irq = 0;
3142 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3143 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3146 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3151 /* Note: this affect both ports */
3152 static int sky2_set_coalesce(struct net_device *dev,
3153 struct ethtool_coalesce *ecmd)
3155 struct sky2_port *sky2 = netdev_priv(dev);
3156 struct sky2_hw *hw = sky2->hw;
3157 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
3159 if (ecmd->tx_coalesce_usecs > tmax ||
3160 ecmd->rx_coalesce_usecs > tmax ||
3161 ecmd->rx_coalesce_usecs_irq > tmax)
3164 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
3166 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
3168 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
3171 if (ecmd->tx_coalesce_usecs == 0)
3172 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3174 sky2_write32(hw, STAT_TX_TIMER_INI,
3175 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3176 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3178 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3180 if (ecmd->rx_coalesce_usecs == 0)
3181 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3183 sky2_write32(hw, STAT_LEV_TIMER_INI,
3184 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3185 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3187 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3189 if (ecmd->rx_coalesce_usecs_irq == 0)
3190 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3192 sky2_write32(hw, STAT_ISR_TIMER_INI,
3193 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3194 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3196 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3200 static void sky2_get_ringparam(struct net_device *dev,
3201 struct ethtool_ringparam *ering)
3203 struct sky2_port *sky2 = netdev_priv(dev);
3205 ering->rx_max_pending = RX_MAX_PENDING;
3206 ering->rx_mini_max_pending = 0;
3207 ering->rx_jumbo_max_pending = 0;
3208 ering->tx_max_pending = TX_RING_SIZE - 1;
3210 ering->rx_pending = sky2->rx_pending;
3211 ering->rx_mini_pending = 0;
3212 ering->rx_jumbo_pending = 0;
3213 ering->tx_pending = sky2->tx_pending;
3216 static int sky2_set_ringparam(struct net_device *dev,
3217 struct ethtool_ringparam *ering)
3219 struct sky2_port *sky2 = netdev_priv(dev);
3222 if (ering->rx_pending > RX_MAX_PENDING ||
3223 ering->rx_pending < 8 ||
3224 ering->tx_pending < MAX_SKB_TX_LE ||
3225 ering->tx_pending > TX_RING_SIZE - 1)
3228 if (netif_running(dev))
3231 sky2->rx_pending = ering->rx_pending;
3232 sky2->tx_pending = ering->tx_pending;
3234 if (netif_running(dev)) {
3239 sky2_set_multicast(dev);
3245 static int sky2_get_regs_len(struct net_device *dev)
3251 * Returns copy of control register region
3252 * Note: access to the RAM address register set will cause timeouts.
3254 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3257 const struct sky2_port *sky2 = netdev_priv(dev);
3258 const void __iomem *io = sky2->hw->regs;
3260 BUG_ON(regs->len < B3_RI_WTO_R1);
3262 memset(p, 0, regs->len);
3264 memcpy_fromio(p, io, B3_RAM_ADDR);
3266 memcpy_fromio(p + B3_RI_WTO_R1,
3268 regs->len - B3_RI_WTO_R1);
3271 static const struct ethtool_ops sky2_ethtool_ops = {
3272 .get_settings = sky2_get_settings,
3273 .set_settings = sky2_set_settings,
3274 .get_drvinfo = sky2_get_drvinfo,
3275 .get_wol = sky2_get_wol,
3276 .set_wol = sky2_set_wol,
3277 .get_msglevel = sky2_get_msglevel,
3278 .set_msglevel = sky2_set_msglevel,
3279 .nway_reset = sky2_nway_reset,
3280 .get_regs_len = sky2_get_regs_len,
3281 .get_regs = sky2_get_regs,
3282 .get_link = ethtool_op_get_link,
3283 .get_sg = ethtool_op_get_sg,
3284 .set_sg = ethtool_op_set_sg,
3285 .get_tx_csum = ethtool_op_get_tx_csum,
3286 .set_tx_csum = ethtool_op_set_tx_csum,
3287 .get_tso = ethtool_op_get_tso,
3288 .set_tso = ethtool_op_set_tso,
3289 .get_rx_csum = sky2_get_rx_csum,
3290 .set_rx_csum = sky2_set_rx_csum,
3291 .get_strings = sky2_get_strings,
3292 .get_coalesce = sky2_get_coalesce,
3293 .set_coalesce = sky2_set_coalesce,
3294 .get_ringparam = sky2_get_ringparam,
3295 .set_ringparam = sky2_set_ringparam,
3296 .get_pauseparam = sky2_get_pauseparam,
3297 .set_pauseparam = sky2_set_pauseparam,
3298 .phys_id = sky2_phys_id,
3299 .get_stats_count = sky2_get_stats_count,
3300 .get_ethtool_stats = sky2_get_ethtool_stats,
3301 .get_perm_addr = ethtool_op_get_perm_addr,
3304 /* Initialize network device */
3305 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
3307 int highmem, int wol)
3309 struct sky2_port *sky2;
3310 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3313 dev_err(&hw->pdev->dev, "etherdev alloc failed");
3317 SET_MODULE_OWNER(dev);
3318 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3319 dev->irq = hw->pdev->irq;
3320 dev->open = sky2_up;
3321 dev->stop = sky2_down;
3322 dev->do_ioctl = sky2_ioctl;
3323 dev->hard_start_xmit = sky2_xmit_frame;
3324 dev->get_stats = sky2_get_stats;
3325 dev->set_multicast_list = sky2_set_multicast;
3326 dev->set_mac_address = sky2_set_mac_address;
3327 dev->change_mtu = sky2_change_mtu;
3328 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3329 dev->tx_timeout = sky2_tx_timeout;
3330 dev->watchdog_timeo = TX_WATCHDOG;
3332 dev->poll = sky2_poll;
3333 dev->weight = NAPI_WEIGHT;
3334 #ifdef CONFIG_NET_POLL_CONTROLLER
3335 /* Network console (only works on port 0)
3336 * because netpoll makes assumptions about NAPI
3339 dev->poll_controller = sky2_netpoll;
3342 sky2 = netdev_priv(dev);
3345 sky2->msg_enable = netif_msg_init(debug, default_msg);
3347 /* Auto speed and flow control */
3348 sky2->autoneg = AUTONEG_ENABLE;
3349 sky2->flow_mode = FC_BOTH;
3353 sky2->advertising = sky2_supported_modes(hw);
3357 spin_lock_init(&sky2->phy_lock);
3358 sky2->tx_pending = TX_DEF_PENDING;
3359 sky2->rx_pending = RX_DEF_PENDING;
3361 hw->dev[port] = dev;
3365 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
3367 dev->features |= NETIF_F_HIGHDMA;
3369 #ifdef SKY2_VLAN_TAG_USED
3370 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3371 dev->vlan_rx_register = sky2_vlan_rx_register;
3372 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
3375 /* read the mac address */
3376 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
3377 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3379 /* device is off until link detection */
3380 netif_carrier_off(dev);
3381 netif_stop_queue(dev);
3386 static void __devinit sky2_show_addr(struct net_device *dev)
3388 const struct sky2_port *sky2 = netdev_priv(dev);
3390 if (netif_msg_probe(sky2))
3391 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3393 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3394 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3397 /* Handle software interrupt used during MSI test */
3398 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
3400 struct sky2_hw *hw = dev_id;
3401 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3406 if (status & Y2_IS_IRQ_SW) {
3408 wake_up(&hw->msi_wait);
3409 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3411 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3416 /* Test interrupt path by forcing a a software IRQ */
3417 static int __devinit sky2_test_msi(struct sky2_hw *hw)
3419 struct pci_dev *pdev = hw->pdev;
3422 init_waitqueue_head (&hw->msi_wait);
3424 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3426 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
3428 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
3432 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
3433 sky2_read8(hw, B0_CTST);
3435 wait_event_timeout(hw->msi_wait, hw->msi, HZ/10);
3438 /* MSI test failed, go back to INTx mode */
3439 dev_info(&pdev->dev, "No interrupt generated using MSI, "
3440 "switching to INTx mode.\n");
3443 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3446 sky2_write32(hw, B0_IMSK, 0);
3447 sky2_read32(hw, B0_IMSK);
3449 free_irq(pdev->irq, hw);
3454 static int __devinit pci_wake_enabled(struct pci_dev *dev)
3456 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
3461 if (pci_read_config_word(dev, pm + PCI_PM_CTRL, &value))
3463 return value & PCI_PM_CTRL_PME_ENABLE;
3466 static int __devinit sky2_probe(struct pci_dev *pdev,
3467 const struct pci_device_id *ent)
3469 struct net_device *dev;
3471 int err, using_dac = 0, wol_default;
3473 err = pci_enable_device(pdev);
3475 dev_err(&pdev->dev, "cannot enable PCI device\n");
3479 err = pci_request_regions(pdev, DRV_NAME);
3481 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
3485 pci_set_master(pdev);
3487 if (sizeof(dma_addr_t) > sizeof(u32) &&
3488 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3490 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3492 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
3493 "for consistent allocations\n");
3494 goto err_out_free_regions;
3497 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3499 dev_err(&pdev->dev, "no usable DMA configuration\n");
3500 goto err_out_free_regions;
3504 wol_default = pci_wake_enabled(pdev) ? WAKE_MAGIC : 0;
3507 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
3509 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
3510 goto err_out_free_regions;
3515 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3517 dev_err(&pdev->dev, "cannot map device registers\n");
3518 goto err_out_free_hw;
3522 /* The sk98lin vendor driver uses hardware byte swapping but
3523 * this driver uses software swapping.
3527 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
3528 reg &= ~PCI_REV_DESC;
3529 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3533 /* ring for status responses */
3534 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3537 goto err_out_iounmap;
3539 err = sky2_init(hw);
3541 goto err_out_iounmap;
3543 dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
3544 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
3545 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
3546 hw->chip_id, hw->chip_rev);
3550 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
3553 goto err_out_free_pci;
3556 if (!disable_msi && pci_enable_msi(pdev) == 0) {
3557 err = sky2_test_msi(hw);
3558 if (err == -EOPNOTSUPP)
3559 pci_disable_msi(pdev);
3561 goto err_out_free_netdev;
3564 err = register_netdev(dev);
3566 dev_err(&pdev->dev, "cannot register net device\n");
3567 goto err_out_free_netdev;
3570 err = request_irq(pdev->irq, sky2_intr, hw->msi ? 0 : IRQF_SHARED,
3573 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
3574 goto err_out_unregister;
3576 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3578 sky2_show_addr(dev);
3580 if (hw->ports > 1) {
3581 struct net_device *dev1;
3583 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
3585 dev_warn(&pdev->dev, "allocation for second device failed\n");
3586 else if ((err = register_netdev(dev1))) {
3587 dev_warn(&pdev->dev,
3588 "register of second port failed (%d)\n", err);
3592 sky2_show_addr(dev1);
3595 setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) hw);
3596 sky2_idle_start(hw);
3598 pci_set_drvdata(pdev, hw);
3604 pci_disable_msi(pdev);
3605 unregister_netdev(dev);
3606 err_out_free_netdev:
3609 sky2_write8(hw, B0_CTST, CS_RST_SET);
3610 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3615 err_out_free_regions:
3616 pci_release_regions(pdev);
3617 pci_disable_device(pdev);
3622 static void __devexit sky2_remove(struct pci_dev *pdev)
3624 struct sky2_hw *hw = pci_get_drvdata(pdev);
3625 struct net_device *dev0, *dev1;
3630 del_timer_sync(&hw->idle_timer);
3632 sky2_write32(hw, B0_IMSK, 0);
3633 synchronize_irq(hw->pdev->irq);
3638 unregister_netdev(dev1);
3639 unregister_netdev(dev0);
3643 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
3644 sky2_write8(hw, B0_CTST, CS_RST_SET);
3645 sky2_read8(hw, B0_CTST);
3647 free_irq(pdev->irq, hw);
3649 pci_disable_msi(pdev);
3650 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3651 pci_release_regions(pdev);
3652 pci_disable_device(pdev);
3660 pci_set_drvdata(pdev, NULL);
3664 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3666 struct sky2_hw *hw = pci_get_drvdata(pdev);
3669 del_timer_sync(&hw->idle_timer);
3670 netif_poll_disable(hw->dev[0]);
3672 for (i = 0; i < hw->ports; i++) {
3673 struct net_device *dev = hw->dev[i];
3674 struct sky2_port *sky2 = netdev_priv(dev);
3676 if (netif_running(dev))
3680 sky2_wol_init(sky2);
3685 sky2_write32(hw, B0_IMSK, 0);
3688 pci_save_state(pdev);
3689 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
3690 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3695 static int sky2_resume(struct pci_dev *pdev)
3697 struct sky2_hw *hw = pci_get_drvdata(pdev);
3700 err = pci_set_power_state(pdev, PCI_D0);
3704 err = pci_restore_state(pdev);
3708 pci_enable_wake(pdev, PCI_D0, 0);
3711 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3713 for (i = 0; i < hw->ports; i++) {
3714 struct net_device *dev = hw->dev[i];
3715 if (netif_running(dev)) {
3718 printk(KERN_ERR PFX "%s: could not up: %d\n",
3726 netif_poll_enable(hw->dev[0]);
3727 sky2_idle_start(hw);
3730 dev_err(&pdev->dev, "resume failed (%d)\n", err);
3731 pci_disable_device(pdev);
3736 static void sky2_shutdown(struct pci_dev *pdev)
3738 struct sky2_hw *hw = pci_get_drvdata(pdev);
3741 del_timer_sync(&hw->idle_timer);
3742 netif_poll_disable(hw->dev[0]);
3744 for (i = 0; i < hw->ports; i++) {
3745 struct net_device *dev = hw->dev[i];
3746 struct sky2_port *sky2 = netdev_priv(dev);
3750 sky2_wol_init(sky2);
3757 pci_enable_wake(pdev, PCI_D3hot, wol);
3758 pci_enable_wake(pdev, PCI_D3cold, wol);
3760 pci_disable_device(pdev);
3761 pci_set_power_state(pdev, PCI_D3hot);
3765 static struct pci_driver sky2_driver = {
3767 .id_table = sky2_id_table,
3768 .probe = sky2_probe,
3769 .remove = __devexit_p(sky2_remove),
3771 .suspend = sky2_suspend,
3772 .resume = sky2_resume,
3774 .shutdown = sky2_shutdown,
3777 static int __init sky2_init_module(void)
3779 return pci_register_driver(&sky2_driver);
3782 static void __exit sky2_cleanup_module(void)
3784 pci_unregister_driver(&sky2_driver);
3787 module_init(sky2_init_module);
3788 module_exit(sky2_cleanup_module);
3790 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3791 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
3792 MODULE_LICENSE("GPL");
3793 MODULE_VERSION(DRV_VERSION);