[SPARC64]: Kill pci_controller->base_address_update().

Implemented but never actually used.

Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/arch/sparc64/kernel/pci_psycho.c b/arch/sparc64/kernel/pci_psycho.c
index c3f2127..64bd357 100644 (file)
--- a/arch/sparc64/kernel/pci_psycho.c
+++ b/arch/sparc64/kernel/pci_psycho.c
@@ -894,50 +894,6 @@ static void psycho_register_error_handlers(struct pci_controller_info *p)
 }
 
 /* PSYCHO boot time probing and initialization. */
-static void psycho_base_address_update(struct pci_dev *pdev, int resource)
-{
-       struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
-       struct resource *res, *root;
-       u32 reg;
-       int where, size, is_64bit;
-
-       res = &pdev->resource[resource];
-       if (resource < 6) {
-               where = PCI_BASE_ADDRESS_0 + (resource * 4);
-       } else if (resource == PCI_ROM_RESOURCE) {
-               where = pdev->rom_base_reg;
-       } else {
-               /* Somebody might have asked allocation of a non-standard resource */
-               return;
-       }
-
-       is_64bit = 0;
-       if (res->flags & IORESOURCE_IO)
-               root = &pbm->io_space;
-       else {
-               root = &pbm->mem_space;
-               if ((res->flags & PCI_BASE_ADDRESS_MEM_TYPE_MASK)
-                   == PCI_BASE_ADDRESS_MEM_TYPE_64)
-                       is_64bit = 1;
-       }
-
-       size = res->end - res->start;
-       pci_read_config_dword(pdev, where, &reg);
-       reg = ((reg & size) |
-              (((u32)(res->start - root->start)) & ~size));
-       if (resource == PCI_ROM_RESOURCE) {
-               reg |= PCI_ROM_ADDRESS_ENABLE;
-               res->flags |= IORESOURCE_ROM_ENABLE;
-       }
-       pci_write_config_dword(pdev, where, reg);
-
-       /* This knows that the upper 32-bits of the address
-        * must be zero.  Our PCI common layer enforces this.
-        */
-       if (is_64bit)
-               pci_write_config_dword(pdev, where + 4, 0);
-}
-
 static void pbm_config_busmastering(struct pci_pbm_info *pbm)
 {
        u8 *addr;
@@ -1209,7 +1165,6 @@ void psycho_init(struct device_node *dp, char *model_name)
        p->index = pci_num_controllers++;
        p->pbms_same_domain = 0;
        p->scan_bus = psycho_scan_bus;
-       p->base_address_update = psycho_base_address_update;
        p->pci_ops = &psycho_ops;
 
        prop = of_find_property(dp, "reg", NULL);

diff --git a/arch/sparc64/kernel/pci_sabre.c b/arch/sparc64/kernel/pci_sabre.c
index 64cdce8..f3ec7bd 100644 (file)
--- a/arch/sparc64/kernel/pci_sabre.c
+++ b/arch/sparc64/kernel/pci_sabre.c
@@ -862,51 +862,6 @@ static void sabre_register_error_handlers(struct pci_controller_info *p)
        sabre_write(base + SABRE_PCICTRL, tmp);
 }
 
-static void sabre_base_address_update(struct pci_dev *pdev, int resource)
-{
-       struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
-       struct resource *res;
-       unsigned long base;
-       u32 reg;
-       int where, size, is_64bit;
-
-       res = &pdev->resource[resource];
-       if (resource < 6) {
-               where = PCI_BASE_ADDRESS_0 + (resource * 4);
-       } else if (resource == PCI_ROM_RESOURCE) {
-               where = pdev->rom_base_reg;
-       } else {
-               /* Somebody might have asked allocation of a non-standard resource */
-               return;
-       }
-
-       is_64bit = 0;
-       if (res->flags & IORESOURCE_IO)
-               base = pbm->controller_regs + SABRE_IOSPACE;
-       else {
-               base = pbm->controller_regs + SABRE_MEMSPACE;
-               if ((res->flags & PCI_BASE_ADDRESS_MEM_TYPE_MASK)
-                   == PCI_BASE_ADDRESS_MEM_TYPE_64)
-                       is_64bit = 1;
-       }
-
-       size = res->end - res->start;
-       pci_read_config_dword(pdev, where, &reg);
-       reg = ((reg & size) |
-              (((u32)(res->start - base)) & ~size));
-       if (resource == PCI_ROM_RESOURCE) {
-               reg |= PCI_ROM_ADDRESS_ENABLE;
-               res->flags |= IORESOURCE_ROM_ENABLE;
-       }
-       pci_write_config_dword(pdev, where, reg);
-
-       /* This knows that the upper 32-bits of the address
-        * must be zero.  Our PCI common layer enforces this.
-        */
-       if (is_64bit)
-               pci_write_config_dword(pdev, where + 4, 0);
-}
-
 static void apb_init(struct pci_controller_info *p, struct pci_bus *sabre_bus)
 {
        struct pci_dev *pdev;
@@ -1099,7 +1054,6 @@ void sabre_init(struct device_node *dp, char *model_name)
        p->index = pci_num_controllers++;
        p->pbms_same_domain = 1;
        p->scan_bus = sabre_scan_bus;
-       p->base_address_update = sabre_base_address_update;
        p->pci_ops = &sabre_ops;
 
        /*

diff --git a/arch/sparc64/kernel/pci_schizo.c b/arch/sparc64/kernel/pci_schizo.c
index ba9206e..99912db 100644 (file)
--- a/arch/sparc64/kernel/pci_schizo.c
+++ b/arch/sparc64/kernel/pci_schizo.c
@@ -1251,50 +1251,6 @@ static void schizo_scan_bus(struct pci_controller_info *p)
                schizo_register_error_handlers(p);
 }
 
-static void schizo_base_address_update(struct pci_dev *pdev, int resource)
-{
-       struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
-       struct resource *res, *root;
-       u32 reg;
-       int where, size, is_64bit;
-
-       res = &pdev->resource[resource];
-       if (resource < 6) {
-               where = PCI_BASE_ADDRESS_0 + (resource * 4);
-       } else if (resource == PCI_ROM_RESOURCE) {
-               where = pdev->rom_base_reg;
-       } else {
-               /* Somebody might have asked allocation of a non-standard resource */
-               return;
-       }
-
-       is_64bit = 0;
-       if (res->flags & IORESOURCE_IO)
-               root = &pbm->io_space;
-       else {
-               root = &pbm->mem_space;
-               if ((res->flags & PCI_BASE_ADDRESS_MEM_TYPE_MASK)
-                   == PCI_BASE_ADDRESS_MEM_TYPE_64)
-                       is_64bit = 1;
-       }
-
-       size = res->end - res->start;
-       pci_read_config_dword(pdev, where, &reg);
-       reg = ((reg & size) |
-              (((u32)(res->start - root->start)) & ~size));
-       if (resource == PCI_ROM_RESOURCE) {
-               reg |= PCI_ROM_ADDRESS_ENABLE;
-               res->flags |= IORESOURCE_ROM_ENABLE;
-       }
-       pci_write_config_dword(pdev, where, reg);
-
-       /* This knows that the upper 32-bits of the address
-        * must be zero.  Our PCI common layer enforces this.
-        */
-       if (is_64bit)
-               pci_write_config_dword(pdev, where + 4, 0);
-}
-
 #define SCHIZO_STRBUF_CONTROL          (0x02800UL)
 #define SCHIZO_STRBUF_FLUSH            (0x02808UL)
 #define SCHIZO_STRBUF_FSYNC            (0x02810UL)
@@ -1661,7 +1617,6 @@ static void __schizo_init(struct device_node *dp, char *model_name, int chip_typ
 
        p->index = pci_num_controllers++;
        p->scan_bus = schizo_scan_bus;
-       p->base_address_update = schizo_base_address_update;
        p->pci_ops = &schizo_ops;
 
        /* Like PSYCHO we have a 2GB aligned area for memory space. */

diff --git a/arch/sparc64/kernel/pci_sun4v.c b/arch/sparc64/kernel/pci_sun4v.c
index ce0417e..f9cd9f6 100644 (file)
--- a/arch/sparc64/kernel/pci_sun4v.c
+++ b/arch/sparc64/kernel/pci_sun4v.c
@@ -698,51 +698,6 @@ static void pci_sun4v_scan_bus(struct pci_controller_info *p)
        /* XXX register error interrupt handlers XXX */
 }
 
-static void pci_sun4v_base_address_update(struct pci_dev *pdev, int resource)
-{
-       struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
-       struct resource *res, *root;
-       u32 reg;
-       int where, size, is_64bit;
-
-       res = &pdev->resource[resource];
-       if (resource < 6) {
-               where = PCI_BASE_ADDRESS_0 + (resource * 4);
-       } else if (resource == PCI_ROM_RESOURCE) {
-               where = pdev->rom_base_reg;
-       } else {
-               /* Somebody might have asked allocation of a non-standard resource */
-               return;
-       }
-
-       /* XXX 64-bit MEM handling is not %100 correct... XXX */
-       is_64bit = 0;
-       if (res->flags & IORESOURCE_IO)
-               root = &pbm->io_space;
-       else {
-               root = &pbm->mem_space;
-               if ((res->flags & PCI_BASE_ADDRESS_MEM_TYPE_MASK)
-                   == PCI_BASE_ADDRESS_MEM_TYPE_64)
-                       is_64bit = 1;
-       }
-
-       size = res->end - res->start;
-       pci_read_config_dword(pdev, where, &reg);
-       reg = ((reg & size) |
-              (((u32)(res->start - root->start)) & ~size));
-       if (resource == PCI_ROM_RESOURCE) {
-               reg |= PCI_ROM_ADDRESS_ENABLE;
-               res->flags |= IORESOURCE_ROM_ENABLE;
-       }
-       pci_write_config_dword(pdev, where, reg);
-
-       /* This knows that the upper 32-bits of the address
-        * must be zero.  Our PCI common layer enforces this.
-        */
-       if (is_64bit)
-               pci_write_config_dword(pdev, where + 4, 0);
-}
-
 static unsigned long probe_existing_entries(struct pci_pbm_info *pbm,
                                            struct pci_iommu *iommu)
 {
@@ -1378,7 +1333,6 @@ void sun4v_pci_init(struct device_node *dp, char *model_name)
        p->pbms_same_domain = 0;
 
        p->scan_bus = pci_sun4v_scan_bus;
-       p->base_address_update = pci_sun4v_base_address_update;
 #ifdef CONFIG_PCI_MSI
        p->setup_msi_irq = pci_sun4v_setup_msi_irq;
        p->teardown_msi_irq = pci_sun4v_teardown_msi_irq;

diff --git a/include/asm-sparc64/pbm.h b/include/asm-sparc64/pbm.h
index 1bd5b37..07f58ad 100644 (file)
--- a/include/asm-sparc64/pbm.h
+++ b/include/asm-sparc64/pbm.h
@@ -224,7 +224,6 @@ struct pci_controller_info {
 
        /* Operations which are controller specific. */
        void (*scan_bus)(struct pci_controller_info *);
-       void (*base_address_update)(struct pci_dev *, int);
 
 #ifdef CONFIG_PCI_MSI
        int (*setup_msi_irq)(unsigned int *virt_irq_p, struct pci_dev *pdev,