4 Copyright 2008, 2009 Michel Pollet <buserror@gmail.com>
6 This file is part of simavr.
8 simavr is free software: you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation, either version 3 of the License, or
11 (at your option) any later version.
13 simavr is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with simavr. If not, see <http://www.gnu.org/licenses/>.
22 #include </usr/include/stdio.h>
24 #include "sim_core_declare.h"
25 #include "avr_eeprom.h"
26 #include "avr_ioport.h"
28 #include "avr_timer8.h"
34 #include "avr/iom644.h"
36 static void init(struct avr_t * avr);
37 static void reset(struct avr_t * avr);
43 avr_ioport_t porta, portb, portc, portd;
44 avr_uart_t uart0,uart1;
45 avr_timer8_t timer0,timer2;
56 AVR_EEPROM_DECLARE(EE_READY_vect),
58 .name = 'A', .r_port = PORTA, .r_ddr = DDRA, .r_pin = PINA,
60 .enable = AVR_IO_REGBIT(PCICR, PCIE0),
61 .raised = AVR_IO_REGBIT(PCIFR, PCIF0),
62 .vector = PCINT0_vect,
67 .name = 'B', .r_port = PORTB, .r_ddr = DDRB, .r_pin = PINB,
69 .enable = AVR_IO_REGBIT(PCICR, PCIE1),
70 .raised = AVR_IO_REGBIT(PCIFR, PCIF1),
71 .vector = PCINT1_vect,
76 .name = 'C', .r_port = PORTC, .r_ddr = DDRC, .r_pin = PINC,
78 .enable = AVR_IO_REGBIT(PCICR, PCIE2),
79 .raised = AVR_IO_REGBIT(PCIFR, PCIF2),
80 .vector = PCINT2_vect,
85 .name = 'D', .r_port = PORTD, .r_ddr = DDRD, .r_pin = PIND,
87 .enable = AVR_IO_REGBIT(PCICR, PCIE3),
88 .raised = AVR_IO_REGBIT(PCIFR, PCIF3),
89 .vector = PCINT3_vect,
95 .disabled = AVR_IO_REGBIT(PRR,PRUSART0),
99 .txen = AVR_IO_REGBIT(UCSR0B, TXEN0),
100 .rxen = AVR_IO_REGBIT(UCSR0B, RXEN0),
108 .enable = AVR_IO_REGBIT(UCSR0B, RXCIE0),
109 .raised = AVR_IO_REGBIT(UCSR0A, RXC0),
110 .vector = USART0_RX_vect,
113 .enable = AVR_IO_REGBIT(UCSR0B, TXCIE0),
114 .raised = AVR_IO_REGBIT(UCSR0A, TXC0),
115 .vector = USART0_TX_vect,
118 .enable = AVR_IO_REGBIT(UCSR0B, UDRIE0),
119 .raised = AVR_IO_REGBIT(UCSR0A, UDRE0),
120 .vector = USART0_UDRE_vect,
124 .disabled = AVR_IO_REGBIT(PRR,PRUSART1),
128 .txen = AVR_IO_REGBIT(UCSR1B, TXEN1),
129 .rxen = AVR_IO_REGBIT(UCSR1B, RXEN1),
137 .enable = AVR_IO_REGBIT(UCSR1B, RXCIE1),
138 .raised = AVR_IO_REGBIT(UCSR1A, RXC1),
139 .vector = USART1_RX_vect,
142 .enable = AVR_IO_REGBIT(UCSR1B, TXCIE1),
143 .raised = AVR_IO_REGBIT(UCSR1A, TXC1),
144 .vector = USART1_TX_vect,
147 .enable = AVR_IO_REGBIT(UCSR1B, UDRIE1),
148 .raised = AVR_IO_REGBIT(UCSR1A, UDRE1),
149 .vector = USART1_UDRE_vect,
155 .wgm = { AVR_IO_REGBIT(TCCR0A, WGM00), AVR_IO_REGBIT(TCCR0A, WGM01), AVR_IO_REGBIT(TCCR0B, WGM02) },
156 .cs = { AVR_IO_REGBIT(TCCR0B, CS00), AVR_IO_REGBIT(TCCR0B, CS01), AVR_IO_REGBIT(TCCR0B, CS02) },
157 .cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */ },
164 .enable = AVR_IO_REGBIT(TIMSK0, TOIE0),
165 .raised = AVR_IO_REGBIT(TIFR0, TOV0),
166 .vector = TIMER0_OVF_vect,
169 .enable = AVR_IO_REGBIT(TIMSK0, OCIE0A),
170 .raised = AVR_IO_REGBIT(TIFR0, OCF0A),
171 .vector = TIMER0_COMPA_vect,
174 .enable = AVR_IO_REGBIT(TIMSK0, OCIE0B),
175 .raised = AVR_IO_REGBIT(TIFR0, OCF0B),
176 .vector = TIMER0_COMPB_vect,
181 .wgm = { AVR_IO_REGBIT(TCCR2A, WGM20), AVR_IO_REGBIT(TCCR2A, WGM21), AVR_IO_REGBIT(TCCR2B, WGM22) },
182 .cs = { AVR_IO_REGBIT(TCCR2B, CS20), AVR_IO_REGBIT(TCCR2B, CS21), AVR_IO_REGBIT(TCCR2B, CS22) },
183 .cs_div = { 0, 0, 3 /* 8 */, 5 /* 32 */, 6 /* 64 */, 7 /* 128 */, 8 /* 256 */, 10 /* 1024 */ },
189 // asynchronous timer source bit.. if set, use 32khz frequency
190 .as2 = AVR_IO_REGBIT(ASSR, AS2),
193 .enable = AVR_IO_REGBIT(TIMSK2, TOIE2),
194 .raised = AVR_IO_REGBIT(TIFR2, TOV2),
195 .vector = TIMER2_OVF_vect,
198 .enable = AVR_IO_REGBIT(TIMSK2, OCIE2A),
199 .raised = AVR_IO_REGBIT(TIFR2, OCF2A),
200 .vector = TIMER2_COMPA_vect,
203 .enable = AVR_IO_REGBIT(TIMSK2, OCIE2B),
204 .raised = AVR_IO_REGBIT(TIFR2, OCF2B),
205 .vector = TIMER2_COMPB_vect,
209 .disabled = AVR_IO_REGBIT(PRR,PRSPI),
215 .spe = AVR_IO_REGBIT(SPCR, SPE),
216 .mstr = AVR_IO_REGBIT(SPCR, MSTR),
218 .spr = { AVR_IO_REGBIT(SPCR, SPR0), AVR_IO_REGBIT(SPCR, SPR1), AVR_IO_REGBIT(SPSR, SPI2X) },
220 .enable = AVR_IO_REGBIT(SPCR, SPIE),
221 .raised = AVR_IO_REGBIT(SPSR, SPIF),
222 .vector = SPI_STC_vect,
227 .disabled = AVR_IO_REGBIT(PRR,PRTWI),
236 .twen = AVR_IO_REGBIT(TWCR, TWEN),
237 .twea = AVR_IO_REGBIT(TWCR, TWEA),
238 .twsta = AVR_IO_REGBIT(TWCR, TWSTA),
239 .twsto = AVR_IO_REGBIT(TWCR, TWSTO),
240 .twwc = AVR_IO_REGBIT(TWCR, TWWC),
242 .twsr = AVR_IO_REGBITS(TWSR, TWS3, 0x1f), // 5 bits
243 .twps = AVR_IO_REGBITS(TWSR, TWPS0, 0x3), // 2 bits
246 .enable = AVR_IO_REGBIT(TWCR, TWIE),
247 .raised = AVR_IO_REGBIT(TWSR, TWINT),
254 static avr_t * make()
259 avr_kind_t mega644 = {
260 .names = { "atmega644", "atmega644p" },
264 static void init(struct avr_t * avr)
266 struct mcu_t * mcu = (struct mcu_t*)avr;
268 printf("%s init\n", avr->mmcu);
270 avr_eeprom_init(avr, &mcu->eeprom);
271 avr_ioport_init(avr, &mcu->porta);
272 avr_ioport_init(avr, &mcu->portb);
273 avr_ioport_init(avr, &mcu->portc);
274 avr_ioport_init(avr, &mcu->portd);
275 avr_uart_init(avr, &mcu->uart0);
276 avr_uart_init(avr, &mcu->uart1);
277 avr_timer8_init(avr, &mcu->timer0);
278 avr_timer8_init(avr, &mcu->timer2);
279 avr_spi_init(avr, &mcu->spi);
280 avr_twi_init(avr, &mcu->twi);
283 static void reset(struct avr_t * avr)
285 // struct mcu_t * mcu = (struct mcu_t*)avr;