4 Copyright 2008, 2010 Michel Pollet <buserror@gmail.com>
6 This file is part of simavr.
8 simavr is free software: you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation, either version 3 of the License, or
11 (at your option) any later version.
13 simavr is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with simavr. If not, see <http://www.gnu.org/licenses/>.
27 static avr_cycle_count_t avr_adc_int_raise(struct avr_t * avr, avr_cycle_count_t when, void * param)
29 avr_adc_t * p = (avr_adc_t *)param;
30 if (avr_regbit_get(avr, p->aden)) {
31 // if the interrupts are not used, still raised the UDRE and TXC flag
32 avr_raise_interrupt(avr, &p->adc);
33 avr_regbit_clear(avr, p->adsc);
40 static uint8_t avr_adc_read_l(struct avr_t * avr, avr_io_addr_t addr, void * param)
42 avr_adc_t * p = (avr_adc_t *)param;
44 if (p->read_status) // conversion already done
45 return avr_core_watch_read(avr, addr);
47 uint8_t refi = avr_regbit_get_array(avr, p->ref, ARRAY_SIZE(p->ref));
48 uint16_t ref = p->ref_values[refi];
49 uint8_t muxi = avr_regbit_get_array(avr, p->mux, ARRAY_SIZE(p->mux));
50 avr_adc_mux_t mux = p->muxmode[muxi];
51 // optional shift left/right
52 uint8_t shift = avr_regbit_get(avr, p->adlar) ? 6 : 0; // shift LEFT
57 reg = p->adc_values[mux.src];
62 reg = ((uint32_t)p->adc_values[mux.src] * mux.gain) -
63 ((uint32_t)p->adc_values[mux.diff] * mux.gain);
66 reg = p->temp; // assumed to be already calibrated somehow
69 reg = mux.src; // reference voltage
76 printf("ADC Warning : missing VCC analog voltage\n");
82 printf("ADC Warning : missing AREF analog voltage\n");
88 printf("ADC Warning : missing AVCC analog voltage\n");
95 // printf("ADCL %d:%3d:%3d read %4d vref %d:%d=%d\n",
96 // mux.kind, mux.diff, mux.src,
97 // reg, refi, ref, vref);
98 reg = (reg * 0x3ff) / vref; // scale to 10 bits ADC
99 // printf("ADC to 10 bits 0x%x %d\n", reg, reg);
101 printf("ADC Warning channel %d clipped %u/%u VREF %d\n", mux.kind, reg, 0x3ff, vref);
105 // printf("ADC to 10 bits %x shifted %d\n", reg, shift);
106 avr->data[p->r_adcl] = reg;
107 avr->data[p->r_adch] = reg >> 8;
109 return avr_core_watch_read(avr, addr);
114 * "When ADCL is read, the ADC Data Register is not updated until ADCH is read.
115 * Consequently, if the result is left adjusted and no more than 8-bit
116 * precision is required, it is sufficient to read ADCH.
117 * Otherwise, ADCL must be read first, then ADCH."
118 * So here if the H is read before the L, we still call the L to update the
121 static uint8_t avr_adc_read_h(struct avr_t * avr, avr_io_addr_t addr, void * param)
123 avr_adc_t * p = (avr_adc_t *)param;
124 // no "break" here on purpose
125 switch (p->read_status) {
127 avr_adc_read_l(avr, p->r_adcl, param);
131 return avr_core_watch_read(avr, addr);
135 static void avr_adc_write(struct avr_t * avr, avr_io_addr_t addr, uint8_t v, void * param)
137 avr_adc_t * p = (avr_adc_t *)param;
138 uint8_t adsc = avr_regbit_get(avr, p->adsc);
139 uint8_t aden = avr_regbit_get(avr, p->aden);
141 avr->data[p->adsc.reg] = v;
143 // can't write zero to adsc
144 if (adsc && !avr_regbit_get(avr, p->adsc)) {
145 avr_regbit_set(avr, p->adsc);
146 v = avr->data[p->adsc.reg];
148 if (!aden && avr_regbit_get(avr, p->aden)) {
151 printf("ADC Start AREF %d AVCC %d\n", avr->aref, avr->avcc);
153 if (aden && !avr_regbit_get(avr, p->aden)) {
155 avr_cycle_timer_cancel(avr, avr_adc_int_raise, p);
156 avr_regbit_clear(avr, p->adsc);
158 if (!adsc && avr_regbit_get(avr, p->adsc)) {
160 uint8_t muxi = avr_regbit_get_array(avr, p->mux, ARRAY_SIZE(p->mux));
164 } e = { .mux = p->muxmode[muxi] };
165 avr_raise_irq(p->io.irq + ADC_IRQ_OUT_TRIGGER, e.v);
167 // clock prescaler are just a bit shift.. and 0 means 1
168 uint32_t div = avr_regbit_get_array(avr, p->adps, ARRAY_SIZE(p->adps));
171 div = avr->frequency >> div;
173 printf("ADC starting at %uKHz\n", div / 13 / 100);
174 div /= p->first ? 25 : 13; // first cycle is longer
176 avr_cycle_timer_register(avr,
177 avr_hz_to_cycles(avr, div),
178 avr_adc_int_raise, p);
180 avr_core_watch_write(avr, addr, v);
183 static void avr_adc_irq_notify(struct avr_irq_t * irq, uint32_t value, void * param)
185 avr_adc_t * p = (avr_adc_t *)param;
186 avr_t * avr = p->io.avr;
189 case ADC_IRQ_ADC0 ... ADC_IRQ_ADC7: {
190 p->adc_values[irq->irq] = value;
195 case ADC_IRQ_IN_TRIGGER: {
196 if (avr_regbit_get(avr, p->adate)) {
197 // start a conversion
203 static void avr_adc_reset(avr_io_t * port)
205 avr_adc_t * p = (avr_adc_t *)port;
208 avr_cycle_timer_cancel(p->io.avr, avr_adc_int_raise, p);
209 avr_regbit_clear(p->io.avr, p->adsc);
211 for (int i = 0; i < ADC_IRQ_COUNT; i++)
212 avr_irq_register_notify(p->io.irq + i, avr_adc_irq_notify, p);
215 static const char * irq_names[ADC_IRQ_COUNT] = {
216 [ADC_IRQ_ADC0] = "16<adc0",
217 [ADC_IRQ_ADC1] = "16<adc1",
218 [ADC_IRQ_ADC2] = "16<adc2",
219 [ADC_IRQ_ADC3] = "16<adc3",
220 [ADC_IRQ_ADC4] = "16<adc4",
221 [ADC_IRQ_ADC5] = "16<adc5",
222 [ADC_IRQ_ADC6] = "16<adc6",
223 [ADC_IRQ_ADC7] = "16<adc7",
224 [ADC_IRQ_TEMP] = "16<temp",
225 [ADC_IRQ_IN_TRIGGER] = "<trigger_in",
226 [ADC_IRQ_OUT_TRIGGER] = ">trigger_out",
229 static avr_io_t _io = {
231 .reset = avr_adc_reset,
232 .irq_names = irq_names,
235 void avr_adc_init(avr_t * avr, avr_adc_t * p)
239 avr_register_io(avr, &p->io);
240 avr_register_vector(avr, &p->adc);
241 // allocate this module's IRQ
242 avr_io_setirqs(&p->io, AVR_IOCTL_ADC_GETIRQ, ADC_IRQ_COUNT, NULL);
244 avr_register_io_write(avr, p->r_adcsra, avr_adc_write, p);
245 avr_register_io_read(avr, p->r_adcl, avr_adc_read_l, p);
246 avr_register_io_read(avr, p->r_adch, avr_adc_read_h, p);