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   1 /*
   2         avr_twi.c
   3
   4         Copyright 2008, 2009 Michel Pollet <buserror@gmail.com>
   5
   6         This file is part of simavr.
   7
   8         simavr is free software: you can redistribute it and/or modify
   9         it under the terms of the GNU General Public License as published by
  10         the Free Software Foundation, either version 3 of the License, or
  11         (at your option) any later version.
  12
  13         simavr is distributed in the hope that it will be useful,
  14         but WITHOUT ANY WARRANTY; without even the implied warranty of
  15         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16         GNU General Public License for more details.
  17
  18         You should have received a copy of the GNU General Public License
  19         along with simavr.  If not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include <stdio.h>
  23 #include "avr_twi.h"
  24
  25 /*
  26  * This block respectfully nicked straight out from the Atmel sample
  27  * code for AVR315. Typos and all.
  28  * There is no copyright notice on the original file.
  29  */
  30 /****************************************************************************
  31   TWI State codes
  32 ****************************************************************************/
  33 // General TWI Master status codes
  34 #define TWI_START                  0x08  // START has been transmitted
  35 #define TWI_REP_START              0x10  // Repeated START has been transmitted
  36 #define TWI_ARB_LOST               0x38  // Arbitration lost
  37
  38 // TWI Master Transmitter status codes
  39 #define TWI_MTX_ADR_ACK            0x18  // SLA+W has been transmitted and ACK received
  40 #define TWI_MTX_ADR_NACK           0x20  // SLA+W has been transmitted and NACK received
  41 #define TWI_MTX_DATA_ACK           0x28  // Data byte has been transmitted and ACK received
  42 #define TWI_MTX_DATA_NACK          0x30  // Data byte has been transmitted and NACK received
  43
  44 // TWI Master Receiver status codes
  45 #define TWI_MRX_ADR_ACK            0x40  // SLA+R has been transmitted and ACK received
  46 #define TWI_MRX_ADR_NACK           0x48  // SLA+R has been transmitted and NACK received
  47 #define TWI_MRX_DATA_ACK           0x50  // Data byte has been received and ACK transmitted
  48 #define TWI_MRX_DATA_NACK          0x58  // Data byte has been received and NACK transmitted
  49
  50 // TWI Slave Transmitter status codes
  51 #define TWI_STX_ADR_ACK            0xA8  // Own SLA+R has been received; ACK has been returned
  52 #define TWI_STX_ADR_ACK_M_ARB_LOST 0xB0  // Arbitration lost in SLA+R/W as Master; own SLA+R has been received; ACK has been returned
  53 #define TWI_STX_DATA_ACK           0xB8  // Data byte in TWDR has been transmitted; ACK has been received
  54 #define TWI_STX_DATA_NACK          0xC0  // Data byte in TWDR has been transmitted; NOT ACK has been received
  55 #define TWI_STX_DATA_ACK_LAST_BYTE 0xC8  // Last data byte in TWDR has been transmitted (TWEA = �0�); ACK has been received
  56
  57 // TWI Slave Receiver status codes
  58 #define TWI_SRX_ADR_ACK            0x60  // Own SLA+W has been received ACK has been returned
  59 #define TWI_SRX_ADR_ACK_M_ARB_LOST 0x68  // Arbitration lost in SLA+R/W as Master; own SLA+W has been received; ACK has been returned
  60 #define TWI_SRX_GEN_ACK            0x70  // General call address has been received; ACK has been returned
  61 #define TWI_SRX_GEN_ACK_M_ARB_LOST 0x78  // Arbitration lost in SLA+R/W as Master; General call address has been received; ACK has been returned
  62 #define TWI_SRX_ADR_DATA_ACK       0x80  // Previously addressed with own SLA+W; data has been received; ACK has been returned
  63 #define TWI_SRX_ADR_DATA_NACK      0x88  // Previously addressed with own SLA+W; data has been received; NOT ACK has been returned
  64 #define TWI_SRX_GEN_DATA_ACK       0x90  // Previously addressed with general call; data has been received; ACK has been returned
  65 #define TWI_SRX_GEN_DATA_NACK      0x98  // Previously addressed with general call; data has been received; NOT ACK has been returned
  66 #define TWI_SRX_STOP_RESTART       0xA0  // A STOP condition or repeated START condition has been received while still addressed as Slave
  67
  68 // TWI Miscellaneous status codes
  69 #define TWI_NO_STATE               0xF8  // No relevant state information available; TWINT = �0�
  70 #define TWI_BUS_ERROR              0x00  // Bus error due to an illegal START or STOP condition
  71
  72 #define AVR_TWI_DEBUG 0
  73
  74 static inline void
  75 _avr_twi_status_set(
  76                 avr_twi_t * p,
  77                 uint8_t v,
  78                 int interrupt)
  79 {
  80         avr_regbit_setto_raw(p->io.avr, p->twsr, v);
  81 #if AVR_TWI_DEBUG
  82         printf("_avr_twi_status_set %02x\n", v);
  83 #endif
  84         avr_raise_irq(p->io.irq + TWI_IRQ_STATUS, v);
  85         if (interrupt)
  86                 avr_raise_interrupt(p->io.avr, &p->twi);
  87 }
  88
  89 static inline uint8_t
  90 _avr_twi_status_get(
  91                 avr_twi_t * p)
  92 {
  93         return avr_regbit_get_raw(p->io.avr, p->twsr);
  94 }
  95
  96 static avr_cycle_count_t
  97 avr_twi_set_state_timer(
  98                 struct avr_t * avr,
  99                 avr_cycle_count_t when,
 100                 void * param)
 101 {
 102         avr_twi_t * p = (avr_twi_t *)param;
 103         _avr_twi_status_set(p, p->next_twstate, 1);
 104         p->next_twstate = 0;
 105         return 0;
 106 }
 107
 108 /*
 109  * This is supposed to trigger a timer whose duration is a multiple
 110  * of 'twi' clock cycles, which should be derived from the prescaler
 111  * (100khz, 400khz etc).
 112  * Right now it cheats and uses one twi cycle == one usec.
 113  */
 114 static void
 115 _avr_twi_delay_state(
 116                 avr_twi_t * p,
 117                 int twi_cycles,
 118                 uint8_t state)
 119 {
 120         p->next_twstate = state;
 121         // TODO: calculate clock rate, convert to cycles, and use that
 122         avr_cycle_timer_register_usec(
 123                         p->io.avr, twi_cycles, avr_twi_set_state_timer, p);
 124 }
 125
 126 static void
 127 avr_twi_write(
 128                 struct avr_t * avr,
 129                 avr_io_addr_t addr,
 130                 uint8_t v,
 131                 void * param)
 132 {
 133         avr_twi_t * p = (avr_twi_t *)param;
 134
 135         uint8_t twen = avr_regbit_get(avr, p->twen);
 136         uint8_t twsta = avr_regbit_get(avr, p->twsta);
 137         uint8_t twsto = avr_regbit_get(avr, p->twsto);
 138         uint8_t twint = avr_regbit_get(avr, p->twi.raised);
 139
 140         avr_core_watch_write(avr, addr, v);
 141 #if AVR_TWI_DEBUG
 142         printf("avr_twi_write %02x START:%d STOP:%d ACK:%d INT:%d TWSR:%02x (state %02x)\n", v,
 143                         avr_regbit_get(avr, p->twsta),
 144                         avr_regbit_get(avr, p->twsto),
 145                         avr_regbit_get(avr, p->twea),
 146                         avr_regbit_get(avr, p->twi.raised),
 147                         avr_regbit_get_raw(p->io.avr, p->twsr), p->state);
 148 #endif
 149         if (twen != avr_regbit_get(avr, p->twen)) {
 150                 twen = !twen;
 151                 if (!twen) { // if we were running, now now are not
 152                         avr_regbit_clear(avr, p->twea);
 153                         avr_regbit_clear(avr, p->twsta);
 154                         avr_regbit_clear(avr, p->twsto);
 155                         avr_clear_interrupt(avr, &p->twi);
 156                         avr_core_watch_write(avr, p->r_twdr, 0xff);
 157                         _avr_twi_status_set(p, TWI_NO_STATE, 0);
 158                         p->state = 0;
 159                         p->peer_addr = 0;
 160                 }
 161                 printf("TWEN: %d\n", twen);
 162         }
 163         if (!twen)
 164                 return;
 165
 166         uint8_t cleared = avr_regbit_get(avr, p->twi.raised);
 167
 168         /*int cleared = */avr_clear_interrupt_if(avr, &p->twi, twint);
 169 //      printf("cleared %d\n", cleared);
 170
 171         if (!twsto && avr_regbit_get(avr, p->twsto)) {
 172                 // generate a stop condition
 173 #if AVR_TWI_DEBUG
 174                 printf("<<<<< I2C stop\n");
 175 #endif
 176                 if (p->state) { // doing stuff
 177                         if (p->state & TWI_COND_START) {
 178                                 avr_raise_irq(p->io.irq + TWI_IRQ_MOSI,
 179                                                 avr_twi_irq_msg(TWI_COND_STOP, p->peer_addr, 1));
 180                         }
 181                 }
 182                 p->state = 0;
 183         }
 184         if (!twsta && avr_regbit_get(avr, p->twsta)) {
 185 #if AVR_TWI_DEBUG
 186                 printf(">>>>> I2C %sstart\n", p->state & TWI_COND_START ? "RE" : "");
 187 #endif
 188                 // generate a start condition
 189                 if (p->state & TWI_COND_START)
 190                         _avr_twi_delay_state(p, 3, TWI_REP_START);
 191                 else
 192                         _avr_twi_delay_state(p, 3, TWI_START);
 193                 p->peer_addr = 0;
 194                 p->state = TWI_COND_START;
 195         }
 196
 197         if (cleared &&
 198                         !avr_regbit_get(avr, p->twsta) &&
 199                         !avr_regbit_get(avr, p->twsto)) {
 200                 // writing or reading a byte
 201                 if (p->state & TWI_COND_ADDR) {
 202                         int do_read = p->peer_addr & 1;
 203 #if AVR_TWI_DEBUG
 204                         if (do_read)
 205                                 printf("I2C READ byte from %02x\n", p->peer_addr);
 206                         else
 207                                 printf("I2C WRITE byte %02x to %02x\n", avr->data[p->r_twdr], p->peer_addr);
 208 #endif
 209                         // a normal data byte
 210                         uint8_t msgv = do_read ? TWI_COND_READ : TWI_COND_WRITE;
 211
 212                         if (avr_regbit_get(avr, p->twea))
 213                                 msgv |= TWI_COND_ACK;
 214
 215                         p->state &= ~TWI_COND_ACK;      // clear ACK bit
 216
 217                         // if the latch is ready... as set by writing/reading the TWDR
 218                         if ((p->state & msgv)) {
 219
 220                                 // we send an IRQ and we /expect/ a slave to reply
 221                                 // immediately via an IRQ to set the COND_ACK bit
 222                                 // otherwise it's assumed it's been nacked...
 223                                 avr_raise_irq(p->io.irq + TWI_IRQ_MOSI,
 224                                                 avr_twi_irq_msg(msgv, p->peer_addr, avr->data[p->r_twdr]));
 225
 226                                 if (do_read) { // read ?
 227                                         _avr_twi_delay_state(p, 9,
 228                                                         msgv & TWI_COND_ACK ?
 229                                                                         TWI_MRX_DATA_ACK : TWI_MRX_DATA_NACK);
 230                                 } else {
 231                                         _avr_twi_delay_state(p, 9,
 232                                                         p->state & TWI_COND_ACK ?
 233                                                                         TWI_MTX_DATA_ACK : TWI_MTX_DATA_NACK);
 234                                 }
 235                         }
 236 #if AVR_TWI_DEBUG
 237                         else
 238                                 printf("I2C latch is not ready, do nothing\n");
 239 #endif
 240                 } else {
 241 #if AVR_TWI_DEBUG
 242                         printf("I2C Master address %02x\n", avr->data[p->r_twdr]);
 243 #endif
 244                         // send the address
 245                         p->state |= TWI_COND_ADDR;
 246                         p->peer_addr = avr->data[p->r_twdr];
 247                         p->state &= ~TWI_COND_ACK;      // clear ACK bit
 248
 249                         // we send an IRQ and we /expect/ a slave to reply
 250                         // immediately via an IRQ tp set the COND_ACK bit
 251                         // otherwise it's assumed it's been nacked...
 252                         avr_raise_irq(p->io.irq + TWI_IRQ_MOSI,
 253                                         avr_twi_irq_msg(TWI_COND_START, p->peer_addr, 0));
 254
 255                         if (p->peer_addr & 1) { // read ?
 256                                 p->state |= TWI_COND_READ;      // always allow read to start with
 257                                 _avr_twi_delay_state(p, 9,
 258                                                 p->state & TWI_COND_ACK ?
 259                                                                 TWI_MRX_ADR_ACK : TWI_MRX_ADR_NACK);
 260                         } else {
 261                                 _avr_twi_delay_state(p, 9,
 262                                                 p->state & TWI_COND_ACK ?
 263                                                                 TWI_MTX_ADR_ACK : TWI_MTX_ADR_NACK);
 264                         }
 265                 }
 266                 p->state &= ~TWI_COND_WRITE;
 267         }
 268 }
 269
 270 /*
 271  * Write data to the latch, tell the system we have something
 272  * to send next
 273  */
 274 static void
 275 avr_twi_write_data(
 276                 struct avr_t * avr,
 277                 avr_io_addr_t addr,
 278                 uint8_t v,
 279                 void * param)
 280 {
 281         avr_twi_t * p = (avr_twi_t *)param;
 282
 283         avr_core_watch_write(avr, addr, v);
 284         // tell system we have something in the write latch
 285         p->state |= TWI_COND_WRITE;
 286 }
 287
 288 /*
 289  * Read data from the latch, tell the system can receive a new byte
 290  */
 291 static uint8_t
 292 avr_twi_read_data(
 293                 struct avr_t * avr,
 294                 avr_io_addr_t addr,
 295                 void * param)
 296 {
 297         avr_twi_t * p = (avr_twi_t *)param;
 298
 299         // tell system we can receive another byte
 300         p->state |= TWI_COND_READ;
 301         return avr->data[p->r_twdr];
 302 }
 303
 304 /*
 305  * prevent code from rewriting out status bits, since we actually use them!
 306  */
 307 static void
 308 avr_twi_write_status(
 309                 struct avr_t * avr,
 310                 avr_io_addr_t addr,
 311                 uint8_t v,
 312                 void * param)
 313 {
 314         avr_twi_t * p = (avr_twi_t *)param;
 315         uint8_t sr = avr_regbit_get(avr, p->twsr);
 316         uint8_t c = avr_regbit_get(avr, p->twps);
 317
 318         avr_core_watch_write(avr, addr, v);
 319         avr_regbit_setto(avr, p->twsr, sr);     // force restore
 320
 321         if (c != avr_regbit_get(avr, p->twps)) {
 322                 // prescaler bits changed...
 323         }
 324 }
 325
 326 static void
 327 avr_twi_irq_input(
 328                 struct avr_irq_t * irq,
 329                 uint32_t value,
 330                 void * param)
 331 {
 332         avr_twi_t * p = (avr_twi_t *)param;
 333         avr_t * avr = p->io.avr;
 334
 335         // check to see if we are enabled
 336         if (!avr_regbit_get(avr, p->twen))
 337                 return;
 338         avr_twi_msg_irq_t msg;
 339         msg.u.v = value;
 340
 341         // receiving an acknowledge bit
 342         if (msg.u.twi.msg & TWI_COND_ACK) {
 343 #if AVR_TWI_DEBUG
 344                 printf("I2C received ACK:%d\n", msg.u.twi.data & 1);
 345 #endif
 346                 if (msg.u.twi.data & 1)
 347                         p->state |= TWI_COND_ACK;
 348                 else
 349                         p->state &= ~TWI_COND_ACK;
 350         }
 351         // receive a data byte from a slave
 352         if (msg.u.twi.msg & TWI_COND_READ) {
 353 #if AVR_TWI_DEBUG
 354                 printf("I2C received %02x\n", msg.u.twi.data);
 355 #endif
 356                 avr->data[p->r_twdr] = msg.u.twi.data;
 357         }
 358 }
 359
 360 void avr_twi_reset(struct avr_io_t *io)
 361 {
 362         avr_twi_t * p = (avr_twi_t *)io;
 363         avr_irq_register_notify(p->io.irq + TWI_IRQ_MISO, avr_twi_irq_input, p);
 364 }
 365
 366 static const char * irq_names[TWI_IRQ_COUNT] = {
 367         [TWI_IRQ_MISO] = "8<mosi",
 368         [TWI_IRQ_MOSI] = "32>miso",
 369         [TWI_IRQ_STATUS] = "8>status",
 370 };
 371
 372 static  avr_io_t        _io = {
 373         .kind = "twi",
 374         .reset = avr_twi_reset,
 375         .irq_names = irq_names,
 376 };
 377
 378 void avr_twi_init(avr_t * avr, avr_twi_t * p)
 379 {
 380         p->io = _io;
 381         avr_register_io(avr, &p->io);
 382         avr_register_vector(avr, &p->twi);
 383
 384         //printf("%s TWI%c init\n", __FUNCTION__, p->name);
 385
 386         // allocate this module's IRQ
 387         avr_io_setirqs(&p->io, AVR_IOCTL_TWI_GETIRQ(p->name), TWI_IRQ_COUNT, NULL);
 388
 389         avr_register_io_write(avr, p->twen.reg, avr_twi_write, p);
 390         avr_register_io_write(avr, p->r_twdr, avr_twi_write_data, p);
 391         avr_register_io_read(avr, p->r_twdr, avr_twi_read_data, p);
 392         avr_register_io_write(avr, p->twsr.reg, avr_twi_write_status, p);
 393 }
 394