5 Right now just handle "write" to the serial port at any speed
6 and printf to the console when '\n' is written.
8 Copyright 2008, 2009 Michel Pollet <buserror@gmail.com>
10 This file is part of simavr.
12 simavr is free software: you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation, either version 3 of the License, or
15 (at your option) any later version.
17 simavr is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with simavr. If not, see <http://www.gnu.org/licenses/>.
30 #define FONT_GREEN "\e[32m"
31 #define FONT_DEFAULT "\e[0m"
41 //#define TRACE(_w) _w
46 DEFINE_FIFO(uint8_t, uart_fifo);
48 static avr_cycle_count_t avr_uart_txc_raise(struct avr_t * avr, avr_cycle_count_t when, void * param)
50 avr_uart_t * p = (avr_uart_t *)param;
51 if (avr_regbit_get(avr, p->txen)) {
52 // if the interrupts are not used, still raise the UDRE and TXC flag
53 avr_raise_interrupt(avr, &p->udrc);
54 avr_raise_interrupt(avr, &p->txc);
59 static avr_cycle_count_t avr_uart_rxc_raise(struct avr_t * avr, avr_cycle_count_t when, void * param)
61 avr_uart_t * p = (avr_uart_t *)param;
62 if (avr_regbit_get(avr, p->rxen))
63 avr_raise_interrupt(avr, &p->rxc);
67 static uint8_t avr_uart_rxc_read(struct avr_t * avr, avr_io_addr_t addr, void * param)
69 avr_uart_t * p = (avr_uart_t *)param;
70 uint8_t v = avr_core_watch_read(avr, addr);
72 //static uint8_t old = 0xff; if (v != old) printf("UCSRA read %02x\n", v); old = v;
74 // if RX is enabled, and there is nothing to read, and
75 // the AVR core is reading this register, it's probably
76 // to poll the RXC TXC flag and spinloop
77 // so here we introduce a usleep to make it a bit lighter
78 // on CPU and let data arrive
80 uint8_t ri = !avr_regbit_get(avr, p->rxen) || !avr_regbit_get(avr, p->rxc.raised);
81 uint8_t ti = !avr_regbit_get(avr, p->txen) || !avr_regbit_get(avr, p->txc.raised);
83 if (p->flags & AVR_UART_FLAG_POOL_SLEEP) {
88 // if reception is idle and the fifo is empty, tell whomever there is room
89 if (avr_regbit_get(avr, p->rxen) && uart_fifo_isempty(&p->input)) {
90 avr_raise_irq(p->io.irq + UART_IRQ_OUT_XOFF, 0);
91 avr_raise_irq(p->io.irq + UART_IRQ_OUT_XON, 1);
97 static uint8_t avr_uart_read(struct avr_t * avr, avr_io_addr_t addr, void * param)
99 avr_uart_t * p = (avr_uart_t *)param;
101 // clear the rxc bit in case the code is using polling
102 avr_regbit_clear(avr, p->rxc.raised);
104 if (!avr_regbit_get(avr, p->rxen)) {
106 // made to trigger potential watchpoints
107 avr_core_watch_read(avr, addr);
110 uint8_t v = uart_fifo_read(&p->input);
112 // TRACE(printf("UART read %02x %s\n", v, uart_fifo_isempty(&p->input) ? "EMPTY!" : "");)
114 // made to trigger potential watchpoints
115 v = avr_core_watch_read(avr, addr);
117 // trigger timer if more characters are pending
118 if (!uart_fifo_isempty(&p->input))
119 avr_cycle_timer_register_usec(avr, p->usec_per_byte, avr_uart_rxc_raise, p);
124 static void avr_uart_baud_write(struct avr_t * avr, avr_io_addr_t addr, uint8_t v, void * param)
126 avr_uart_t * p = (avr_uart_t *)param;
127 avr_core_watch_write(avr, addr, v);
128 uint32_t val = avr->data[p->r_ubrrl] | (avr->data[p->r_ubrrh] << 8);
129 uint32_t baud = avr->frequency / (val+1);
130 if (avr_regbit_get(avr, p->u2x))
135 const int databits[] = { 5,6,7,8, /* 'reserved', assume 8 */8,8,8, 9 };
136 int db = databits[avr_regbit_get(avr, p->ucsz) | (avr_regbit_get(avr, p->ucsz2) << 2)];
137 int sb = 1 + avr_regbit_get(avr, p->usbs);
138 int word_size = 1 /* start */ + db /* data bits */ + 1 /* parity */ + sb /* stops */;
140 AVR_LOG(avr, LOG_TRACE, "UART: %c configured to %04x = %d bps (x%d), %d data %d stop\n",
141 p->name, val, baud, avr_regbit_get(avr, p->u2x)?2:1, db, sb);
142 // TODO: Use the divider value and calculate the straight number of cycles
143 p->usec_per_byte = 1000000 / (baud / word_size);
144 AVR_LOG(avr, LOG_TRACE, "UART: Roughly %d usec per bytes\n", (int)p->usec_per_byte);
147 static void avr_uart_write(struct avr_t * avr, avr_io_addr_t addr, uint8_t v, void * param)
149 avr_uart_t * p = (avr_uart_t *)param;
151 if (addr == p->r_udr) {
152 avr_core_watch_write(avr, addr, v);
155 avr_regbit_clear(avr, p->udrc.raised);
156 avr_cycle_timer_register_usec(avr,
157 p->usec_per_byte, avr_uart_txc_raise, p); // should be uart speed dependent
159 if (p->flags & AVR_UART_FLAG_STDIO) {
160 const int maxsize = 256;
162 p->stdio_out = malloc(maxsize);
163 p->stdio_out[p->stdio_len++] = v < ' ' ? '.' : v;
164 p->stdio_out[p->stdio_len] = 0;
165 if (v == '\n' || p->stdio_len == maxsize) {
167 printf( FONT_GREEN "%s\n" FONT_DEFAULT, p->stdio_out);
170 TRACE(printf("UDR%c(%02x) = %02x\n", p->name, addr, v);)
171 // tell other modules we are "outputting" a byte
172 if (avr_regbit_get(avr, p->txen))
173 avr_raise_irq(p->io.irq + UART_IRQ_OUTPUT, v);
175 if (p->udrc.vector && addr == p->udrc.enable.reg) {
177 * If enabling the UDRC interrupt, raise it immediately if FIFO is empty
179 uint8_t udrce = avr_regbit_get(avr, p->udrc.enable);
180 avr_core_watch_write(avr, addr, v);
181 uint8_t nudrce = avr_regbit_get(avr, p->udrc.enable);
182 if (!udrce && nudrce) {
183 // if the FIDO is not empty (clear timer is flying) we don't
184 // need to raise the interrupt, it will happen when the timer
186 if (avr_cycle_timer_status(avr, avr_uart_txc_raise, p) == 0)
187 avr_raise_interrupt(avr, &p->udrc);
190 if (p->udrc.vector && addr == p->udrc.raised.reg) {
191 // get the bits before the write
192 //uint8_t udre = avr_regbit_get(avr, p->udrc.raised);
193 uint8_t txc = avr_regbit_get(avr, p->txc.raised);
195 // required for u2x (double uart transmission speed)
196 avr_core_watch_write(avr, addr, v);
198 //avr_clear_interrupt_if(avr, &p->udrc, udre);
199 avr_clear_interrupt_if(avr, &p->txc, txc);
203 static void avr_uart_irq_input(struct avr_irq_t * irq, uint32_t value, void * param)
205 avr_uart_t * p = (avr_uart_t *)param;
206 avr_t * avr = p->io.avr;
208 // check to see if receiver is enabled
209 if (!avr_regbit_get(avr, p->rxen))
212 if (uart_fifo_isempty(&p->input))
213 avr_cycle_timer_register_usec(avr, p->usec_per_byte, avr_uart_rxc_raise, p); // should be uart speed dependent
214 uart_fifo_write(&p->input, value); // add to fifo
216 TRACE(printf("UART IRQ in %02x (%d/%d) %s\n", value, p->input.read, p->input.write, uart_fifo_isfull(&p->input) ? "FULL!!" : "");)
218 if (uart_fifo_isfull(&p->input))
219 avr_raise_irq(p->io.irq + UART_IRQ_OUT_XOFF, 1);
223 void avr_uart_reset(struct avr_io_t *io)
225 avr_uart_t * p = (avr_uart_t *)io;
226 avr_t * avr = p->io.avr;
228 avr_regbit_set(avr, p->udrc.raised);
229 avr_irq_register_notify(p->io.irq + UART_IRQ_INPUT, avr_uart_irq_input, p);
230 avr_cycle_timer_cancel(avr, avr_uart_rxc_raise, p);
231 avr_cycle_timer_cancel(avr, avr_uart_txc_raise, p);
232 uart_fifo_reset(&p->input);
234 avr_regbit_set(avr, p->ucsz);
235 avr_regbit_clear(avr, p->ucsz2);
237 // DEBUG allow printf without fiddling with enabling the uart
238 avr_regbit_set(avr, p->txen);
239 p->usec_per_byte = 100;
242 static int avr_uart_ioctl(struct avr_io_t * port, uint32_t ctl, void * io_param)
244 avr_uart_t * p = (avr_uart_t *)port;
250 if (ctl == AVR_IOCTL_UART_SET_FLAGS(p->name)) {
251 p->flags = *(uint32_t*)io_param;
254 if (ctl == AVR_IOCTL_UART_GET_FLAGS(p->name)) {
255 *(uint32_t*)io_param = p->flags;
262 static const char * irq_names[UART_IRQ_COUNT] = {
263 [UART_IRQ_INPUT] = "8<in",
264 [UART_IRQ_OUTPUT] = "8>out",
265 [UART_IRQ_OUT_XON] = ">xon",
266 [UART_IRQ_OUT_XOFF] = ">xoff",
269 static avr_io_t _io = {
271 .reset = avr_uart_reset,
272 .ioctl = avr_uart_ioctl,
273 .irq_names = irq_names,
276 void avr_uart_init(avr_t * avr, avr_uart_t * p)
280 // printf("%s UART%c UDR=%02x\n", __FUNCTION__, p->name, p->r_udr);
282 p->flags = AVR_UART_FLAG_POOL_SLEEP|AVR_UART_FLAG_STDIO;
284 avr_register_io(avr, &p->io);
285 avr_register_vector(avr, &p->rxc);
286 avr_register_vector(avr, &p->txc);
287 avr_register_vector(avr, &p->udrc);
289 // allocate this module's IRQ
290 avr_io_setirqs(&p->io, AVR_IOCTL_UART_GETIRQ(p->name), UART_IRQ_COUNT, NULL);
291 // Only call callbacks when the value change...
292 p->io.irq[UART_IRQ_OUT_XOFF].flags |= IRQ_FLAG_FILTERED;
294 avr_register_io_write(avr, p->r_udr, avr_uart_write, p);
295 avr_register_io_read(avr, p->r_udr, avr_uart_read, p);
296 // monitor code that reads the rxc flag, and delay it a bit
297 avr_register_io_read(avr, p->rxc.raised.reg, avr_uart_rxc_read, p);
300 avr_register_io_write(avr, p->udrc.enable.reg, avr_uart_write, p);
302 avr_register_io_write(avr, p->r_ucsra, avr_uart_write, p);
304 avr_register_io_write(avr, p->r_ubrrl, avr_uart_baud_write, p);