5 Right now just handle "write" to the serial port at any speed
6 and printf to the console when '\n' is written.
8 Copyright 2008, 2009 Michel Pollet <buserror@gmail.com>
10 This file is part of simavr.
12 simavr is free software: you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation, either version 3 of the License, or
15 (at your option) any later version.
17 simavr is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with simavr. If not, see <http://www.gnu.org/licenses/>.
31 DEFINE_FIFO(uint8_t, uart_fifo, 64);
33 static avr_cycle_count_t avr_uart_txc_raise(struct avr_t * avr, avr_cycle_count_t when, void * param)
35 avr_uart_t * p = (avr_uart_t *)param;
36 if (avr_regbit_get(avr, p->txen)) {
37 // if the interrupts are not used, still raised the UDRE and TXC flag
38 avr_raise_interrupt(avr, &p->udrc);
39 avr_raise_interrupt(avr, &p->txc);
44 static avr_cycle_count_t avr_uart_rxc_raise(struct avr_t * avr, avr_cycle_count_t when, void * param)
46 avr_uart_t * p = (avr_uart_t *)param;
47 if (avr_regbit_get(avr, p->rxen))
48 avr_raise_interrupt(avr, &p->rxc);
52 static uint8_t avr_uart_rxc_read(struct avr_t * avr, avr_io_addr_t addr, void * param)
54 avr_uart_t * p = (avr_uart_t *)param;
55 uint8_t v = avr_core_watch_read(avr, addr);
57 //static uint8_t old = 0xff; if (v != old) printf("UCSRA read %02x\n", v); old = v;
59 // if RX is enabled, and there is nothing to read, and
60 // the AVR core is reading this register, it's probably
61 // to pool the RXC TXC flag and spinloop
62 // so here we introduce a usleep to make it a bit lighter
63 // on CPU and let data arrive
65 uint8_t ri = !avr_regbit_get(avr, p->rxen) || !avr_regbit_get(avr, p->rxc.raised);
66 uint8_t ti = !avr_regbit_get(avr, p->txen) || !avr_regbit_get(avr, p->txc.raised);
68 if (p->flags & AVR_UART_FLAG_POOL_SLEEP) {
73 // if reception is idle and the fifo is empty, tell whomever there is room
74 if (avr_regbit_get(avr, p->rxen) && uart_fifo_isempty(&p->input))
75 avr_raise_irq(p->io.irq + UART_IRQ_OUT_XON, 1);
80 static uint8_t avr_uart_read(struct avr_t * avr, avr_io_addr_t addr, void * param)
82 avr_uart_t * p = (avr_uart_t *)param;
84 // clear the rxc bit in case the code is using pooling
85 avr_regbit_clear(avr, p->rxc.raised);
87 if (!avr_regbit_get(avr, p->rxen)) {
89 // made to trigger potential watchpoints
90 avr_core_watch_read(avr, addr);
93 uint8_t v = uart_fifo_read(&p->input);
95 //printf("UART read %02x %s\n", v, uart_fifo_isempty(&p->input) ? "EMPTY!" : "");
97 // made to trigger potential watchpoints
98 v = avr_core_watch_read(avr, addr);
100 if (!uart_fifo_isempty(&p->input))
101 avr_cycle_timer_register_usec(avr, 100, avr_uart_rxc_raise, p); // should be uart speed dependent
106 static void avr_uart_baud_write(struct avr_t * avr, avr_io_addr_t addr, uint8_t v, void * param)
108 avr_uart_t * p = (avr_uart_t *)param;
109 avr_core_watch_write(avr, addr, v);
110 uint32_t val = avr->data[p->r_ubrrl] | (avr->data[p->r_ubrrh] << 8);
111 uint32_t baud = avr->frequency / (val+1);
112 if (avr_regbit_get(avr, p->u2x))
116 printf("UART-%c configured to %04x = %d baud\n", p->name, val, baud);
119 static void avr_uart_write(struct avr_t * avr, avr_io_addr_t addr, uint8_t v, void * param)
121 avr_uart_t * p = (avr_uart_t *)param;
123 if (addr == p->r_udr) {
124 avr_core_watch_write(avr, addr, v);
126 avr_regbit_clear(avr, p->udrc.raised);
127 avr_cycle_timer_register_usec(avr, 100, avr_uart_txc_raise, p); // should be uart speed dependent
129 if (p->flags & AVR_UART_FLAG_STDIO) {
130 static char buf[128];
132 buf[l++] = v < ' ' ? '.' : v;
134 if (v == '\n' || l == 127) {
136 printf("\e[32m%s\e[0m\n", buf);
139 // printf("UDR%c(%02x) = %02x\n", p->name, addr, v);
140 // tell other modules we are "outputing" a byte
141 if (avr_regbit_get(avr, p->txen))
142 avr_raise_irq(p->io.irq + UART_IRQ_OUTPUT, v);
144 if (addr == p->udrc.enable.reg) {
146 * If enabling the UDRC interupt, raise it immediately if FIFO is empty
148 uint8_t udrce = avr_regbit_get(avr, p->udrc.enable);
149 avr_core_watch_write(avr, addr, v);
150 uint8_t nudrce = avr_regbit_get(avr, p->udrc.enable);
151 if (!udrce && nudrce) {
152 // if the FIDO is not empty (clear timer is flying) we dont
153 // need to raise the interupt, it will happend when the timer
155 if (avr_cycle_timer_status(avr, avr_uart_txc_raise, p) == 0)
156 avr_raise_interrupt(avr, &p->udrc);
159 if (addr == p->udrc.raised.reg) {
160 // get the bits before the write
161 uint8_t udre = avr_regbit_get(avr, p->udrc.raised);
162 uint8_t txc = avr_regbit_get(avr, p->txc.raised);
164 // no need to write this value in here, only the
165 // interupt flags needs clearing!
166 // avr_core_watch_write(avr, addr, v);
168 avr_clear_interupt_if(avr, &p->udrc, udre);
169 avr_clear_interupt_if(avr, &p->txc, txc);
173 static void avr_uart_irq_input(struct avr_irq_t * irq, uint32_t value, void * param)
175 avr_uart_t * p = (avr_uart_t *)param;
176 avr_t * avr = p->io.avr;
178 // check to see fi receiver is enabled
179 if (!avr_regbit_get(avr, p->rxen))
182 if (uart_fifo_isempty(&p->input))
183 avr_cycle_timer_register_usec(avr, 100, avr_uart_rxc_raise, p); // should be uart speed dependent
184 uart_fifo_write(&p->input, value); // add to fifo
186 // printf("UART IRQ in %02x (%d/%d) %s\n", value, p->input.read, p->input.write, uart_fifo_isfull(&p->input) ? "FULL!!" : "");
188 if (uart_fifo_isfull(&p->input))
189 avr_raise_irq(p->io.irq + UART_IRQ_OUT_XOFF, 1);
193 void avr_uart_reset(struct avr_io_t *io)
195 avr_uart_t * p = (avr_uart_t *)io;
196 avr_t * avr = p->io.avr;
197 avr_regbit_set(avr, p->udrc.raised);
198 avr_irq_register_notify(p->io.irq + UART_IRQ_INPUT, avr_uart_irq_input, p);
199 avr_cycle_timer_cancel(avr, avr_uart_rxc_raise, p);
200 avr_cycle_timer_cancel(avr, avr_uart_txc_raise, p);
201 uart_fifo_reset(&p->input);
203 // DEBUG allow printf without fidding with enabling the uart
204 avr_regbit_set(avr, p->txen);
208 static int avr_uart_ioctl(struct avr_io_t * port, uint32_t ctl, void * io_param)
210 avr_uart_t * p = (avr_uart_t *)port;
216 if (ctl == AVR_IOCTL_UART_SET_FLAGS(p->name)) {
217 p->flags = *(uint32_t*)io_param;
220 if (ctl == AVR_IOCTL_UART_GET_FLAGS(p->name)) {
221 *(uint32_t*)io_param = p->flags;
228 static const char * irq_names[UART_IRQ_COUNT] = {
229 [UART_IRQ_INPUT] = "8<in",
230 [UART_IRQ_OUTPUT] = "8>out",
231 [UART_IRQ_OUT_XON] = ">xon",
232 [UART_IRQ_OUT_XOFF] = ">xoff",
235 static avr_io_t _io = {
237 .reset = avr_uart_reset,
238 .ioctl = avr_uart_ioctl,
239 .irq_names = irq_names,
242 void avr_uart_init(avr_t * avr, avr_uart_t * p)
246 // printf("%s UART%c UDR=%02x\n", __FUNCTION__, p->name, p->r_udr);
248 p->flags = AVR_UART_FLAG_POOL_SLEEP|AVR_UART_FLAG_STDIO;
250 avr_register_io(avr, &p->io);
251 avr_register_vector(avr, &p->rxc);
252 avr_register_vector(avr, &p->txc);
253 avr_register_vector(avr, &p->udrc);
255 // allocate this module's IRQ
256 avr_io_setirqs(&p->io, AVR_IOCTL_UART_GETIRQ(p->name), UART_IRQ_COUNT, NULL);
258 avr_register_io_write(avr, p->r_udr, avr_uart_write, p);
259 avr_register_io_write(avr, p->udrc.enable.reg, avr_uart_write, p);
260 avr_register_io_read(avr, p->r_udr, avr_uart_read, p);
261 // monitor code that reads the rxc flag, and delay it a bit
262 avr_register_io_read(avr, p->rxc.raised.reg, avr_uart_rxc_read, p);
264 avr_register_io_write(avr, p->r_ucsra, avr_uart_write, p);
265 avr_register_io_write(avr, p->r_ubrrl, avr_uart_baud_write, p);