5 Right now just handle "write" to the serial port at any speed
6 and printf to the console when '\n' is written.
8 Copyright 2008, 2009 Michel Pollet <buserror@gmail.com>
10 This file is part of simavr.
12 simavr is free software: you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation, either version 3 of the License, or
15 (at your option) any later version.
17 simavr is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with simavr. If not, see <http://www.gnu.org/licenses/>.
31 DEFINE_FIFO(uint8_t, uart_fifo, 64);
33 static avr_cycle_count_t avr_uart_txc_raise(struct avr_t * avr, avr_cycle_count_t when, void * param)
35 avr_uart_t * p = (avr_uart_t *)param;
36 if (avr_regbit_get(avr, p->txen)) {
37 // if the interrupts are not used, still raise the UDRE and TXC flag
38 avr_raise_interrupt(avr, &p->udrc);
39 avr_raise_interrupt(avr, &p->txc);
44 static avr_cycle_count_t avr_uart_rxc_raise(struct avr_t * avr, avr_cycle_count_t when, void * param)
46 avr_uart_t * p = (avr_uart_t *)param;
47 if (avr_regbit_get(avr, p->rxen))
48 avr_raise_interrupt(avr, &p->rxc);
52 static uint8_t avr_uart_rxc_read(struct avr_t * avr, avr_io_addr_t addr, void * param)
54 avr_uart_t * p = (avr_uart_t *)param;
55 uint8_t v = avr_core_watch_read(avr, addr);
57 //static uint8_t old = 0xff; if (v != old) printf("UCSRA read %02x\n", v); old = v;
59 // if RX is enabled, and there is nothing to read, and
60 // the AVR core is reading this register, it's probably
61 // to pool the RXC TXC flag and spinloop
62 // so here we introduce a usleep to make it a bit lighter
63 // on CPU and let data arrive
65 uint8_t ri = !avr_regbit_get(avr, p->rxen) || !avr_regbit_get(avr, p->rxc.raised);
66 uint8_t ti = !avr_regbit_get(avr, p->txen) || !avr_regbit_get(avr, p->txc.raised);
68 if (p->flags & AVR_UART_FLAG_POOL_SLEEP) {
73 // if reception is idle and the fifo is empty, tell whomever there is room
74 if (avr_regbit_get(avr, p->rxen))
75 avr_raise_irq(p->io.irq + UART_IRQ_OUT_XON, uart_fifo_isempty(&p->input) != 0);
80 static uint8_t avr_uart_read(struct avr_t * avr, avr_io_addr_t addr, void * param)
82 avr_uart_t * p = (avr_uart_t *)param;
84 // clear the rxc bit in case the code is using pooling
85 avr_regbit_clear(avr, p->rxc.raised);
87 if (!avr_regbit_get(avr, p->rxen)) {
89 // made to trigger potential watchpoints
90 avr_core_watch_read(avr, addr);
93 uint8_t v = uart_fifo_read(&p->input);
95 //printf("UART read %02x %s\n", v, uart_fifo_isempty(&p->input) ? "EMPTY!" : "");
97 // made to trigger potential watchpoints
98 v = avr_core_watch_read(avr, addr);
100 // should always trigger that timer
101 // if (!uart_fifo_isempty(&p->input))
102 avr_cycle_timer_register_usec(avr, p->usec_per_byte, avr_uart_rxc_raise, p);
107 static void avr_uart_baud_write(struct avr_t * avr, avr_io_addr_t addr, uint8_t v, void * param)
109 avr_uart_t * p = (avr_uart_t *)param;
110 avr_core_watch_write(avr, addr, v);
111 uint32_t val = avr->data[p->r_ubrrl] | (avr->data[p->r_ubrrh] << 8);
112 uint32_t baud = avr->frequency / (val+1);
113 if (avr_regbit_get(avr, p->u2x))
118 const int databits[] = { 5,6,7,8, /* 'reserved', assume 8 */8,8,8, 9 };
119 int db = databits[avr_regbit_get(avr, p->ucsz) | (avr_regbit_get(avr, p->ucsz2) << 2)];
120 int sb = 1 + avr_regbit_get(avr, p->usbs);
121 int word_size = 1 /* start */ + db /* data bits */ + 1 /* parity */ + sb /* stops */;
123 printf("UART-%c configured to %04x = %d bps, %d data %d stop\n",
124 p->name, val, baud, db, sb);
125 // TODO: Use the divider value and calculate the straight number of cycles
126 p->usec_per_byte = 1000000 / (baud / word_size);
127 printf("Roughtly %d usec per bytes\n", (int)p->usec_per_byte);
130 static void avr_uart_write(struct avr_t * avr, avr_io_addr_t addr, uint8_t v, void * param)
132 avr_uart_t * p = (avr_uart_t *)param;
134 if (addr == p->r_udr) {
135 avr_core_watch_write(avr, addr, v);
137 avr_regbit_clear(avr, p->udrc.raised);
138 avr_cycle_timer_register_usec(avr,
139 p->usec_per_byte, avr_uart_txc_raise, p); // should be uart speed dependent
141 if (p->flags & AVR_UART_FLAG_STDIO) {
142 static char buf[128];
144 buf[l++] = v < ' ' ? '.' : v;
146 if (v == '\n' || l == 127) {
148 printf("\e[32m%s\e[0m\n", buf);
151 // printf("UDR%c(%02x) = %02x\n", p->name, addr, v);
152 // tell other modules we are "outputing" a byte
153 if (avr_regbit_get(avr, p->txen))
154 avr_raise_irq(p->io.irq + UART_IRQ_OUTPUT, v);
156 if (addr == p->udrc.enable.reg) {
158 * If enabling the UDRC interrupt, raise it immediately if FIFO is empty
160 uint8_t udrce = avr_regbit_get(avr, p->udrc.enable);
161 avr_core_watch_write(avr, addr, v);
162 uint8_t nudrce = avr_regbit_get(avr, p->udrc.enable);
163 if (!udrce && nudrce) {
164 // if the FIDO is not empty (clear timer is flying) we don't
165 // need to raise the interrupt, it will happen when the timer
167 if (avr_cycle_timer_status(avr, avr_uart_txc_raise, p) == 0)
168 avr_raise_interrupt(avr, &p->udrc);
171 if (addr == p->udrc.raised.reg) {
172 // get the bits before the write
173 //uint8_t udre = avr_regbit_get(avr, p->udrc.raised);
174 uint8_t txc = avr_regbit_get(avr, p->txc.raised);
176 // no need to write this value in here, only the
177 // interrupt flags need clearing!
178 // avr_core_watch_write(avr, addr, v);
180 //avr_clear_interrupt_if(avr, &p->udrc, udre);
181 avr_clear_interrupt_if(avr, &p->txc, txc);
185 static void avr_uart_irq_input(struct avr_irq_t * irq, uint32_t value, void * param)
187 avr_uart_t * p = (avr_uart_t *)param;
188 avr_t * avr = p->io.avr;
190 // check to see fi receiver is enabled
191 if (!avr_regbit_get(avr, p->rxen))
194 if (uart_fifo_isempty(&p->input))
195 avr_cycle_timer_register_usec(avr, p->usec_per_byte, avr_uart_rxc_raise, p); // should be uart speed dependent
196 uart_fifo_write(&p->input, value); // add to fifo
198 // printf("UART IRQ in %02x (%d/%d) %s\n", value, p->input.read, p->input.write, uart_fifo_isfull(&p->input) ? "FULL!!" : "");
200 avr_raise_irq(p->io.irq + UART_IRQ_OUT_XOFF, uart_fifo_isfull(&p->input) != 0);
204 void avr_uart_reset(struct avr_io_t *io)
206 avr_uart_t * p = (avr_uart_t *)io;
207 avr_t * avr = p->io.avr;
208 avr_regbit_set(avr, p->udrc.raised);
209 avr_irq_register_notify(p->io.irq + UART_IRQ_INPUT, avr_uart_irq_input, p);
210 avr_cycle_timer_cancel(avr, avr_uart_rxc_raise, p);
211 avr_cycle_timer_cancel(avr, avr_uart_txc_raise, p);
212 uart_fifo_reset(&p->input);
214 // DEBUG allow printf without fidding with enabling the uart
215 avr_regbit_set(avr, p->txen);
216 p->usec_per_byte = 100;
219 static int avr_uart_ioctl(struct avr_io_t * port, uint32_t ctl, void * io_param)
221 avr_uart_t * p = (avr_uart_t *)port;
227 if (ctl == AVR_IOCTL_UART_SET_FLAGS(p->name)) {
228 p->flags = *(uint32_t*)io_param;
231 if (ctl == AVR_IOCTL_UART_GET_FLAGS(p->name)) {
232 *(uint32_t*)io_param = p->flags;
239 static const char * irq_names[UART_IRQ_COUNT] = {
240 [UART_IRQ_INPUT] = "8<in",
241 [UART_IRQ_OUTPUT] = "8>out",
242 [UART_IRQ_OUT_XON] = ">xon",
243 [UART_IRQ_OUT_XOFF] = ">xoff",
246 static avr_io_t _io = {
248 .reset = avr_uart_reset,
249 .ioctl = avr_uart_ioctl,
250 .irq_names = irq_names,
253 void avr_uart_init(avr_t * avr, avr_uart_t * p)
257 // printf("%s UART%c UDR=%02x\n", __FUNCTION__, p->name, p->r_udr);
259 p->flags = AVR_UART_FLAG_POOL_SLEEP|AVR_UART_FLAG_STDIO;
261 avr_register_io(avr, &p->io);
262 avr_register_vector(avr, &p->rxc);
263 avr_register_vector(avr, &p->txc);
264 avr_register_vector(avr, &p->udrc);
266 // allocate this module's IRQ
267 avr_io_setirqs(&p->io, AVR_IOCTL_UART_GETIRQ(p->name), UART_IRQ_COUNT, NULL);
268 // Only call callbacks when the value change...
269 p->io.irq[UART_IRQ_OUT_XOFF].flags |= IRQ_FLAG_FILTERED;
270 p->io.irq[UART_IRQ_OUT_XON].flags |= IRQ_FLAG_FILTERED;
272 avr_register_io_write(avr, p->r_udr, avr_uart_write, p);
273 avr_register_io_write(avr, p->udrc.enable.reg, avr_uart_write, p);
274 avr_register_io_read(avr, p->r_udr, avr_uart_read, p);
275 // monitor code that reads the rxc flag, and delay it a bit
276 avr_register_io_read(avr, p->rxc.raised.reg, avr_uart_rxc_read, p);
278 avr_register_io_write(avr, p->r_ucsra, avr_uart_write, p);
279 avr_register_io_write(avr, p->r_ubrrl, avr_uart_baud_write, p);