4 Copyright 2008, 2009 Michel Pollet <buserror@gmail.com>
6 This file is part of simavr.
8 simavr is free software: you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation, either version 3 of the License, or
11 (at your option) any later version.
13 simavr is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with simavr. If not, see <http://www.gnu.org/licenses/>.
29 #include "avr_flash.h"
30 #include "avr_watchdog.h"
33 const char * _sreg_bit_name = "cznvshti";
36 * Handle "touching" registers, marking them changed.
37 * This is used only for debugging purposes to be able to
38 * print the effects of each instructions on registers
40 #if CONFIG_SIMAVR_TRACE
44 #define REG_TOUCH(a, r) (a)->trace_data->touched[(r) >> 5] |= (1 << ((r) & 0x1f))
45 #define REG_ISTOUCHED(a, r) ((a)->trace_data->touched[(r) >> 5] & (1 << ((r) & 0x1f)))
48 * This allows a "special case" to skip instruction tracing when in these
49 * symbols since printf() is useful to have, but generates a lot of cycles.
51 int dont_trace(const char * name)
54 !strcmp(name, "uart_putchar") ||
55 !strcmp(name, "fputc") ||
56 !strcmp(name, "printf") ||
57 !strcmp(name, "vfprintf") ||
58 !strcmp(name, "__ultoa_invert") ||
59 !strcmp(name, "__prologue_saves__") ||
60 !strcmp(name, "__epilogue_restores__"));
65 #define STATE(_f, args...) { \
67 if (avr->trace_data->codeline && avr->trace_data->codeline[avr->pc>>1]) {\
68 const char * symn = avr->trace_data->codeline[avr->pc>>1]->symbol; \
69 int dont = 0 && dont_trace(symn);\
70 if (dont!=donttrace) { \
75 printf("%04x: %-25s " _f, avr->pc, symn, ## args);\
77 printf("%s: %04x: " _f, __FUNCTION__, avr->pc, ## args);\
80 #define SREG() if (avr->trace && donttrace == 0) {\
81 printf("%04x: \t\t\t\t\t\t\t\t\tSREG = ", avr->pc); \
82 for (int _sbi = 0; _sbi < 8; _sbi++)\
83 printf("%c", avr->sreg[_sbi] ? toupper(_sreg_bit_name[_sbi]) : '.');\
88 #define REG_TOUCH(a, r)
89 #define STATE(_f, args...)
93 void avr_core_watch_write(avr_t *avr, uint16_t addr, uint8_t v)
95 if (addr > avr->ramend) {
96 AVR_LOG(avr, LOG_ERROR, "CORE: *** Invalid write address PC=%04x SP=%04x O=%04x Address %04x=%02x out of ram\n",
97 avr->pc, _avr_sp_get(avr), avr->flash[avr->pc + 1] | (avr->flash[avr->pc]<<8), addr, v);
101 AVR_LOG(avr, LOG_ERROR, "CORE: *** Invalid write address PC=%04x SP=%04x O=%04x Address %04x=%02x low registers\n",
102 avr->pc, _avr_sp_get(avr), avr->flash[avr->pc + 1] | (avr->flash[avr->pc]<<8), addr, v);
107 * this checks that the current "function" is not doctoring the stack frame that is located
108 * higher on the stack than it should be. It's a sign of code that has overrun it's stack
109 * frame and is munching on it's own return address.
111 if (avr->trace_data->stack_frame_index > 1 && addr > avr->trace_data->stack_frame[avr->trace_data->stack_frame_index-2].sp) {
112 printf( FONT_RED "%04x : munching stack SP %04x, A=%04x <= %02x\n" FONT_DEFAULT, avr->pc, _avr_sp_get(avr), addr, v);
117 avr_gdb_handle_watchpoints(avr, addr, AVR_GDB_WATCH_WRITE);
123 uint8_t avr_core_watch_read(avr_t *avr, uint16_t addr)
125 if (addr > avr->ramend) {
126 AVR_LOG(avr, LOG_ERROR, FONT_RED "CORE: *** Invalid read address PC=%04x SP=%04x O=%04x Address %04x out of ram (%04x)\n" FONT_DEFAULT,
127 avr->pc, _avr_sp_get(avr), avr->flash[avr->pc + 1] | (avr->flash[avr->pc]<<8), addr, avr->ramend);
132 avr_gdb_handle_watchpoints(avr, addr, AVR_GDB_WATCH_READ);
135 return avr->data[addr];
139 * Set a register (r < 256)
140 * if it's an IO register (> 31) also (try to) call any callback that was
141 * registered to track changes to that register.
143 static inline void _avr_set_r(avr_t * avr, uint8_t r, uint8_t v)
148 avr->data[R_SREG] = v;
150 SET_SREG_FROM(avr, v);
154 uint8_t io = AVR_DATA_TO_IO(r);
156 avr->io[io].w.c(avr, r, v, avr->io[io].w.param);
159 if (avr->io[io].irq) {
160 avr_raise_irq(avr->io[io].irq + AVR_IOMEM_IRQ_ALL, v);
161 for (int i = 0; i < 8; i++)
162 avr_raise_irq(avr->io[io].irq + i, (v >> i) & 1);
169 * Stack pointer access
171 inline uint16_t _avr_sp_get(avr_t * avr)
173 return avr->data[R_SPL] | (avr->data[R_SPH] << 8);
176 inline void _avr_sp_set(avr_t * avr, uint16_t sp)
178 _avr_set_r(avr, R_SPL, sp);
179 _avr_set_r(avr, R_SPH, sp >> 8);
183 * Set any address to a value; split between registers and SRAM
185 static inline void _avr_set_ram(avr_t * avr, uint16_t addr, uint8_t v)
188 _avr_set_r(avr, addr, v);
190 avr_core_watch_write(avr, addr, v);
194 * Get a value from SRAM.
196 static inline uint8_t _avr_get_ram(avr_t * avr, uint16_t addr)
198 if (addr == R_SREG) {
200 * SREG is special it's reconstructed when read
201 * while the core itself uses the "shortcut" array
203 READ_SREG_INTO(avr, avr->data[R_SREG]);
205 } else if (addr > 31 && addr < 256) {
206 uint8_t io = AVR_DATA_TO_IO(addr);
209 avr->data[addr] = avr->io[io].r.c(avr, addr, avr->io[io].r.param);
211 if (avr->io[io].irq) {
212 uint8_t v = avr->data[addr];
213 avr_raise_irq(avr->io[io].irq + AVR_IOMEM_IRQ_ALL, v);
214 for (int i = 0; i < 8; i++)
215 avr_raise_irq(avr->io[io].irq + i, (v >> i) & 1);
218 return avr_core_watch_read(avr, addr);
222 * Stack push accessors. Push/pop 8 and 16 bits
224 static inline void _avr_push8(avr_t * avr, uint16_t v)
226 uint16_t sp = _avr_sp_get(avr);
227 _avr_set_ram(avr, sp, v);
228 _avr_sp_set(avr, sp-1);
231 static inline uint8_t _avr_pop8(avr_t * avr)
233 uint16_t sp = _avr_sp_get(avr) + 1;
234 uint8_t res = _avr_get_ram(avr, sp);
235 _avr_sp_set(avr, sp);
239 inline void _avr_push16(avr_t * avr, uint16_t v)
242 _avr_push8(avr, v >> 8);
245 static inline uint16_t _avr_pop16(avr_t * avr)
247 uint16_t res = _avr_pop8(avr) << 8;
248 res |= _avr_pop8(avr);
253 * "Pretty" register names
255 const char * reg_names[255] = {
256 [R_XH] = "XH", [R_XL] = "XL",
257 [R_YH] = "YH", [R_YL] = "YL",
258 [R_ZH] = "ZH", [R_ZL] = "ZL",
259 [R_SPH] = "SPH", [R_SPL] = "SPL",
264 const char * avr_regname(uint8_t reg)
266 if (!reg_names[reg]) {
269 sprintf(tt, "r%d", reg);
271 sprintf(tt, "io:%02x", reg);
272 reg_names[reg] = strdup(tt);
274 return reg_names[reg];
278 * Called when an invalid opcode is decoded
280 static void _avr_invalid_opcode(avr_t * avr)
282 #if CONFIG_SIMAVR_TRACE
283 printf( FONT_RED "*** %04x: %-25s Invalid Opcode SP=%04x O=%04x \n" FONT_DEFAULT,
284 avr->pc, avr->trace_data->codeline[avr->pc>>1]->symbol, _avr_sp_get(avr), avr->flash[avr->pc] | (avr->flash[avr->pc+1]<<8));
286 AVR_LOG(avr, LOG_ERROR, FONT_RED "CORE: *** %04x: Invalid Opcode SP=%04x O=%04x \n" FONT_DEFAULT,
287 avr->pc, _avr_sp_get(avr), avr->flash[avr->pc] | (avr->flash[avr->pc+1]<<8));
291 #if CONFIG_SIMAVR_TRACE
293 * Dump changed registers when tracing
295 void avr_dump_state(avr_t * avr)
297 if (!avr->trace || donttrace)
302 for (int r = 0; r < 3 && !doit; r++)
303 if (avr->trace_data->touched[r])
308 const int r16[] = { R_SPL, R_XL, R_YL, R_ZL };
309 for (int i = 0; i < 4; i++)
310 if (REG_ISTOUCHED(avr, r16[i]) || REG_ISTOUCHED(avr, r16[i]+1)) {
311 REG_TOUCH(avr, r16[i]);
312 REG_TOUCH(avr, r16[i]+1);
315 for (int i = 0; i < 3*32; i++)
316 if (REG_ISTOUCHED(avr, i)) {
317 printf("%s=%02x ", avr_regname(i), avr->data[i]);
323 #define get_r_d_10(o) \
324 const uint8_t r = ((o >> 5) & 0x10) | (o & 0xf); \
325 const uint8_t d = (o >> 4) & 0x1f;\
326 const uint8_t vd = avr->data[d], vr = avr->data[r];
327 #define get_r_dd_10(o) \
328 const uint8_t r = ((o >> 5) & 0x10) | (o & 0xf); \
329 const uint8_t d = (o >> 4) & 0x1f;\
330 const uint8_t vr = avr->data[r];
331 #define get_k_r16(o) \
332 const uint8_t r = 16 + ((o >> 4) & 0xf); \
333 const uint8_t k = ((o & 0x0f00) >> 4) | (o & 0xf);
336 * Add a "jump" address to the jump trace buffer
338 #if CONFIG_SIMAVR_TRACE
339 #define TRACE_JUMP()\
340 avr->trace_data->old[avr->trace_data->old_pci].pc = avr->pc;\
341 avr->trace_data->old[avr->trace_data->old_pci].sp = _avr_sp_get(avr);\
342 avr->trace_data->old_pci = (avr->trace_data->old_pci + 1) & (OLD_PC_SIZE-1);\
345 #define STACK_FRAME_PUSH()\
346 avr->trace_data->stack_frame[avr->trace_data->stack_frame_index].pc = avr->pc;\
347 avr->trace_data->stack_frame[avr->trace_data->stack_frame_index].sp = _avr_sp_get(avr);\
348 avr->trace_data->stack_frame_index++;
349 #define STACK_FRAME_POP()\
350 if (avr->trace_data->stack_frame_index > 0) \
351 avr->trace_data->stack_frame_index--;
353 #define STACK_FRAME_PUSH()
354 #define STACK_FRAME_POP()
356 #else /* CONFIG_SIMAVR_TRACE */
359 #define STACK_FRAME_PUSH()
360 #define STACK_FRAME_POP()
364 /****************************************************************************\
366 * Helper functions for calculating the status register bit values.
367 * See the Atmel data sheet for the instruction set for more info.
369 \****************************************************************************/
372 get_add_carry (uint8_t res, uint8_t rd, uint8_t rr, int b)
374 uint8_t resb = res >> b & 0x1;
375 uint8_t rdb = rd >> b & 0x1;
376 uint8_t rrb = rr >> b & 0x1;
377 return (rdb & rrb) | (rrb & ~resb) | (~resb & rdb);
381 get_add_overflow (uint8_t res, uint8_t rd, uint8_t rr)
383 uint8_t res7 = res >> 7 & 0x1;
384 uint8_t rd7 = rd >> 7 & 0x1;
385 uint8_t rr7 = rr >> 7 & 0x1;
386 return (rd7 & rr7 & ~res7) | (~rd7 & ~rr7 & res7);
390 get_sub_carry (uint8_t res, uint8_t rd, uint8_t rr, int b)
392 uint8_t resb = res >> b & 0x1;
393 uint8_t rdb = rd >> b & 0x1;
394 uint8_t rrb = rr >> b & 0x1;
395 return (~rdb & rrb) | (rrb & resb) | (resb & ~rdb);
399 get_sub_overflow (uint8_t res, uint8_t rd, uint8_t rr)
401 uint8_t res7 = res >> 7 & 0x1;
402 uint8_t rd7 = rd >> 7 & 0x1;
403 uint8_t rr7 = rr >> 7 & 0x1;
404 return (rd7 & ~rr7 & ~res7) | (~rd7 & rr7 & res7);
408 get_compare_carry (uint8_t res, uint8_t rd, uint8_t rr, int b)
410 uint8_t resb = (res >> b) & 0x1;
411 uint8_t rdb = (rd >> b) & 0x1;
412 uint8_t rrb = (rr >> b) & 0x1;
413 return (~rdb & rrb) | (rrb & resb) | (resb & ~rdb);
417 get_compare_overflow (uint8_t res, uint8_t rd, uint8_t rr)
419 res >>= 7; rd >>= 7; rr >>= 7;
420 /* The atmel data sheet says the second term is ~rd7 for CP
421 * but that doesn't make any sense. You be the judge. */
422 return (rd & ~rr & ~res) | (~rd & rr & res);
425 static inline int _avr_is_instruction_32_bits(avr_t * avr, avr_flashaddr_t pc)
427 uint16_t o = (avr->flash[pc] | (avr->flash[pc+1] << 8)) & 0xfc0f;
428 return o == 0x9200 || // STS ! Store Direct to Data Space
429 o == 0x9000 || // LDS Load Direct from Data Space
430 o == 0x940c || // JMP Long Jump
431 o == 0x940d || // JMP Long Jump
432 o == 0x940e || // CALL Long Call to sub
433 o == 0x940f; // CALL Long Call to sub
437 * Main opcode decoder
439 * The decoder was written by following the datasheet in no particular order.
440 * As I went along, I noticed "bit patterns" that could be used to factor opcodes
441 * However, a lot of these only became apparent later on, so SOME instructions
442 * (skip of bit set etc) are compact, and some could use some refactoring (the ALU
443 * ones scream to be factored).
444 * I assume that the decoder could easily be 2/3 of it's current size.
446 * + It lacks the "extended" XMega jumps.
447 * + It also doesn't check whether the core it's
448 * emulating is supposed to have the fancy instructions, like multiply and such.
450 * The number of cycles taken by instruction has been added, but might not be
453 avr_flashaddr_t avr_run_one(avr_t * avr)
455 #if CONFIG_SIMAVR_TRACE
457 * this traces spurious reset or bad jumps
459 if ((avr->pc == 0 && avr->cycle > 0) || avr->pc >= avr->codeend) {
464 avr->trace_data->touched[0] = avr->trace_data->touched[1] = avr->trace_data->touched[2] = 0;
467 uint32_t opcode = (avr->flash[avr->pc + 1] << 8) | avr->flash[avr->pc];
468 avr_flashaddr_t new_pc = avr->pc + 2; // future "default" pc
471 switch (opcode & 0xf000) {
474 case 0x0000: { // NOP
478 switch (opcode & 0xfc00) {
479 case 0x0400: { // CPC compare with carry 0000 01rd dddd rrrr
481 uint8_t res = vd - vr - avr->sreg[S_C];
482 STATE("cpc %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res);
485 avr->sreg[S_H] = get_compare_carry(res, vd, vr, 3);
486 avr->sreg[S_V] = get_compare_overflow(res, vd, vr);
487 avr->sreg[S_N] = (res >> 7) & 1;
488 avr->sreg[S_C] = get_compare_carry(res, vd, vr, 7);
489 avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
492 case 0x0c00: { // ADD without carry 0000 11 rd dddd rrrr
494 uint8_t res = vd + vr;
496 STATE("lsl %s[%02x] = %02x\n", avr_regname(d), vd, res & 0xff);
498 STATE("add %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res);
500 _avr_set_r(avr, d, res);
501 avr->sreg[S_Z] = res == 0;
502 avr->sreg[S_H] = get_add_carry(res, vd, vr, 3);
503 avr->sreg[S_V] = get_add_overflow(res, vd, vr);
504 avr->sreg[S_N] = (res >> 7) & 1;
505 avr->sreg[S_C] = get_add_carry(res, vd, vr, 7);
506 avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
509 case 0x0800: { // SBC subtract with carry 0000 10rd dddd rrrr
511 uint8_t res = vd - vr - avr->sreg[S_C];
512 STATE("sbc %s[%02x], %s[%02x] = %02x\n", avr_regname(d), avr->data[d], avr_regname(r), avr->data[r], res);
513 _avr_set_r(avr, d, res);
516 avr->sreg[S_H] = get_sub_carry(res, vd, vr, 3);
517 avr->sreg[S_V] = get_sub_overflow(res, vd, vr);
518 avr->sreg[S_N] = (res >> 7) & 1;
519 avr->sreg[S_C] = get_sub_carry(res, vd, vr, 7);
520 avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
524 switch (opcode & 0xff00) {
525 case 0x0100: { // MOVW – Copy Register Word 0000 0001 dddd rrrr
526 uint8_t d = ((opcode >> 4) & 0xf) << 1;
527 uint8_t r = ((opcode) & 0xf) << 1;
528 STATE("movw %s:%s, %s:%s[%02x%02x]\n", avr_regname(d), avr_regname(d+1), avr_regname(r), avr_regname(r+1), avr->data[r+1], avr->data[r]);
529 _avr_set_r(avr, d, avr->data[r]);
530 _avr_set_r(avr, d+1, avr->data[r+1]);
532 case 0x0200: { // MULS – Multiply Signed 0000 0010 dddd rrrr
533 int8_t r = 16 + (opcode & 0xf);
534 int8_t d = 16 + ((opcode >> 4) & 0xf);
535 int16_t res = ((int8_t)avr->data[r]) * ((int8_t)avr->data[d]);
536 STATE("muls %s[%d], %s[%02x] = %d\n", avr_regname(d), ((int8_t)avr->data[d]), avr_regname(r), ((int8_t)avr->data[r]), res);
537 _avr_set_r(avr, 0, res);
538 _avr_set_r(avr, 1, res >> 8);
539 avr->sreg[S_C] = (res >> 15) & 1;
540 avr->sreg[S_Z] = res == 0;
543 case 0x0300: { // MUL Multiply 0000 0011 fddd frrr
544 int8_t r = 16 + (opcode & 0x7);
545 int8_t d = 16 + ((opcode >> 4) & 0x7);
548 T(const char * name = "";)
549 switch (opcode & 0x88) {
550 case 0x00: // MULSU – Multiply Signed Unsigned 0000 0011 0ddd 0rrr
551 res = ((uint8_t)avr->data[r]) * ((int8_t)avr->data[d]);
555 case 0x08: // FMUL Fractional Multiply Unsigned 0000 0011 0ddd 1rrr
556 res = ((uint8_t)avr->data[r]) * ((uint8_t)avr->data[d]);
561 case 0x80: // FMULS – Multiply Signed 0000 0011 1ddd 0rrr
562 res = ((int8_t)avr->data[r]) * ((int8_t)avr->data[d]);
567 case 0x88: // FMULSU – Multiply Signed Unsigned 0000 0011 1ddd 1rrr
568 res = ((uint8_t)avr->data[r]) * ((int8_t)avr->data[d]);
575 STATE("%s %s[%d], %s[%02x] = %d\n", name, avr_regname(d), ((int8_t)avr->data[d]), avr_regname(r), ((int8_t)avr->data[r]), res);
576 _avr_set_r(avr, 0, res);
577 _avr_set_r(avr, 1, res >> 8);
579 avr->sreg[S_Z] = res == 0;
582 default: _avr_invalid_opcode(avr);
590 switch (opcode & 0xfc00) {
591 case 0x1800: { // SUB without carry 0000 10 rd dddd rrrr
593 uint8_t res = vd - vr;
594 STATE("sub %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res);
595 _avr_set_r(avr, d, res);
596 avr->sreg[S_Z] = res == 0;
597 avr->sreg[S_H] = get_sub_carry(res, vd, vr, 3);
598 avr->sreg[S_V] = get_sub_overflow(res, vd, vr);
599 avr->sreg[S_N] = (res >> 7) & 1;
600 avr->sreg[S_C] = get_sub_carry(res, vd, vr, 7);
601 avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
604 case 0x1000: { // CPSE Compare, skip if equal 0000 00 rd dddd rrrr
606 uint16_t res = vd == vr;
607 STATE("cpse %s[%02x], %s[%02x]\t; Will%s skip\n", avr_regname(d), avr->data[d], avr_regname(r), avr->data[r], res ? "":" not");
609 if (_avr_is_instruction_32_bits(avr, new_pc)) {
610 new_pc += 4; cycle += 2;
612 new_pc += 2; cycle++;
616 case 0x1400: { // CP Compare 0000 01 rd dddd rrrr
618 uint8_t res = vd - vr;
619 STATE("cp %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res);
620 avr->sreg[S_Z] = res == 0;
621 avr->sreg[S_H] = get_compare_carry(res, vd, vr, 3);
622 avr->sreg[S_V] = get_compare_overflow(res, vd, vr);
623 avr->sreg[S_N] = res >> 7;
624 avr->sreg[S_C] = get_compare_carry(res, vd, vr, 7);
625 avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
628 case 0x1c00: { // ADD with carry 0001 11 rd dddd rrrr
630 uint8_t res = vd + vr + avr->sreg[S_C];
632 STATE("rol %s[%02x] = %02x\n", avr_regname(d), avr->data[d], res);
634 STATE("addc %s[%02x], %s[%02x] = %02x\n", avr_regname(d), avr->data[d], avr_regname(r), avr->data[r], res);
636 _avr_set_r(avr, d, res);
637 avr->sreg[S_Z] = res == 0;
638 avr->sreg[S_H] = get_add_carry(res, vd, vr, 3);
639 avr->sreg[S_V] = get_add_overflow(res, vd, vr);
640 avr->sreg[S_N] = (res >> 7) & 1;
641 avr->sreg[S_C] = get_add_carry(res, vd, vr, 7);
642 avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
645 default: _avr_invalid_opcode(avr);
650 switch (opcode & 0xfc00) {
651 case 0x2000: { // AND 0010 00rd dddd rrrr
653 uint8_t res = vd & vr;
655 STATE("tst %s[%02x]\n", avr_regname(d), avr->data[d]);
657 STATE("and %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res);
659 _avr_set_r(avr, d, res);
660 avr->sreg[S_Z] = res == 0;
661 avr->sreg[S_N] = (res >> 7) & 1;
663 avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
666 case 0x2400: { // EOR 0010 01rd dddd rrrr
668 uint8_t res = vd ^ vr;
670 STATE("clr %s[%02x]\n", avr_regname(d), avr->data[d]);
672 STATE("eor %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res);
674 _avr_set_r(avr, d, res);
675 avr->sreg[S_Z] = res == 0;
676 avr->sreg[S_N] = (res >> 7) & 1;
678 avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
681 case 0x2800: { // OR Logical OR 0010 10rd dddd rrrr
683 uint8_t res = vd | vr;
684 STATE("or %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res);
685 _avr_set_r(avr, d, res);
686 avr->sreg[S_Z] = res == 0;
687 avr->sreg[S_N] = (res >> 7) & 1;
689 avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
692 case 0x2c00: { // MOV 0010 11rd dddd rrrr
695 STATE("mov %s, %s[%02x] = %02x\n", avr_regname(d), avr_regname(r), vr, res);
696 _avr_set_r(avr, d, res);
698 default: _avr_invalid_opcode(avr);
702 case 0x3000: { // CPI 0011 KKKK rrrr KKKK
704 uint8_t vr = avr->data[r];
705 uint8_t res = vr - k;
706 STATE("cpi %s[%02x], 0x%02x\n", avr_regname(r), vr, k);
708 avr->sreg[S_Z] = res == 0;
709 avr->sreg[S_H] = get_compare_carry(res, vr, k, 3);
710 avr->sreg[S_V] = get_compare_overflow(res, vr, k);
711 avr->sreg[S_N] = (res >> 7) & 1;
712 avr->sreg[S_C] = get_compare_carry(res, vr, k, 7);
713 avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
717 case 0x4000: { // SBCI Subtract Immediate With Carry 0101 10 kkkk dddd kkkk
719 uint8_t vr = avr->data[r];
720 uint8_t res = vr - k - avr->sreg[S_C];
721 STATE("sbci %s[%02x], 0x%02x = %02x\n", avr_regname(r), avr->data[r], k, res);
722 _avr_set_r(avr, r, res);
725 avr->sreg[S_N] = (res >> 7) & 1;
726 avr->sreg[S_C] = (k + avr->sreg[S_C]) > vr;
727 avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
731 case 0x5000: { // SUB Subtract Immediate 0101 10 kkkk dddd kkkk
733 uint8_t vr = avr->data[r];
734 uint8_t res = vr - k;
735 STATE("subi %s[%02x], 0x%02x = %02x\n", avr_regname(r), avr->data[r], k, res);
736 _avr_set_r(avr, r, res);
737 avr->sreg[S_Z] = res == 0;
738 avr->sreg[S_N] = (res >> 7) & 1;
739 avr->sreg[S_C] = k > vr;
740 avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
744 case 0x6000: { // ORI aka SBR Logical AND with Immediate 0110 kkkk dddd kkkk
746 uint8_t res = avr->data[r] | k;
747 STATE("ori %s[%02x], 0x%02x\n", avr_regname(r), avr->data[r], k);
748 _avr_set_r(avr, r, res);
749 avr->sreg[S_Z] = res == 0;
750 avr->sreg[S_N] = (res >> 7) & 1;
752 avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
756 case 0x7000: { // ANDI Logical AND with Immediate 0111 kkkk dddd kkkk
758 uint8_t res = avr->data[r] & k;
759 STATE("andi %s[%02x], 0x%02x\n", avr_regname(r), avr->data[r], k);
760 _avr_set_r(avr, r, res);
761 avr->sreg[S_Z] = res == 0;
762 avr->sreg[S_N] = (res >> 7) & 1;
764 avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
770 switch (opcode & 0xd008) {
772 case 0x8000: { // LD (LDD) – Load Indirect using Z 10q0 qq0r rrrr 0qqq
773 uint16_t v = avr->data[R_ZL] | (avr->data[R_ZH] << 8);
774 uint8_t r = (opcode >> 4) & 0x1f;
775 uint8_t q = ((opcode & 0x2000) >> 8) | ((opcode & 0x0c00) >> 7) | (opcode & 0x7);
777 if (opcode & 0x0200) {
778 STATE("st (Z+%d[%04x]), %s[%02x]\n", q, v+q, avr_regname(r), avr->data[r]);
779 _avr_set_ram(avr, v+q, avr->data[r]);
781 STATE("ld %s, (Z+%d[%04x])=[%02x]\n", avr_regname(r), q, v+q, avr->data[v+q]);
782 _avr_set_r(avr, r, _avr_get_ram(avr, v+q));
784 cycle += 1; // 2 cycles, 3 for tinyavr
787 case 0x8008: { // LD (LDD) – Load Indirect using Y 10q0 qq0r rrrr 1qqq
788 uint16_t v = avr->data[R_YL] | (avr->data[R_YH] << 8);
789 uint8_t r = (opcode >> 4) & 0x1f;
790 uint8_t q = ((opcode & 0x2000) >> 8) | ((opcode & 0x0c00) >> 7) | (opcode & 0x7);
792 if (opcode & 0x0200) {
793 STATE("st (Y+%d[%04x]), %s[%02x]\n", q, v+q, avr_regname(r), avr->data[r]);
794 _avr_set_ram(avr, v+q, avr->data[r]);
796 STATE("ld %s, (Y+%d[%04x])=[%02x]\n", avr_regname(r), q, v+q, avr->data[v+q]);
797 _avr_set_r(avr, r, _avr_get_ram(avr, v+q));
799 cycle += 1; // 2 cycles, 3 for tinyavr
801 default: _avr_invalid_opcode(avr);
806 /* this is an annoying special case, but at least these lines handle all the SREG set/clear opcodes */
807 if ((opcode & 0xff0f) == 0x9408) {
808 uint8_t b = (opcode >> 4) & 7;
809 STATE("%s%c\n", opcode & 0x0080 ? "cl" : "se", _sreg_bit_name[b]);
810 avr->sreg[b] = (opcode & 0x0080) == 0;
812 } else switch (opcode) {
813 case 0x9588: { // SLEEP
815 /* Don't sleep if there are interrupts about to be serviced.
816 * Without this check, it was possible to incorrectly enter a state
817 * in which the cpu was sleeping and interrupts were disabled. For more
818 * details, see the commit message. */
819 if (!avr_has_pending_interrupts(avr) || !avr->sreg[S_I])
820 avr->state = cpu_Sleeping;
822 case 0x9598: { // BREAK
825 // if gdb is on, we break here as in here
826 // and we do so until gdb restores the instruction
827 // that was here before
828 avr->state = cpu_StepDone;
833 case 0x95a8: { // WDR
835 avr_ioctl(avr, AVR_IOCTL_WATCHDOG_RESET, 0);
837 case 0x95e8: { // SPM
839 avr_ioctl(avr, AVR_IOCTL_FLASH_SPM, 0);
841 case 0x9409: // IJMP Indirect jump 1001 0100 0000 1001
842 case 0x9419: // EIJMP Indirect jump 1001 0100 0001 1001 bit 4 is "indirect"
843 case 0x9509: // ICALL Indirect Call to Subroutine 1001 0101 0000 1001
844 case 0x9519: { // EICALL Indirect Call to Subroutine 1001 0101 0001 1001 bit 8 is "push pc"
845 int e = opcode & 0x10;
846 int p = opcode & 0x100;
848 _avr_invalid_opcode(avr);
849 uint16_t z = avr->data[R_ZL] | (avr->data[R_ZH] << 8);
851 z |= avr->data[avr->eind] << 16;
852 STATE("%si%s Z[%04x]\n", e?"e":"", p?"call":"jmp", z << 1);
855 _avr_push16(avr, new_pc >> 1);
862 case 0x9508: { // RET
863 new_pc = _avr_pop16(avr) << 1;
864 if (opcode & 0x10) // reti
867 STATE("ret%s\n", opcode & 0x10 ? "i" : "");
871 case 0x95c8: { // LPM Load Program Memory R0 <- (Z)
872 uint16_t z = avr->data[R_ZL] | (avr->data[R_ZH] << 8);
873 STATE("lpm %s, (Z[%04x])\n", avr_regname(0), z);
874 cycle += 2; // 3 cycles
875 _avr_set_r(avr, 0, avr->flash[z]);
877 case 0x9408:case 0x9418:case 0x9428:case 0x9438:case 0x9448:case 0x9458:case 0x9468:
879 { // BSET 1001 0100 0ddd 1000
880 uint8_t b = (opcode >> 4) & 7;
882 STATE("bset %c\n", _sreg_bit_name[b]);
885 case 0x9488:case 0x9498:case 0x94a8:case 0x94b8:case 0x94c8:case 0x94d8:case 0x94e8:
886 case 0x94f8: // bit 7 is 'clear vs set'
887 { // BCLR 1001 0100 1ddd 1000
888 uint8_t b = (opcode >> 4) & 7;
890 STATE("bclr %c\n", _sreg_bit_name[b]);
894 switch (opcode & 0xfe0f) {
895 case 0x9000: { // LDS Load Direct from Data Space, 32 bits
896 uint8_t r = (opcode >> 4) & 0x1f;
897 uint16_t x = (avr->flash[new_pc+1] << 8) | avr->flash[new_pc];
899 STATE("lds %s[%02x], 0x%04x\n", avr_regname(r), avr->data[r], x);
900 _avr_set_r(avr, r, _avr_get_ram(avr, x));
904 case 0x9004: { // LPM Load Program Memory 1001 000d dddd 01oo
905 uint16_t z = avr->data[R_ZL] | (avr->data[R_ZH] << 8);
906 uint8_t r = (opcode >> 4) & 0x1f;
908 STATE("lpm %s, (Z[%04x]%s)\n", avr_regname(r), z, opcode?"+":"");
909 _avr_set_r(avr, r, avr->flash[z]);
912 _avr_set_r(avr, R_ZH, z >> 8);
913 _avr_set_r(avr, R_ZL, z);
915 cycle += 2; // 3 cycles
918 case 0x9007: { // ELPM Extended Load Program Memory 1001 000d dddd 01oo
920 _avr_invalid_opcode(avr);
921 uint32_t z = avr->data[R_ZL] | (avr->data[R_ZH] << 8) | (avr->data[avr->rampz] << 16);
922 uint8_t r = (opcode >> 4) & 0x1f;
924 STATE("elpm %s, (Z[%02x:%04x]%s)\n", avr_regname(r), z >> 16, z&0xffff, opcode?"+":"");
925 _avr_set_r(avr, r, avr->flash[z]);
928 _avr_set_r(avr, avr->rampz, z >> 16);
929 _avr_set_r(avr, R_ZH, z >> 8);
930 _avr_set_r(avr, R_ZL, z);
932 cycle += 2; // 3 cycles
935 * Load store instructions
937 * 1001 00sr rrrr iioo
938 * s = 0 = load, 1 = store
939 * ii = 16 bits register index, 11 = Z, 10 = Y, 00 = X
940 * oo = 1) post increment, 2) pre-decrement
944 case 0x900e: { // LD Load Indirect from Data using X 1001 000r rrrr 11oo
946 uint8_t r = (opcode >> 4) & 0x1f;
947 uint16_t x = (avr->data[R_XH] << 8) | avr->data[R_XL];
948 STATE("ld %s, %sX[%04x]%s\n", avr_regname(r), op == 2 ? "--" : "", x, op == 1 ? "++" : "");
949 cycle++; // 2 cycles (1 for tinyavr, except with inc/dec 2)
951 _avr_set_r(avr, r, _avr_get_ram(avr, x));
953 _avr_set_r(avr, R_XH, x >> 8);
954 _avr_set_r(avr, R_XL, x);
958 case 0x920e: { // ST Store Indirect Data Space X 1001 001r rrrr 11oo
960 uint8_t r = (opcode >> 4) & 0x1f;
961 uint16_t x = (avr->data[R_XH] << 8) | avr->data[R_XL];
962 STATE("st %sX[%04x]%s, %s[%02x] \n", op == 2 ? "--" : "", x, op == 1 ? "++" : "", avr_regname(r), avr->data[r]);
963 cycle++; // 2 cycles, except tinyavr
965 _avr_set_ram(avr, x, avr->data[r]);
967 _avr_set_r(avr, R_XH, x >> 8);
968 _avr_set_r(avr, R_XL, x);
971 case 0x900a: { // LD Load Indirect from Data using Y 1001 000r rrrr 10oo
973 uint8_t r = (opcode >> 4) & 0x1f;
974 uint16_t y = (avr->data[R_YH] << 8) | avr->data[R_YL];
975 STATE("ld %s, %sY[%04x]%s\n", avr_regname(r), op == 2 ? "--" : "", y, op == 1 ? "++" : "");
976 cycle++; // 2 cycles, except tinyavr
978 _avr_set_r(avr, r, _avr_get_ram(avr, y));
980 _avr_set_r(avr, R_YH, y >> 8);
981 _avr_set_r(avr, R_YL, y);
984 case 0x920a: { // ST Store Indirect Data Space Y 1001 001r rrrr 10oo
986 uint8_t r = (opcode >> 4) & 0x1f;
987 uint16_t y = (avr->data[R_YH] << 8) | avr->data[R_YL];
988 STATE("st %sY[%04x]%s, %s[%02x]\n", op == 2 ? "--" : "", y, op == 1 ? "++" : "", avr_regname(r), avr->data[r]);
991 _avr_set_ram(avr, y, avr->data[r]);
993 _avr_set_r(avr, R_YH, y >> 8);
994 _avr_set_r(avr, R_YL, y);
996 case 0x9200: { // STS ! Store Direct to Data Space, 32 bits
997 uint8_t r = (opcode >> 4) & 0x1f;
998 uint16_t x = (avr->flash[new_pc+1] << 8) | avr->flash[new_pc];
1000 STATE("sts 0x%04x, %s[%02x]\n", x, avr_regname(r), avr->data[r]);
1002 _avr_set_ram(avr, x, avr->data[r]);
1005 case 0x9002: { // LD Load Indirect from Data using Z 1001 001r rrrr 00oo
1006 int op = opcode & 3;
1007 uint8_t r = (opcode >> 4) & 0x1f;
1008 uint16_t z = (avr->data[R_ZH] << 8) | avr->data[R_ZL];
1009 STATE("ld %s, %sZ[%04x]%s\n", avr_regname(r), op == 2 ? "--" : "", z, op == 1 ? "++" : "");
1010 cycle++;; // 2 cycles, except tinyavr
1012 _avr_set_r(avr, r, _avr_get_ram(avr, z));
1014 _avr_set_r(avr, R_ZH, z >> 8);
1015 _avr_set_r(avr, R_ZL, z);
1018 case 0x9202: { // ST Store Indirect Data Space Z 1001 001r rrrr 00oo
1019 int op = opcode & 3;
1020 uint8_t r = (opcode >> 4) & 0x1f;
1021 uint16_t z = (avr->data[R_ZH] << 8) | avr->data[R_ZL];
1022 STATE("st %sZ[%04x]%s, %s[%02x] \n", op == 2 ? "--" : "", z, op == 1 ? "++" : "", avr_regname(r), avr->data[r]);
1023 cycle++; // 2 cycles, except tinyavr
1025 _avr_set_ram(avr, z, avr->data[r]);
1027 _avr_set_r(avr, R_ZH, z >> 8);
1028 _avr_set_r(avr, R_ZL, z);
1030 case 0x900f: { // POP 1001 000d dddd 1111
1031 uint8_t r = (opcode >> 4) & 0x1f;
1032 _avr_set_r(avr, r, _avr_pop8(avr));
1033 T(uint16_t sp = _avr_sp_get(avr);)
1034 STATE("pop %s (@%04x)[%02x]\n", avr_regname(r), sp, avr->data[sp]);
1037 case 0x920f: { // PUSH 1001 001d dddd 1111
1038 uint8_t r = (opcode >> 4) & 0x1f;
1039 _avr_push8(avr, avr->data[r]);
1040 T(uint16_t sp = _avr_sp_get(avr);)
1041 STATE("push %s[%02x] (@%04x)\n", avr_regname(r), avr->data[r], sp);
1044 case 0x9400: { // COM – One’s Complement
1045 uint8_t r = (opcode >> 4) & 0x1f;
1046 uint8_t res = 0xff - avr->data[r];
1047 STATE("com %s[%02x] = %02x\n", avr_regname(r), avr->data[r], res);
1048 _avr_set_r(avr, r, res);
1049 avr->sreg[S_Z] = res == 0;
1050 avr->sreg[S_N] = res >> 7;
1053 avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
1056 case 0x9401: { // NEG – Two’s Complement
1057 uint8_t r = (opcode >> 4) & 0x1f;
1058 uint8_t rd = avr->data[r];
1059 uint8_t res = 0x00 - rd;
1060 STATE("neg %s[%02x] = %02x\n", avr_regname(r), rd, res);
1061 _avr_set_r(avr, r, res);
1062 avr->sreg[S_H] = ((res >> 3) | (rd >> 3)) & 1;
1063 avr->sreg[S_Z] = res == 0;
1064 avr->sreg[S_N] = res >> 7;
1065 avr->sreg[S_V] = res == 0x80;
1066 avr->sreg[S_C] = res != 0;
1067 avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
1070 case 0x9402: { // SWAP – Swap Nibbles
1071 uint8_t r = (opcode >> 4) & 0x1f;
1072 uint8_t res = (avr->data[r] >> 4) | (avr->data[r] << 4) ;
1073 STATE("swap %s[%02x] = %02x\n", avr_regname(r), avr->data[r], res);
1074 _avr_set_r(avr, r, res);
1076 case 0x9403: { // INC – Increment
1077 uint8_t r = (opcode >> 4) & 0x1f;
1078 uint8_t res = avr->data[r] + 1;
1079 STATE("inc %s[%02x] = %02x\n", avr_regname(r), avr->data[r], res);
1080 _avr_set_r(avr, r, res);
1081 avr->sreg[S_Z] = res == 0;
1082 avr->sreg[S_N] = res >> 7;
1083 avr->sreg[S_V] = res == 0x7f;
1084 avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
1087 case 0x9405: { // ASR – Arithmetic Shift Right 1001 010d dddd 0101
1088 uint8_t r = (opcode >> 4) & 0x1f;
1089 uint8_t vr = avr->data[r];
1090 uint8_t res = (vr >> 1) | (vr & 0x80);
1091 STATE("asr %s[%02x]\n", avr_regname(r), vr);
1092 _avr_set_r(avr, r, res);
1093 avr->sreg[S_Z] = res == 0;
1094 avr->sreg[S_C] = vr & 1;
1095 avr->sreg[S_N] = res >> 7;
1096 avr->sreg[S_V] = avr->sreg[S_N] ^ avr->sreg[S_C];
1097 avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
1100 case 0x9406: { // LSR 1001 010d dddd 0110
1101 uint8_t r = (opcode >> 4) & 0x1f;
1102 uint8_t vr = avr->data[r];
1103 uint8_t res = vr >> 1;
1104 STATE("lsr %s[%02x]\n", avr_regname(r), vr);
1105 _avr_set_r(avr, r, res);
1106 avr->sreg[S_Z] = res == 0;
1107 avr->sreg[S_C] = vr & 1;
1109 avr->sreg[S_V] = avr->sreg[S_N] ^ avr->sreg[S_C];
1110 avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
1113 case 0x9407: { // ROR 1001 010d dddd 0111
1114 uint8_t r = (opcode >> 4) & 0x1f;
1115 uint8_t vr = avr->data[r];
1116 uint8_t res = (avr->sreg[S_C] ? 0x80 : 0) | vr >> 1;
1117 STATE("ror %s[%02x]\n", avr_regname(r), vr);
1118 _avr_set_r(avr, r, res);
1119 avr->sreg[S_Z] = res == 0;
1120 avr->sreg[S_C] = vr & 1;
1122 avr->sreg[S_V] = avr->sreg[S_N] ^ avr->sreg[S_C];
1123 avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
1126 case 0x940a: { // DEC – Decrement
1127 uint8_t r = (opcode >> 4) & 0x1f;
1128 uint8_t res = avr->data[r] - 1;
1129 STATE("dec %s[%02x] = %02x\n", avr_regname(r), avr->data[r], res);
1130 _avr_set_r(avr, r, res);
1131 avr->sreg[S_Z] = res == 0;
1132 avr->sreg[S_N] = res >> 7;
1133 avr->sreg[S_V] = res == 0x80;
1134 avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
1138 case 0x940d: { // JMP Long Call to sub, 32 bits
1139 avr_flashaddr_t a = ((opcode & 0x01f0) >> 3) | (opcode & 1);
1140 uint16_t x = (avr->flash[new_pc+1] << 8) | avr->flash[new_pc];
1142 STATE("jmp 0x%06x\n", a);
1148 case 0x940f: { // CALL Long Call to sub, 32 bits
1149 avr_flashaddr_t a = ((opcode & 0x01f0) >> 3) | (opcode & 1);
1150 uint16_t x = (avr->flash[new_pc+1] << 8) | avr->flash[new_pc];
1152 STATE("call 0x%06x\n", a);
1154 _avr_push16(avr, new_pc >> 1);
1156 cycle += 3; // 4 cycles; FIXME 5 on devices with 22 bit PC
1162 switch (opcode & 0xff00) {
1163 case 0x9600: { // ADIW - Add Immediate to Word 1001 0110 KKdd KKKK
1164 uint8_t r = 24 + ((opcode >> 3) & 0x6);
1165 uint8_t k = ((opcode & 0x00c0) >> 2) | (opcode & 0xf);
1166 uint8_t rdl = avr->data[r], rdh = avr->data[r+1];
1167 uint32_t res = rdl | (rdh << 8);
1168 STATE("adiw %s:%s[%04x], 0x%02x\n", avr_regname(r), avr_regname(r+1), res, k);
1170 _avr_set_r(avr, r + 1, res >> 8);
1171 _avr_set_r(avr, r, res);
1172 avr->sreg[S_V] = ~(rdh >> 7) & ((res >> 15) & 1);
1173 avr->sreg[S_Z] = (res & 0xffff) == 0;
1174 avr->sreg[S_N] = (res >> 15) & 1;
1175 avr->sreg[S_C] = ~((res >> 15) & 1) & (rdh >> 7);
1176 avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
1180 case 0x9700: { // SBIW - Subtract Immediate from Word 1001 0110 KKdd KKKK
1181 uint8_t r = 24 + ((opcode >> 3) & 0x6);
1182 uint8_t k = ((opcode & 0x00c0) >> 2) | (opcode & 0xf);
1183 uint8_t rdl = avr->data[r], rdh = avr->data[r+1];
1184 uint32_t res = rdl | (rdh << 8);
1185 STATE("sbiw %s:%s[%04x], 0x%02x\n", avr_regname(r), avr_regname(r+1), res, k);
1187 _avr_set_r(avr, r + 1, res >> 8);
1188 _avr_set_r(avr, r, res);
1189 avr->sreg[S_V] = (rdh >> 7) & (~(res >> 15) & 1);
1190 avr->sreg[S_Z] = (res & 0xffff) == 0;
1191 avr->sreg[S_N] = (res >> 15) & 1;
1192 avr->sreg[S_C] = ((res >> 15) & 1) & (~rdh >> 7);
1193 avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
1197 case 0x9800: { // CBI - Clear Bit in I/O Register 1001 1000 AAAA Abbb
1198 uint8_t io = ((opcode >> 3) & 0x1f) + 32;
1199 uint8_t b = opcode & 0x7;
1200 uint8_t res = _avr_get_ram(avr, io) & ~(1 << b);
1201 STATE("cbi %s[%04x], 0x%02x = %02x\n", avr_regname(io), avr->data[io], 1<<b, res);
1202 _avr_set_ram(avr, io, res);
1205 case 0x9900: { // SBIC - Skip if Bit in I/O Register is Cleared 1001 0111 AAAA Abbb
1206 uint8_t io = ((opcode >> 3) & 0x1f) + 32;
1207 uint8_t b = opcode & 0x7;
1208 uint8_t res = _avr_get_ram(avr, io) & (1 << b);
1209 STATE("sbic %s[%04x], 0x%02x\t; Will%s branch\n", avr_regname(io), avr->data[io], 1<<b, !res?"":" not");
1211 if (_avr_is_instruction_32_bits(avr, new_pc)) {
1212 new_pc += 4; cycle += 2;
1214 new_pc += 2; cycle++;
1218 case 0x9a00: { // SBI - Set Bit in I/O Register 1001 1000 AAAA Abbb
1219 uint8_t io = ((opcode >> 3) & 0x1f) + 32;
1220 uint8_t b = opcode & 0x7;
1221 uint8_t res = _avr_get_ram(avr, io) | (1 << b);
1222 STATE("sbi %s[%04x], 0x%02x = %02x\n", avr_regname(io), avr->data[io], 1<<b, res);
1223 _avr_set_ram(avr, io, res);
1226 case 0x9b00: { // SBIS - Skip if Bit in I/O Register is Set 1001 1011 AAAA Abbb
1227 uint8_t io = ((opcode >> 3) & 0x1f) + 32;
1228 uint8_t b = opcode & 0x7;
1229 uint8_t res = _avr_get_ram(avr, io) & (1 << b);
1230 STATE("sbis %s[%04x], 0x%02x\t; Will%s branch\n", avr_regname(io), avr->data[io], 1<<b, res?"":" not");
1232 if (_avr_is_instruction_32_bits(avr, new_pc)) {
1233 new_pc += 4; cycle += 2;
1235 new_pc += 2; cycle++;
1240 switch (opcode & 0xfc00) {
1241 case 0x9c00: { // MUL - Multiply Unsigned 1001 11rd dddd rrrr
1243 uint16_t res = vd * vr;
1244 STATE("mul %s[%02x], %s[%02x] = %04x\n", avr_regname(d), vd, avr_regname(r), vr, res);
1246 _avr_set_r(avr, 0, res);
1247 _avr_set_r(avr, 1, res >> 8);
1248 avr->sreg[S_Z] = res == 0;
1249 avr->sreg[S_C] = (res >> 15) & 1;
1252 default: _avr_invalid_opcode(avr);
1262 switch (opcode & 0xf800) {
1263 case 0xb800: { // OUT A,Rr 1011 1AAr rrrr AAAA
1264 uint8_t r = (opcode >> 4) & 0x1f;
1265 uint8_t A = ((((opcode >> 9) & 3) << 4) | ((opcode) & 0xf)) + 32;
1266 STATE("out %s, %s[%02x]\n", avr_regname(A), avr_regname(r), avr->data[r]);
1267 _avr_set_ram(avr, A, avr->data[r]);
1269 case 0xb000: { // IN Rd,A 1011 0AAr rrrr AAAA
1270 uint8_t r = (opcode >> 4) & 0x1f;
1271 uint8_t A = ((((opcode >> 9) & 3) << 4) | ((opcode) & 0xf)) + 32;
1272 STATE("in %s, %s[%02x]\n", avr_regname(r), avr_regname(A), avr->data[A]);
1273 _avr_set_r(avr, r, _avr_get_ram(avr, A));
1275 default: _avr_invalid_opcode(avr);
1280 // RJMP 1100 kkkk kkkk kkkk
1281 // int16_t o = ((int16_t)(opcode << 4)) >> 4; // CLANG BUG!
1282 int16_t o = ((int16_t)((opcode << 4)&0xffff)) >> 4;
1283 STATE("rjmp .%d [%04x]\n", o, new_pc + (o << 1));
1284 new_pc = new_pc + (o << 1);
1290 // RCALL 1100 kkkk kkkk kkkk
1291 // int16_t o = ((int16_t)(opcode << 4)) >> 4; // CLANG BUG!
1292 int16_t o = ((int16_t)((opcode << 4)&0xffff)) >> 4;
1293 STATE("rcall .%d [%04x]\n", o, new_pc + (o << 1));
1294 _avr_push16(avr, new_pc >> 1);
1295 new_pc = new_pc + (o << 1);
1297 // 'rcall .1' is used as a cheap "push 16 bits of room on the stack"
1304 case 0xe000: { // LDI Rd, K 1110 KKKK RRRR KKKK -- aka SER (LDI r, 0xff)
1305 uint8_t d = 16 + ((opcode >> 4) & 0xf);
1306 uint8_t k = ((opcode & 0x0f00) >> 4) | (opcode & 0xf);
1307 STATE("ldi %s, 0x%02x\n", avr_regname(d), k);
1308 _avr_set_r(avr, d, k);
1312 switch (opcode & 0xfe00) {
1316 case 0xf600: { // All the SREG branches
1317 int16_t o = ((int16_t)(opcode << 6)) >> 9; // offset
1318 uint8_t s = opcode & 7;
1319 int set = (opcode & 0x0400) == 0; // this bit means BRXC otherwise BRXS
1320 int branch = (avr->sreg[s] && set) || (!avr->sreg[s] && !set);
1321 const char *names[2][8] = {
1322 { "brcc", "brne", "brpl", "brvc", NULL, "brhc", "brtc", "brid"},
1323 { "brcs", "breq", "brmi", "brvs", NULL, "brhs", "brts", "brie"},
1325 if (names[set][s]) {
1326 STATE("%s .%d [%04x]\t; Will%s branch\n", names[set][s], o, new_pc + (o << 1), branch ? "":" not");
1328 STATE("%s%c .%d [%04x]\t; Will%s branch\n", set ? "brbs" : "brbc", _sreg_bit_name[s], o, new_pc + (o << 1), branch ? "":" not");
1331 cycle++; // 2 cycles if taken, 1 otherwise
1332 new_pc = new_pc + (o << 1);
1336 case 0xf900: { // BLD – Bit Store from T into a Bit in Register 1111 100r rrrr 0bbb
1337 uint8_t r = (opcode >> 4) & 0x1f; // register index
1338 uint8_t s = opcode & 7;
1339 uint8_t v = avr->data[r] | (avr->sreg[S_T] ? (1 << s) : 0);
1340 STATE("bld %s[%02x], 0x%02x = %02x\n", avr_regname(r), avr->data[r], 1 << s, v);
1341 _avr_set_r(avr, r, v);
1344 case 0xfb00:{ // BST – Bit Store into T from bit in Register 1111 100r rrrr 0bbb
1345 uint8_t r = (opcode >> 4) & 0x1f; // register index
1346 uint8_t s = opcode & 7;
1347 STATE("bst %s[%02x], 0x%02x\n", avr_regname(r), avr->data[r], 1 << s);
1348 avr->sreg[S_T] = (avr->data[r] >> s) & 1;
1352 case 0xfe00: { // SBRS/SBRC – Skip if Bit in Register is Set/Clear 1111 11sr rrrr 0bbb
1353 uint8_t r = (opcode >> 4) & 0x1f; // register index
1354 uint8_t s = opcode & 7;
1355 int set = (opcode & 0x0200) != 0;
1356 int branch = ((avr->data[r] & (1 << s)) && set) || (!(avr->data[r] & (1 << s)) && !set);
1357 STATE("%s %s[%02x], 0x%02x\t; Will%s branch\n", set ? "sbrs" : "sbrc", avr_regname(r), avr->data[r], 1 << s, branch ? "":" not");
1359 if (_avr_is_instruction_32_bits(avr, new_pc)) {
1360 new_pc += 4; cycle += 2;
1362 new_pc += 2; cycle++;
1366 default: _avr_invalid_opcode(avr);
1370 default: _avr_invalid_opcode(avr);
1373 avr->cycle += cycle;