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   1 /*
   2         sim_core.c
   3
   4         Copyright 2008, 2009 Michel Pollet <buserror@gmail.com>
   5
   6         This file is part of simavr.
   7
   8         simavr is free software: you can redistribute it and/or modify
   9         it under the terms of the GNU General Public License as published by
  10         the Free Software Foundation, either version 3 of the License, or
  11         (at your option) any later version.
  12
  13         simavr is distributed in the hope that it will be useful,
  14         but WITHOUT ANY WARRANTY; without even the implied warranty of
  15         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16         GNU General Public License for more details.
  17
  18         You should have received a copy of the GNU General Public License
  19         along with simavr.  If not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include <stdlib.h>
  23 #include <stdio.h>
  24 #include <string.h>
  25 #include <ctype.h>
  26 #include "sim_avr.h"
  27 #include "sim_core.h"
  28 #include "avr_flash.h"
  29 #include "avr_watchdog.h"
  30
  31 // SREG bit names
  32 const char * _sreg_bit_name = "cznvshti";
  33
  34 /*
  35  * Handle "touching" registers, marking them changed.
  36  * This is used only for debugging purposes to be able to
  37  * print the effects of each instructions on registers
  38  */
  39 #if CONFIG_SIMAVR_TRACE
  40
  41 #define T(w) w
  42
  43 #define REG_TOUCH(a, r) (a)->trace_data->touched[(r) >> 5] |= (1 << ((r) & 0x1f))
  44 #define REG_ISTOUCHED(a, r) ((a)->trace_data->touched[(r) >> 5] & (1 << ((r) & 0x1f)))
  45
  46 /*
  47  * This allows a "special case" to skip indtruction tracing when in these
  48  * symbols. since printf() is useful to have, but generates a lot of cycles
  49  */
  50 int dont_trace(const char * name)
  51 {
  52         return (
  53                 !strcmp(name, "uart_putchar") ||
  54                 !strcmp(name, "fputc") ||
  55                 !strcmp(name, "printf") ||
  56                 !strcmp(name, "vfprintf") ||
  57                 !strcmp(name, "__ultoa_invert") ||
  58                 !strcmp(name, "__prologue_saves__") ||
  59                 !strcmp(name, "__epilogue_restores__"));
  60 }
  61
  62 int donttrace = 0;
  63
  64 #define STATE(_f, args...) { \
  65         if (avr->trace) {\
  66                 if (avr->trace_data->codeline && avr->trace_data->codeline[avr->pc>>1]) {\
  67                         const char * symn = avr->trace_data->codeline[avr->pc>>1]->symbol; \
  68                         int dont = 0 && dont_trace(symn);\
  69                         if (dont!=donttrace) { \
  70                                 donttrace = dont;\
  71                                 DUMP_REG();\
  72                         }\
  73                         if (donttrace==0)\
  74                                 printf("%04x: %-25s " _f, avr->pc, symn, ## args);\
  75                 } else \
  76                         printf("%s: %04x: " _f, __FUNCTION__, avr->pc, ## args);\
  77                 }\
  78         }
  79 #define SREG() if (avr->trace && donttrace == 0) {\
  80         printf("%04x: \t\t\t\t\t\t\t\t\tSREG = ", avr->pc); \
  81         for (int _sbi = 0; _sbi < 8; _sbi++)\
  82                 printf("%c", avr->sreg[_sbi] ? toupper(_sreg_bit_name[_sbi]) : '.');\
  83         printf("\n");\
  84 }
  85 #else
  86 #define T(w)
  87 #define REG_TOUCH(a, r)
  88 #define STATE(_f, args...)
  89 #define SREG()
  90 #endif
  91
  92 void avr_core_watch_write(avr_t *avr, uint16_t addr, uint8_t v)
  93 {
  94         if (addr > avr->ramend) {
  95                 printf("*** Invalid write address PC=%04x SP=%04x O=%04x Address %04x=%02x out of ram\n",
  96                                 avr->pc, _avr_sp_get(avr), avr->flash[avr->pc] | (avr->flash[avr->pc]<<8), addr, v);
  97                 CRASH();
  98         }
  99         if (addr < 32) {
 100                 printf("*** Invalid write address PC=%04x SP=%04x O=%04x Address %04x=%02x low registers\n",
 101                                 avr->pc, _avr_sp_get(avr), avr->flash[avr->pc] | (avr->flash[avr->pc]<<8), addr, v);
 102                 CRASH();
 103         }
 104 #if AVR_STACK_WATCH
 105         /*
 106          * this checks that the current "function" is not doctoring the stack frame that is located
 107          * higher on the stack than it should be. It's a sign of code that has overrun it's stack
 108          * frame and is munching on it's own return address.
 109          */
 110         if (avr->trace_data->stack_frame_index > 1 && addr > avr->trace_data->stack_frame[avr->trace_data->stack_frame_index-2].sp) {
 111                 printf("\e[31m%04x : munching stack SP %04x, A=%04x <= %02x\e[0m\n", avr->pc, _avr_sp_get(avr), addr, v);
 112         }
 113 #endif
 114         avr->data[addr] = v;
 115 }
 116
 117 uint8_t avr_core_watch_read(avr_t *avr, uint16_t addr)
 118 {
 119         if (addr > avr->ramend) {
 120                 printf("*** Invalid read address PC=%04x SP=%04x O=%04x Address %04x out of ram (%04x)\n",
 121                                 avr->pc, _avr_sp_get(avr), avr->flash[avr->pc] | (avr->flash[avr->pc]<<8), addr, avr->ramend);
 122                 CRASH();
 123         }
 124         return avr->data[addr];
 125 }
 126
 127 /*
 128  * Set a register (r < 256)
 129  * if it's an IO regisrer (> 31) also (try to) call any callback that was
 130  * registered to track changes to that register.
 131  */
 132 static inline void _avr_set_r(avr_t * avr, uint8_t r, uint8_t v)
 133 {
 134         REG_TOUCH(avr, r);
 135
 136         if (r == R_SREG) {
 137                 avr->data[R_SREG] = v;
 138                 // unsplit the SREG
 139                 for (int i = 0; i < 8; i++)
 140                         avr->sreg[i] = (v & (1 << i)) != 0;
 141                 SREG();
 142         }
 143         if (r > 31) {
 144                 uint8_t io = AVR_DATA_TO_IO(r);
 145                 if (avr->io[io].w.c)
 146                         avr->io[io].w.c(avr, r, v, avr->io[io].w.param);
 147                 else
 148                         avr->data[r] = v;
 149                 if (avr->io[io].irq) {
 150                         avr_raise_irq(avr->io[io].irq + AVR_IOMEM_IRQ_ALL, v);
 151                         for (int i = 0; i < 8; i++)
 152                                 avr_raise_irq(avr->io[io].irq + i, (v >> i) & 1);
 153                 }
 154         } else
 155                 avr->data[r] = v;
 156 }
 157
 158 /*
 159  * Stack pointer access
 160  */
 161 inline uint16_t _avr_sp_get(avr_t * avr)
 162 {
 163         return avr->data[R_SPL] | (avr->data[R_SPH] << 8);
 164 }
 165
 166 inline void _avr_sp_set(avr_t * avr, uint16_t sp)
 167 {
 168         _avr_set_r(avr, R_SPL, sp);
 169         _avr_set_r(avr, R_SPH, sp >> 8);
 170 }
 171
 172 /*
 173  * Set any address to a value; split between registers and SRAM
 174  */
 175 static inline void _avr_set_ram(avr_t * avr, uint16_t addr, uint8_t v)
 176 {
 177         if (addr < 256)
 178                 _avr_set_r(avr, addr, v);
 179         else
 180                 avr_core_watch_write(avr, addr, v);
 181 }
 182
 183 /*
 184  * Get a value from SRAM.
 185  */
 186 static inline uint8_t _avr_get_ram(avr_t * avr, uint16_t addr)
 187 {
 188         if (addr == R_SREG) {
 189                 /*
 190                  * SREG is special it's reconstructed when read
 191                  * while the core itself uses the "shortcut" array
 192                  */
 193                 avr->data[R_SREG] = 0;
 194                 for (int i = 0; i < 8; i++)
 195                         if (avr->sreg[i] > 1) {
 196                                 printf("** Invalid SREG!!\n");
 197                                 CRASH();
 198                         } else if (avr->sreg[i])
 199                                 avr->data[R_SREG] |= (1 << i);
 200
 201         } else if (addr > 31 && addr < 256) {
 202                 uint8_t io = AVR_DATA_TO_IO(addr);
 203
 204                 if (avr->io[io].r.c)
 205                         avr->data[addr] = avr->io[io].r.c(avr, addr, avr->io[io].r.param);
 206
 207                 if (avr->io[io].irq) {
 208                         uint8_t v = avr->data[addr];
 209                         avr_raise_irq(avr->io[io].irq + AVR_IOMEM_IRQ_ALL, v);
 210                         for (int i = 0; i < 8; i++)
 211                                 avr_raise_irq(avr->io[io].irq + i, (v >> i) & 1);
 212                 }
 213         }
 214         return avr_core_watch_read(avr, addr);
 215 }
 216
 217 /*
 218  * Stack push accessors. Push/pop 8 and 16 bits
 219  */
 220 static inline void _avr_push8(avr_t * avr, uint16_t v)
 221 {
 222         uint16_t sp = _avr_sp_get(avr);
 223         _avr_set_ram(avr, sp, v);
 224         _avr_sp_set(avr, sp-1);
 225 }
 226
 227 static inline uint8_t _avr_pop8(avr_t * avr)
 228 {
 229         uint16_t sp = _avr_sp_get(avr) + 1;
 230         uint8_t res = _avr_get_ram(avr, sp);
 231         _avr_sp_set(avr, sp);
 232         return res;
 233 }
 234
 235 inline void _avr_push16(avr_t * avr, uint16_t v)
 236 {
 237         _avr_push8(avr, v);
 238         _avr_push8(avr, v >> 8);
 239 }
 240
 241 static inline uint16_t _avr_pop16(avr_t * avr)
 242 {
 243         uint16_t res = _avr_pop8(avr) << 8;
 244         res |= _avr_pop8(avr);
 245         return res;
 246 }
 247
 248 /*
 249  * "Pretty" register names
 250  */
 251 const char * reg_names[255] = {
 252                 [R_XH] = "XH", [R_XL] = "XL",
 253                 [R_YH] = "YH", [R_YL] = "YL",
 254                 [R_ZH] = "ZH", [R_ZL] = "ZL",
 255                 [R_SPH] = "SPH", [R_SPL] = "SPL",
 256                 [R_SREG] = "SREG",
 257 };
 258
 259
 260 const char * avr_regname(uint8_t reg)
 261 {
 262         if (!reg_names[reg]) {
 263                 char tt[16];
 264                 if (reg < 32)
 265                         sprintf(tt, "r%d", reg);
 266                 else
 267                         sprintf(tt, "io:%02x", reg);
 268                 reg_names[reg] = strdup(tt);
 269         }
 270         return reg_names[reg];
 271 }
 272
 273 /*
 274  * Called when an invalid opcode is decoded
 275  */
 276 static void _avr_invalid_opcode(avr_t * avr)
 277 {
 278 #if CONFIG_SIMAVR_TRACE
 279         printf("\e[31m*** %04x: %-25s Invalid Opcode SP=%04x O=%04x \e[0m\n",
 280                         avr->pc, avr->trace_data->codeline[avr->pc>>1]->symbol, _avr_sp_get(avr), avr->flash[avr->pc] | (avr->flash[avr->pc+1]<<8));
 281 #else
 282         printf("\e[31m*** %04x: Invalid Opcode SP=%04x O=%04x \e[0m\n",
 283                         avr->pc, _avr_sp_get(avr), avr->flash[avr->pc] | (avr->flash[avr->pc+1]<<8));
 284 #endif
 285 }
 286
 287 #if CONFIG_SIMAVR_TRACE
 288 /*
 289  * Dump changed registers when tracing
 290  */
 291 void avr_dump_state(avr_t * avr)
 292 {
 293         if (!avr->trace || donttrace)
 294                 return;
 295
 296         int doit = 0;
 297
 298         for (int r = 0; r < 3 && !doit; r++)
 299                 if (avr->trace_data->touched[r])
 300                         doit = 1;
 301         if (!doit)
 302                 return;
 303         printf("                                       ->> ");
 304         const int r16[] = { R_SPL, R_XL, R_YL, R_ZL };
 305         for (int i = 0; i < 4; i++)
 306                 if (REG_ISTOUCHED(avr, r16[i]) || REG_ISTOUCHED(avr, r16[i]+1)) {
 307                         REG_TOUCH(avr, r16[i]);
 308                         REG_TOUCH(avr, r16[i]+1);
 309                 }
 310
 311         for (int i = 0; i < 3*32; i++)
 312                 if (REG_ISTOUCHED(avr, i)) {
 313                         printf("%s=%02x ", avr_regname(i), avr->data[i]);
 314                 }
 315         printf("\n");
 316 }
 317 #endif
 318
 319 #define get_r_d_10(o) \
 320                 const uint8_t r = ((o >> 5) & 0x10) | (o & 0xf); \
 321                 const uint8_t d = (o >> 4) & 0x1f;\
 322                 const uint8_t vd = avr->data[d], vr = avr->data[r];
 323 #define get_r_dd_10(o) \
 324                 const uint8_t r = ((o >> 5) & 0x10) | (o & 0xf); \
 325                 const uint8_t d = (o >> 4) & 0x1f;\
 326                 const uint8_t vr = avr->data[r];
 327 #define get_k_r16(o) \
 328                 const uint8_t r = 16 + ((o >> 4) & 0xf); \
 329                 const uint8_t k = ((o & 0x0f00) >> 4) | (o & 0xf);
 330
 331 /*
 332  * Add a "jump" address to the jump trace buffer
 333  */
 334 #if CONFIG_SIMAVR_TRACE
 335 #define TRACE_JUMP()\
 336         avr->trace_data->old[avr->trace_data->old_pci].pc = avr->pc;\
 337         avr->trace_data->old[avr->trace_data->old_pci].sp = _avr_sp_get(avr);\
 338         avr->trace_data->old_pci = (avr->trace_data->old_pci + 1) & (OLD_PC_SIZE-1);\
 339
 340 #if AVR_STACK_WATCH
 341 #define STACK_FRAME_PUSH()\
 342         avr->trace_data->stack_frame[avr->trace_data->stack_frame_index].pc = avr->pc;\
 343         avr->trace_data->stack_frame[avr->trace_data->stack_frame_index].sp = _avr_sp_get(avr);\
 344         avr->trace_data->stack_frame_index++;
 345 #define STACK_FRAME_POP()\
 346         if (avr->trace_data->stack_frame_index > 0) \
 347                 avr->trace_data->stack_frame_index--;
 348 #else
 349 #define STACK_FRAME_PUSH()
 350 #define STACK_FRAME_POP()
 351 #endif
 352 #else /* CONFIG_SIMAVR_TRACE */
 353
 354 #define TRACE_JUMP()
 355 #define STACK_FRAME_PUSH()
 356 #define STACK_FRAME_POP()
 357
 358 #endif
 359
 360 /****************************************************************************\
 361  *
 362  * Helper functions for calculating the status register bit values.
 363  * See the Atmel data sheet for the instruction set for more info.
 364  *
 365 \****************************************************************************/
 366
 367 static uint8_t
 368 get_add_carry (uint8_t res, uint8_t rd, uint8_t rr, int b)
 369 {
 370     uint8_t resb = res >> b & 0x1;
 371     uint8_t rdb = rd >> b & 0x1;
 372     uint8_t rrb = rr >> b & 0x1;
 373     return (rdb & rrb) | (rrb & ~resb) | (~resb & rdb);
 374 }
 375
 376 static  uint8_t
 377 get_add_overflow (uint8_t res, uint8_t rd, uint8_t rr)
 378 {
 379     uint8_t res7 = res >> 7 & 0x1;
 380     uint8_t rd7 = rd >> 7 & 0x1;
 381     uint8_t rr7 = rr >> 7 & 0x1;
 382     return (rd7 & rr7 & ~res7) | (~rd7 & ~rr7 & res7);
 383 }
 384
 385 static  uint8_t
 386 get_sub_carry (uint8_t res, uint8_t rd, uint8_t rr, int b)
 387 {
 388     uint8_t resb = res >> b & 0x1;
 389     uint8_t rdb = rd >> b & 0x1;
 390     uint8_t rrb = rr >> b & 0x1;
 391     return (~rdb & rrb) | (rrb & resb) | (resb & ~rdb);
 392 }
 393
 394 static  uint8_t
 395 get_sub_overflow (uint8_t res, uint8_t rd, uint8_t rr)
 396 {
 397     uint8_t res7 = res >> 7 & 0x1;
 398     uint8_t rd7 = rd >> 7 & 0x1;
 399     uint8_t rr7 = rr >> 7 & 0x1;
 400     return (rd7 & ~rr7 & ~res7) | (~rd7 & rr7 & res7);
 401 }
 402
 403 static  uint8_t
 404 get_compare_carry (uint8_t res, uint8_t rd, uint8_t rr, int b)
 405 {
 406     uint8_t resb = (res >> b) & 0x1;
 407     uint8_t rdb = (rd >> b) & 0x1;
 408     uint8_t rrb = (rr >> b) & 0x1;
 409     return (~rdb & rrb) | (rrb & resb) | (resb & ~rdb);
 410 }
 411
 412 static  uint8_t
 413 get_compare_overflow (uint8_t res, uint8_t rd, uint8_t rr)
 414 {
 415     res >>= 7; rd >>= 7; rr >>= 7;
 416     /* The atmel data sheet says the second term is ~rd7 for CP
 417      * but that doesn't make any sense. You be the judge. */
 418     return (rd & ~rr & ~res) | (~rd & rr & res);
 419 }
 420
 421 static inline int _avr_is_instruction_32_bits(avr_t * avr, uint32_t pc)
 422 {
 423         uint16_t o = (avr->flash[pc] | (avr->flash[pc+1] << 8)) & 0xfc0f;
 424         return  o == 0x9200 || // STS ! Store Direct to Data Space
 425                         o == 0x9000 || // LDS Load Direct from Data Space
 426                         o == 0x940c || // JMP Long Jump
 427                         o == 0x940d || // JMP Long Jump
 428                         o == 0x940e ||  // CALL Long Call to sub
 429                         o == 0x940f; // CALL Long Call to sub
 430 }
 431
 432 /*
 433  * Main opcode decoder
 434  *
 435  * The decoder was written by following the datasheet in no particular order.
 436  * As I went along, I noticed "bit patterns" that could be used to factor opcodes
 437  * However, a lot of these only became apparent later on, so SOME instructions
 438  * (skip of bit set etc) are compact, and some could use some refactoring (the ALU
 439  * ones scream to be factored).
 440  * I assume that the decoder could easily be 2/3 of it's current size.
 441  *
 442  * + It lacks the "extended" XMega jumps.
 443  * + It also doesn't check whether the core it's
 444  *   emulating is supposed to have the fancy instructions, like multiply and such.
 445  *
 446  * The nunber of cycles taken by instruction has been added, but might not be
 447  * entirely accurate.
 448  */
 449 uint16_t avr_run_one(avr_t * avr)
 450 {
 451 #if CONFIG_SIMAVR_TRACE
 452         /*
 453          * this traces spurious reset or bad jumps
 454          */
 455         if ((avr->pc == 0 && avr->cycle > 0) || avr->pc >= avr->codeend) {
 456                 avr->trace = 1;
 457                 STATE("RESET\n");
 458                 CRASH();
 459         }
 460         avr->trace_data->touched[0] = avr->trace_data->touched[1] = avr->trace_data->touched[2] = 0;
 461 #endif
 462
 463         uint32_t        opcode = (avr->flash[avr->pc + 1] << 8) | avr->flash[avr->pc];
 464         uint32_t        new_pc = avr->pc + 2;   // future "default" pc
 465         int             cycle = 1;
 466
 467         switch (opcode & 0xf000) {
 468                 case 0x0000: {
 469                         switch (opcode) {
 470                                 case 0x0000: {  // NOP
 471                                         STATE("nop\n");
 472                                 }       break;
 473                                 default: {
 474                                         switch (opcode & 0xfc00) {
 475                                                 case 0x0400: {  // CPC compare with carry 0000 01rd dddd rrrr
 476                                                         get_r_d_10(opcode);
 477                                                         uint8_t res = vd - vr - avr->sreg[S_C];
 478                                                         STATE("cpc %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res);
 479                                                         if (res)
 480                                                                 avr->sreg[S_Z] = 0;
 481                                                         avr->sreg[S_H] = get_compare_carry(res, vd, vr, 3);
 482                                                         avr->sreg[S_V] = get_compare_overflow(res, vd, vr);
 483                                                         avr->sreg[S_N] = (res >> 7) & 1;
 484                                                         avr->sreg[S_C] = get_compare_carry(res, vd, vr, 7);
 485                                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 486                                                         SREG();
 487                                                 }       break;
 488                                                 case 0x0c00: {  // ADD without carry 0000 11 rd dddd rrrr
 489                                                         get_r_d_10(opcode);
 490                                                         uint8_t res = vd + vr;
 491                                                         if (r == d) {
 492                                                                 STATE("lsl %s[%02x] = %02x\n", avr_regname(d), vd, res & 0xff);
 493                                                         } else {
 494                                                                 STATE("add %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res);
 495                                                         }
 496                                                         _avr_set_r(avr, d, res);
 497                                                         avr->sreg[S_Z] = res == 0;
 498                                                         avr->sreg[S_H] = get_add_carry(res, vd, vr, 3);
 499                                                         avr->sreg[S_V] = get_add_overflow(res, vd, vr);
 500                                                         avr->sreg[S_N] = (res >> 7) & 1;
 501                                                         avr->sreg[S_C] = get_add_carry(res, vd, vr, 7);
 502                                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 503                                                         SREG();
 504                                                 }       break;
 505                                                 case 0x0800: {  // SBC subtract with carry 0000 10rd dddd rrrr
 506                                                         get_r_d_10(opcode);
 507                                                         uint8_t res = vd - vr - avr->sreg[S_C];
 508                                                         STATE("sbc %s[%02x], %s[%02x] = %02x\n", avr_regname(d), avr->data[d], avr_regname(r), avr->data[r], res);
 509                                                         _avr_set_r(avr, d, res);
 510                                                         if (res)
 511                                                                 avr->sreg[S_Z] = 0;
 512                                                         avr->sreg[S_H] = get_sub_carry(res, vd, vr, 3);
 513                                                         avr->sreg[S_V] = get_sub_overflow(res, vd, vr);
 514                                                         avr->sreg[S_N] = (res >> 7) & 1;
 515                                                         avr->sreg[S_C] = get_sub_carry(res, vd, vr, 7);
 516                                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 517                                                         SREG();
 518                                                 }       break;
 519                                                 default:
 520                                                         switch (opcode & 0xff00) {
 521                                                                 case 0x0100: {  // MOVW – Copy Register Word 0000 0001 dddd rrrr
 522                                                                         uint8_t d = ((opcode >> 4) & 0xf) << 1;
 523                                                                         uint8_t r = ((opcode) & 0xf) << 1;
 524                                                                         STATE("movw %s:%s, %s:%s[%02x%02x]\n", avr_regname(d), avr_regname(d+1), avr_regname(r), avr_regname(r+1), avr->data[r+1], avr->data[r]);
 525                                                                         _avr_set_r(avr, d, avr->data[r]);
 526                                                                         _avr_set_r(avr, d+1, avr->data[r+1]);
 527                                                                 }       break;
 528                                                                 case 0x0200: {  // MULS – Multiply Signed 0000 0010 dddd rrrr
 529                                                                         int8_t r = 16 + (opcode & 0xf);
 530                                                                         int8_t d = 16 + ((opcode >> 4) & 0xf);
 531                                                                         int16_t res = ((int8_t)avr->data[r]) * ((int8_t)avr->data[d]);
 532                                                                         STATE("muls %s[%d], %s[%02x] = %d\n", avr_regname(d), ((int8_t)avr->data[d]), avr_regname(r), ((int8_t)avr->data[r]), res);
 533                                                                         _avr_set_r(avr, 0, res);
 534                                                                         _avr_set_r(avr, 1, res >> 8);
 535                                                                         avr->sreg[S_C] = (res >> 15) & 1;
 536                                                                         avr->sreg[S_Z] = res == 0;
 537                                                                         SREG();
 538                                                                 }       break;
 539                                                                 case 0x0300: {  // MUL Multiply 0000 0011 fddd frrr
 540                                                                         int8_t r = 16 + (opcode & 0x7);
 541                                                                         int8_t d = 16 + ((opcode >> 4) & 0x7);
 542                                                                         int16_t res = 0;
 543                                                                         uint8_t c = 0;
 544                                                                         T(const char * name = "";)
 545                                                                         switch (opcode & 0x88) {
 546                                                                                 case 0x00:      // MULSU – Multiply Signed Unsigned 0000 0011 0ddd 0rrr
 547                                                                                         res = ((uint8_t)avr->data[r]) * ((int8_t)avr->data[d]);
 548                                                                                         c = (res >> 15) & 1;
 549                                                                                         T(name = "mulsu";)
 550                                                                                         break;
 551                                                                                 case 0x08:      // FMUL Fractional Multiply Unsigned 0000 0011 0ddd 1rrr
 552                                                                                         res = ((uint8_t)avr->data[r]) * ((uint8_t)avr->data[d]);
 553                                                                                         c = (res >> 15) & 1;
 554                                                                                         res <<= 1;
 555                                                                                         T(name = "fmul";)
 556                                                                                         break;
 557                                                                                 case 0x80:      // FMULS – Multiply Signed  0000 0011 1ddd 0rrr
 558                                                                                         res = ((int8_t)avr->data[r]) * ((int8_t)avr->data[d]);
 559                                                                                         c = (res >> 15) & 1;
 560                                                                                         res <<= 1;
 561                                                                                         T(name = "fmuls";)
 562                                                                                         break;
 563                                                                                 case 0x88:      // FMULSU – Multiply Signed Unsigned 0000 0011 1ddd 1rrr
 564                                                                                         res = ((uint8_t)avr->data[r]) * ((int8_t)avr->data[d]);
 565                                                                                         c = (res >> 15) & 1;
 566                                                                                         res <<= 1;
 567                                                                                         T(name = "fmulsu";)
 568                                                                                         break;
 569                                                                         }
 570                                                                         cycle++;
 571                                                                         STATE("%s %s[%d], %s[%02x] = %d\n", name, avr_regname(d), ((int8_t)avr->data[d]), avr_regname(r), ((int8_t)avr->data[r]), res);
 572                                                                         _avr_set_r(avr, 0, res);
 573                                                                         _avr_set_r(avr, 1, res >> 8);
 574                                                                         avr->sreg[S_C] = c;
 575                                                                         avr->sreg[S_Z] = res == 0;
 576                                                                         SREG();
 577                                                                 }       break;
 578                                                                 default: _avr_invalid_opcode(avr);
 579                                                         }
 580                                         }
 581                                 }
 582                         }
 583                 }       break;
 584
 585                 case 0x1000: {
 586                         switch (opcode & 0xfc00) {
 587                                 case 0x1800: {  // SUB without carry 0000 10 rd dddd rrrr
 588                                         get_r_d_10(opcode);
 589                                         uint8_t res = vd - vr;
 590                                         STATE("sub %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res);
 591                                         _avr_set_r(avr, d, res);
 592                                         avr->sreg[S_Z] = res == 0;
 593                                         avr->sreg[S_H] = get_sub_carry(res, vd, vr, 3);
 594                                         avr->sreg[S_V] = get_sub_overflow(res, vd, vr);
 595                                         avr->sreg[S_N] = (res >> 7) & 1;
 596                                         avr->sreg[S_C] = get_sub_carry(res, vd, vr, 7);
 597                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 598                                         SREG();
 599                                 }       break;
 600                                 case 0x1000: {  // CPSE Compare, skip if equal 0000 00 rd dddd rrrr
 601                                         get_r_d_10(opcode);
 602                                         uint16_t res = vd == vr;
 603                                         STATE("cpse %s[%02x], %s[%02x]\t; Will%s skip\n", avr_regname(d), avr->data[d], avr_regname(r), avr->data[r], res ? "":" not");
 604                                         if (res) {
 605                                                 if (_avr_is_instruction_32_bits(avr, new_pc)) {
 606                                                         new_pc += 4; cycle += 2;
 607                                                 } else {
 608                                                         new_pc += 2; cycle++;
 609                                                 }
 610                                         }
 611                                 }       break;
 612                                 case 0x1400: {  // CP Compare 0000 01 rd dddd rrrr
 613                                         get_r_d_10(opcode);
 614                                         uint8_t res = vd - vr;
 615                                         STATE("cp %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res);
 616                                         avr->sreg[S_Z] = res == 0;
 617                                         avr->sreg[S_H] = get_compare_carry(res, vd, vr, 3);
 618                                         avr->sreg[S_V] = get_compare_overflow(res, vd, vr);
 619                                         avr->sreg[S_N] = res >> 7;
 620                                         avr->sreg[S_C] = get_compare_carry(res, vd, vr, 7);
 621                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 622                                         SREG();
 623                                 }       break;
 624                                 case 0x1c00: {  // ADD with carry 0001 11 rd dddd rrrr
 625                                         get_r_d_10(opcode);
 626                                         uint8_t res = vd + vr + avr->sreg[S_C];
 627                                         if (r == d) {
 628                                                 STATE("rol %s[%02x] = %02x\n", avr_regname(d), avr->data[d], res);
 629                                         } else {
 630                                                 STATE("addc %s[%02x], %s[%02x] = %02x\n", avr_regname(d), avr->data[d], avr_regname(r), avr->data[r], res);
 631                                         }
 632                                         _avr_set_r(avr, d, res);
 633                                         avr->sreg[S_Z] = res == 0;
 634                                         avr->sreg[S_H] = get_add_carry(res, vd, vr, 3);
 635                                         avr->sreg[S_V] = get_add_overflow(res, vd, vr);
 636                                         avr->sreg[S_N] = (res >> 7) & 1;
 637                                         avr->sreg[S_C] = get_add_carry(res, vd, vr, 7);
 638                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 639                                         SREG();
 640                                 }       break;
 641                                 default: _avr_invalid_opcode(avr);
 642                         }
 643                 }       break;
 644
 645                 case 0x2000: {
 646                         switch (opcode & 0xfc00) {
 647                                 case 0x2000: {  // AND  0010 00rd dddd rrrr
 648                                         get_r_d_10(opcode);
 649                                         uint8_t res = vd & vr;
 650                                         if (r == d) {
 651                                                 STATE("tst %s[%02x]\n", avr_regname(d), avr->data[d]);
 652                                         } else {
 653                                                 STATE("and %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res);
 654                                         }
 655                                         _avr_set_r(avr, d, res);
 656                                         avr->sreg[S_Z] = res == 0;
 657                                         avr->sreg[S_N] = (res >> 7) & 1;
 658                                         avr->sreg[S_V] = 0;
 659                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 660                                         SREG();
 661                                 }       break;
 662                                 case 0x2400: {  // EOR  0010 01rd dddd rrrr
 663                                         get_r_d_10(opcode);
 664                                         uint8_t res = vd ^ vr;
 665                                         if (r==d) {
 666                                                 STATE("clr %s[%02x]\n", avr_regname(d), avr->data[d]);
 667                                         } else {
 668                                                 STATE("eor %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res);
 669                                         }
 670                                         _avr_set_r(avr, d, res);
 671                                         avr->sreg[S_Z] = res == 0;
 672                                         avr->sreg[S_N] = (res >> 7) & 1;
 673                                         avr->sreg[S_V] = 0;
 674                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 675                                         SREG();
 676                                 }       break;
 677                                 case 0x2800: {  // OR Logical OR        0010 10rd dddd rrrr
 678                                         get_r_d_10(opcode);
 679                                         uint8_t res = vd | vr;
 680                                         STATE("or %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res);
 681                                         _avr_set_r(avr, d, res);
 682                                         avr->sreg[S_Z] = res == 0;
 683                                         avr->sreg[S_N] = (res >> 7) & 1;
 684                                         avr->sreg[S_V] = 0;
 685                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 686                                         SREG();
 687                                 }       break;
 688                                 case 0x2c00: {  // MOV  0010 11rd dddd rrrr
 689                                         get_r_dd_10(opcode);
 690                                         uint8_t res = vr;
 691                                         STATE("mov %s, %s[%02x] = %02x\n", avr_regname(d), avr_regname(r), vr, res);
 692                                         _avr_set_r(avr, d, res);
 693                                 }       break;
 694                                 default: _avr_invalid_opcode(avr);
 695                         }
 696                 }       break;
 697
 698                 case 0x3000: {  // CPI 0011 KKKK rrrr KKKK
 699                         get_k_r16(opcode);
 700                         uint8_t vr = avr->data[r];
 701                         uint8_t res = vr - k;
 702                         STATE("cpi %s[%02x], 0x%02x\n", avr_regname(r), vr, k);
 703
 704                         avr->sreg[S_Z] = res == 0;
 705                         avr->sreg[S_H] = get_compare_carry(res, vr, k, 3);
 706                         avr->sreg[S_V] = get_compare_overflow(res, vr, k);
 707                         avr->sreg[S_N] = (res >> 7) & 1;
 708                         avr->sreg[S_C] = get_compare_carry(res, vr, k, 7);
 709                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 710                         SREG();
 711                 }       break;
 712
 713                 case 0x4000: {  // SBCI Subtract Immediate With Carry 0101 10 kkkk dddd kkkk
 714                         get_k_r16(opcode);
 715                         uint8_t vr = avr->data[r];
 716                         uint8_t res = vr - k - avr->sreg[S_C];
 717                         STATE("sbci %s[%02x], 0x%02x = %02x\n", avr_regname(r), avr->data[r], k, res);
 718                         _avr_set_r(avr, r, res);
 719                         if (res)
 720                                 avr->sreg[S_Z] = 0;
 721                         avr->sreg[S_N] = (res >> 7) & 1;
 722                         avr->sreg[S_C] = (k + avr->sreg[S_C]) > vr;
 723                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 724                         SREG();
 725                 }       break;
 726
 727                 case 0x5000: {  // SUB Subtract Immediate 0101 10 kkkk dddd kkkk
 728                         get_k_r16(opcode);
 729                         uint8_t vr = avr->data[r];
 730                         uint8_t res = vr - k;
 731                         STATE("subi %s[%02x], 0x%02x = %02x\n", avr_regname(r), avr->data[r], k, res);
 732                         _avr_set_r(avr, r, res);
 733                         avr->sreg[S_Z] = res  == 0;
 734                         avr->sreg[S_N] = (res >> 7) & 1;
 735                         avr->sreg[S_C] = k > vr;
 736                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 737                         SREG();
 738                 }       break;
 739
 740                 case 0x6000: {  // ORI aka SBR  Logical AND with Immediate      0110 kkkk dddd kkkk
 741                         get_k_r16(opcode);
 742                         uint8_t res = avr->data[r] | k;
 743                         STATE("ori %s[%02x], 0x%02x\n", avr_regname(r), avr->data[r], k);
 744                         _avr_set_r(avr, r, res);
 745                         avr->sreg[S_Z] = res == 0;
 746                         avr->sreg[S_N] = (res >> 7) & 1;
 747                         avr->sreg[S_V] = 0;
 748                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 749                         SREG();
 750                 }       break;
 751
 752                 case 0x7000: {  // ANDI Logical AND with Immediate      0111 kkkk dddd kkkk
 753                         get_k_r16(opcode);
 754                         uint8_t res = avr->data[r] & k;
 755                         STATE("andi %s[%02x], 0x%02x\n", avr_regname(r), avr->data[r], k);
 756                         _avr_set_r(avr, r, res);
 757                         avr->sreg[S_Z] = res == 0;
 758                         avr->sreg[S_N] = (res >> 7) & 1;
 759                         avr->sreg[S_V] = 0;
 760                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 761                         SREG();
 762                 }       break;
 763
 764                 case 0xa000:
 765                 case 0x8000: {
 766                         switch (opcode & 0xd008) {
 767                                 case 0xa000:
 768                                 case 0x8000: {  // LD (LDD) – Load Indirect using Z 10q0 qq0r rrrr 0qqq
 769                                         uint16_t v = avr->data[R_ZL] | (avr->data[R_ZH] << 8);
 770                                         uint8_t r = (opcode >> 4) & 0x1f;
 771                                         uint8_t q = ((opcode & 0x2000) >> 8) | ((opcode & 0x0c00) >> 7) | (opcode & 0x7);
 772
 773                                         if (opcode & 0x0200) {
 774                                                 STATE("st (Z+%d[%04x]), %s[%02x]\n", q, v+q, avr_regname(r), avr->data[r]);
 775                                                 _avr_set_ram(avr, v+q, avr->data[r]);
 776                                         } else {
 777                                                 STATE("ld %s, (Z+%d[%04x])=[%02x]\n", avr_regname(r), q, v+q, avr->data[v+q]);
 778                                                 _avr_set_r(avr, r, _avr_get_ram(avr, v+q));
 779                                         }
 780                                         cycle += 1; // 2 cycles, 3 for tinyavr
 781                                 }       break;
 782                                 case 0xa008:
 783                                 case 0x8008: {  // LD (LDD) – Load Indirect using Y 10q0 qq0r rrrr 1qqq
 784                                         uint16_t v = avr->data[R_YL] | (avr->data[R_YH] << 8);
 785                                         uint8_t r = (opcode >> 4) & 0x1f;
 786                                         uint8_t q = ((opcode & 0x2000) >> 8) | ((opcode & 0x0c00) >> 7) | (opcode & 0x7);
 787
 788                                         if (opcode & 0x0200) {
 789                                                 STATE("st (Y+%d[%04x]), %s[%02x]\n", q, v+q, avr_regname(r), avr->data[r]);
 790                                                 _avr_set_ram(avr, v+q, avr->data[r]);
 791                                         } else {
 792                                                 STATE("ld %s, (Y+%d[%04x])=[%02x]\n", avr_regname(r), q, v+q, avr->data[v+q]);
 793                                                 _avr_set_r(avr, r, _avr_get_ram(avr, v+q));
 794                                         }
 795                                         cycle += 1; // 2 cycles, 3 for tinyavr
 796                                 }       break;
 797                                 default: _avr_invalid_opcode(avr);
 798                         }
 799                 }       break;
 800
 801                 case 0x9000: {
 802                         /* this is an annoying special case, but at least these lines handle all the SREG set/clear opcodes */
 803                         if ((opcode & 0xff0f) == 0x9408) {
 804                                 uint8_t b = (opcode >> 4) & 7;
 805                                 STATE("%s%c\n", opcode & 0x0080 ? "cl" : "se", _sreg_bit_name[b]);
 806                                 avr->sreg[b] = (opcode & 0x0080) == 0;
 807                                 SREG();
 808                         } else switch (opcode) {
 809                                 case 0x9588: { // SLEEP
 810                                         STATE("sleep\n");
 811                                         avr->state = cpu_Sleeping;
 812                                 }       break;
 813                                 case 0x9598: { // BREAK
 814                                         STATE("break\n");
 815                                         if (avr->gdb) {
 816                                                 // if gdb is on, we break here as in here
 817                                                 // and we do so until gdb restores the instruction
 818                                                 // that was here before
 819                                                 avr->state = cpu_StepDone;
 820                                                 new_pc = avr->pc;
 821                                                 cycle = 0;
 822                                         }
 823                                 }       break;
 824                                 case 0x95a8: { // WDR
 825                                         STATE("wdr\n");
 826                                         avr_ioctl(avr, AVR_IOCTL_WATCHDOG_RESET, 0);
 827                                 }       break;
 828                                 case 0x95e8: { // SPM
 829                                         STATE("spm\n");
 830                                         avr_ioctl(avr, AVR_IOCTL_FLASH_SPM, 0);
 831                                 }       break;
 832                                 case 0x9409:   // IJMP Indirect jump                                    1001 0100 0000 1001
 833                                 case 0x9419:   // EIJMP Indirect jump                                   1001 0100 0001 1001   bit 4 is "indirect"
 834                                 case 0x9509:   // ICALL Indirect Call to Subroutine             1001 0101 0000 1001
 835                                 case 0x9519: { // EICALL Indirect Call to Subroutine    1001 0101 0001 1001   bit 8 is "push pc"
 836                                         int e = opcode & 0x10;
 837                                         int p = opcode & 0x100;
 838                                         if (e && !avr->eind)
 839                                                 _avr_invalid_opcode(avr);
 840                                         uint16_t z = avr->data[R_ZL] | (avr->data[R_ZH] << 8);
 841                                         if (e)
 842                                                 z |= avr->data[avr->eind] << 16;
 843                                         STATE("%si%s Z[%04x]\n", e?"e":"", p?"call":"jmp", z << 1);
 844                                         if (p) {
 845                                                 cycle++;
 846                                                 _avr_push16(avr, new_pc >> 1);
 847                                         }
 848                                         new_pc = z << 1;
 849                                         cycle++;
 850                                         TRACE_JUMP();
 851                                 }       break;
 852                                 case 0x9518:    // RETI
 853                                 case 0x9508: {  // RET
 854                                         new_pc = _avr_pop16(avr) << 1;
 855                                         if (opcode & 0x10)      // reti
 856                                                 avr->sreg[S_I] = 1;
 857                                         cycle += 3;
 858                                         STATE("ret%s\n", opcode & 0x10 ? "i" : "");
 859                                         TRACE_JUMP();
 860                                         STACK_FRAME_POP();
 861                                 }       break;
 862                                 case 0x95c8: {  // LPM Load Program Memory R0 <- (Z)
 863                                         uint16_t z = avr->data[R_ZL] | (avr->data[R_ZH] << 8);
 864                                         STATE("lpm %s, (Z[%04x])\n", avr_regname(0), z);
 865                                         cycle += 2; // 3 cycles
 866                                         _avr_set_r(avr, 0, avr->flash[z]);
 867                                 }       break;
 868                                 case 0x9408:case 0x9418:case 0x9428:case 0x9438:case 0x9448:case 0x9458:case 0x9468:
 869                                 case 0x9478:
 870                                 {       // BSET 1001 0100 0ddd 1000
 871                                         uint8_t b = (opcode >> 4) & 7;
 872                                         avr->sreg[b] = 1;
 873                                         STATE("bset %c\n", _sreg_bit_name[b]);
 874                                         SREG();
 875                                 }       break;
 876                                 case 0x9488:case 0x9498:case 0x94a8:case 0x94b8:case 0x94c8:case 0x94d8:case 0x94e8:
 877                                 case 0x94f8:    // bit 7 is 'clear vs set'
 878                                 {       // BCLR 1001 0100 1ddd 1000
 879                                         uint8_t b = (opcode >> 4) & 7;
 880                                         avr->sreg[b] = 0;
 881                                         STATE("bclr %c\n", _sreg_bit_name[b]);
 882                                         SREG();
 883                                 }       break;
 884                                 default:  {
 885                                         switch (opcode & 0xfe0f) {
 886                                                 case 0x9000: {  // LDS Load Direct from Data Space, 32 bits
 887                                                         uint8_t r = (opcode >> 4) & 0x1f;
 888                                                         uint16_t x = (avr->flash[new_pc+1] << 8) | avr->flash[new_pc];
 889                                                         new_pc += 2;
 890                                                         STATE("lds %s[%02x], 0x%04x\n", avr_regname(r), avr->data[r], x);
 891                                                         _avr_set_r(avr, r, _avr_get_ram(avr, x));
 892                                                         cycle++; // 2 cycles
 893                                                 }       break;
 894                                                 case 0x9005:
 895                                                 case 0x9004: {  // LPM Load Program Memory 1001 000d dddd 01oo
 896                                                         uint16_t z = avr->data[R_ZL] | (avr->data[R_ZH] << 8);
 897                                                         uint8_t r = (opcode >> 4) & 0x1f;
 898                                                         int op = opcode & 3;
 899                                                         STATE("lpm %s, (Z[%04x]%s)\n", avr_regname(r), z, opcode?"+":"");
 900                                                         _avr_set_r(avr, r, avr->flash[z]);
 901                                                         if (op == 1) {
 902                                                                 z++;
 903                                                                 _avr_set_r(avr, R_ZH, z >> 8);
 904                                                                 _avr_set_r(avr, R_ZL, z);
 905                                                         }
 906                                                         cycle += 2; // 3 cycles
 907                                                 }       break;
 908                                                 case 0x9006:
 909                                                 case 0x9007: {  // ELPM Extended Load Program Memory 1001 000d dddd 01oo
 910                                                         if (!avr->rampz)
 911                                                                 _avr_invalid_opcode(avr);
 912                                                         uint16_t z = avr->data[R_ZL] | (avr->data[R_ZH] << 8) | (avr->data[avr->rampz] << 16);
 913                                                         uint8_t r = (opcode >> 4) & 0x1f;
 914                                                         int op = opcode & 3;
 915                                                         STATE("elpm %s, (Z[%02x:%04x]%s)\n", avr_regname(r), z >> 16, z&0xffff, opcode?"+":"");
 916                                                         _avr_set_r(avr, r, avr->flash[z]);
 917                                                         if (op == 3) {
 918                                                                 z++;
 919                                                                 _avr_set_r(avr, avr->rampz, z >> 16);
 920                                                                 _avr_set_r(avr, R_ZH, z >> 8);
 921                                                                 _avr_set_r(avr, R_ZL, z);
 922                                                         }
 923                                                         cycle += 2; // 3 cycles
 924                                                 }       break;
 925                                                 /*
 926                                                  * Load store instructions
 927                                                  *
 928                                                  * 1001 00sr rrrr iioo
 929                                                  * s = 0 = load, 1 = store
 930                                                  * ii = 16 bits register index, 11 = Z, 10 = Y, 00 = X
 931                                                  * oo = 1) post increment, 2) pre-decrement
 932                                                  */
 933                                                 case 0x900c:
 934                                                 case 0x900d:
 935                                                 case 0x900e: {  // LD Load Indirect from Data using X 1001 000r rrrr 11oo
 936                                                         int op = opcode & 3;
 937                                                         uint8_t r = (opcode >> 4) & 0x1f;
 938                                                         uint16_t x = (avr->data[R_XH] << 8) | avr->data[R_XL];
 939                                                         STATE("ld %s, %sX[%04x]%s\n", avr_regname(r), op == 2 ? "--" : "", x, op == 1 ? "++" : "");
 940                                                         cycle++; // 2 cycles (1 for tinyavr, except with inc/dec 2)
 941                                                         if (op == 2) x--;
 942                                                         _avr_set_r(avr, r, _avr_get_ram(avr, x));
 943                                                         if (op == 1) x++;
 944                                                         _avr_set_r(avr, R_XH, x >> 8);
 945                                                         _avr_set_r(avr, R_XL, x);
 946                                                 }       break;
 947                                                 case 0x920c:
 948                                                 case 0x920d:
 949                                                 case 0x920e: {  // ST Store Indirect Data Space X 1001 001r rrrr 11oo
 950                                                         int op = opcode & 3;
 951                                                         uint8_t r = (opcode >> 4) & 0x1f;
 952                                                         uint16_t x = (avr->data[R_XH] << 8) | avr->data[R_XL];
 953                                                         STATE("st %sX[%04x]%s, %s[%02x] \n", op == 2 ? "--" : "", x, op == 1 ? "++" : "", avr_regname(r), avr->data[r]);
 954                                                         cycle++; // 2 cycles, except tinyavr
 955                                                         if (op == 2) x--;
 956                                                         _avr_set_ram(avr, x, avr->data[r]);
 957                                                         if (op == 1) x++;
 958                                                         _avr_set_r(avr, R_XH, x >> 8);
 959                                                         _avr_set_r(avr, R_XL, x);
 960                                                 }       break;
 961                                                 case 0x9009:
 962                                                 case 0x900a: {  // LD Load Indirect from Data using Y 1001 000r rrrr 10oo
 963                                                         int op = opcode & 3;
 964                                                         uint8_t r = (opcode >> 4) & 0x1f;
 965                                                         uint16_t y = (avr->data[R_YH] << 8) | avr->data[R_YL];
 966                                                         STATE("ld %s, %sY[%04x]%s\n", avr_regname(r), op == 2 ? "--" : "", y, op == 1 ? "++" : "");
 967                                                         cycle++; // 2 cycles, except tinyavr
 968                                                         if (op == 2) y--;
 969                                                         _avr_set_r(avr, r, _avr_get_ram(avr, y));
 970                                                         if (op == 1) y++;
 971                                                         _avr_set_r(avr, R_YH, y >> 8);
 972                                                         _avr_set_r(avr, R_YL, y);
 973                                                 }       break;
 974                                                 case 0x9209:
 975                                                 case 0x920a: {  // ST Store Indirect Data Space Y 1001 001r rrrr 10oo
 976                                                         int op = opcode & 3;
 977                                                         uint8_t r = (opcode >> 4) & 0x1f;
 978                                                         uint16_t y = (avr->data[R_YH] << 8) | avr->data[R_YL];
 979                                                         STATE("st %sY[%04x]%s, %s[%02x]\n", op == 2 ? "--" : "", y, op == 1 ? "++" : "", avr_regname(r), avr->data[r]);
 980                                                         cycle++;
 981                                                         if (op == 2) y--;
 982                                                         _avr_set_ram(avr, y, avr->data[r]);
 983                                                         if (op == 1) y++;
 984                                                         _avr_set_r(avr, R_YH, y >> 8);
 985                                                         _avr_set_r(avr, R_YL, y);
 986                                                 }       break;
 987                                                 case 0x9200: {  // STS ! Store Direct to Data Space, 32 bits
 988                                                         uint8_t r = (opcode >> 4) & 0x1f;
 989                                                         uint16_t x = (avr->flash[new_pc+1] << 8) | avr->flash[new_pc];
 990                                                         new_pc += 2;
 991                                                         STATE("sts 0x%04x, %s[%02x]\n", x, avr_regname(r), avr->data[r]);
 992                                                         cycle++;
 993                                                         _avr_set_ram(avr, x, avr->data[r]);
 994                                                 }       break;
 995                                                 case 0x9001:
 996                                                 case 0x9002: {  // LD Load Indirect from Data using Z 1001 001r rrrr 00oo
 997                                                         int op = opcode & 3;
 998                                                         uint8_t r = (opcode >> 4) & 0x1f;
 999                                                         uint16_t z = (avr->data[R_ZH] << 8) | avr->data[R_ZL];
1000                                                         STATE("ld %s, %sZ[%04x]%s\n", avr_regname(r), op == 2 ? "--" : "", z, op == 1 ? "++" : "");
1001                                                         cycle++;; // 2 cycles, except tinyavr
1002                                                         if (op == 2) z--;
1003                                                         _avr_set_r(avr, r, _avr_get_ram(avr, z));
1004                                                         if (op == 1) z++;
1005                                                         _avr_set_r(avr, R_ZH, z >> 8);
1006                                                         _avr_set_r(avr, R_ZL, z);
1007                                                 }       break;
1008                                                 case 0x9201:
1009                                                 case 0x9202: {  // ST Store Indirect Data Space Z 1001 001r rrrr 00oo
1010                                                         int op = opcode & 3;
1011                                                         uint8_t r = (opcode >> 4) & 0x1f;
1012                                                         uint16_t z = (avr->data[R_ZH] << 8) | avr->data[R_ZL];
1013                                                         STATE("st %sZ[%04x]%s, %s[%02x] \n", op == 2 ? "--" : "", z, op == 1 ? "++" : "", avr_regname(r), avr->data[r]);
1014                                                         cycle++; // 2 cycles, except tinyavr
1015                                                         if (op == 2) z--;
1016                                                         _avr_set_ram(avr, z, avr->data[r]);
1017                                                         if (op == 1) z++;
1018                                                         _avr_set_r(avr, R_ZH, z >> 8);
1019                                                         _avr_set_r(avr, R_ZL, z);
1020                                                 }       break;
1021                                                 case 0x900f: {  // POP 1001 000d dddd 1111
1022                                                         uint8_t r = (opcode >> 4) & 0x1f;
1023                                                         _avr_set_r(avr, r, _avr_pop8(avr));
1024                                                         T(uint16_t sp = _avr_sp_get(avr);)
1025                                                         STATE("pop %s (@%04x)[%02x]\n", avr_regname(r), sp, avr->data[sp]);
1026                                                         cycle++;
1027                                                 }       break;
1028                                                 case 0x920f: {  // PUSH 1001 001d dddd 1111
1029                                                         uint8_t r = (opcode >> 4) & 0x1f;
1030                                                         _avr_push8(avr, avr->data[r]);
1031                                                         T(uint16_t sp = _avr_sp_get(avr);)
1032                                                         STATE("push %s[%02x] (@%04x)\n", avr_regname(r), avr->data[r], sp);
1033                                                         cycle++;
1034                                                 }       break;
1035                                                 case 0x9400: {  // COM – One’s Complement
1036                                                         uint8_t r = (opcode >> 4) & 0x1f;
1037                                                         uint8_t res = 0xff - avr->data[r];
1038                                                         STATE("com %s[%02x] = %02x\n", avr_regname(r), avr->data[r], res);
1039                                                         _avr_set_r(avr, r, res);
1040                                                         avr->sreg[S_Z] = res == 0;
1041                                                         avr->sreg[S_N] = res >> 7;
1042                                                         avr->sreg[S_V] = 0;
1043                                                         avr->sreg[S_C] = 1;
1044                                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
1045                                                         SREG();
1046                                                 }       break;
1047                                                 case 0x9401: {  // NEG – Two’s Complement
1048                                                         uint8_t r = (opcode >> 4) & 0x1f;
1049                                                         uint8_t rd = avr->data[r];
1050                                                         uint8_t res = 0x00 - rd;
1051                                                         STATE("neg %s[%02x] = %02x\n", avr_regname(r), rd, res);
1052                                                         _avr_set_r(avr, r, res);
1053                                                         avr->sreg[S_H] = ((res >> 3) | (rd >> 3)) & 1;
1054                                                         avr->sreg[S_Z] = res == 0;
1055                                                         avr->sreg[S_N] = res >> 7;
1056                                                         avr->sreg[S_V] = res == 0x80;
1057                                                         avr->sreg[S_C] = res != 0;
1058                                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
1059                                                         SREG();
1060                                                 }       break;
1061                                                 case 0x9402: {  // SWAP – Swap Nibbles
1062                                                         uint8_t r = (opcode >> 4) & 0x1f;
1063                                                         uint8_t res = (avr->data[r] >> 4) | (avr->data[r] << 4) ;
1064                                                         STATE("swap %s[%02x] = %02x\n", avr_regname(r), avr->data[r], res);
1065                                                         _avr_set_r(avr, r, res);
1066                                                 }       break;
1067                                                 case 0x9403: {  // INC – Increment
1068                                                         uint8_t r = (opcode >> 4) & 0x1f;
1069                                                         uint8_t res = avr->data[r] + 1;
1070                                                         STATE("inc %s[%02x] = %02x\n", avr_regname(r), avr->data[r], res);
1071                                                         _avr_set_r(avr, r, res);
1072                                                         avr->sreg[S_Z] = res == 0;
1073                                                         avr->sreg[S_N] = res >> 7;
1074                                                         avr->sreg[S_V] = res == 0x7f;
1075                                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
1076                                                         SREG();
1077                                                 }       break;
1078                                                 case 0x9405: {  // ASR – Arithmetic Shift Right 1001 010d dddd 0101
1079                                                         uint8_t r = (opcode >> 4) & 0x1f;
1080                                                         uint8_t vr = avr->data[r];
1081                                                         uint8_t res = (vr >> 1) | (vr & 0x80);
1082                                                         STATE("asr %s[%02x]\n", avr_regname(r), vr);
1083                                                         _avr_set_r(avr, r, res);
1084                                                         avr->sreg[S_Z] = res == 0;
1085                                                         avr->sreg[S_C] = vr & 1;
1086                                                         avr->sreg[S_N] = res >> 7;
1087                                                         avr->sreg[S_V] = avr->sreg[S_N] ^ avr->sreg[S_C];
1088                                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
1089                                                         SREG();
1090                                                 }       break;
1091                                                 case 0x9406: {  // LSR 1001 010d dddd 0110
1092                                                         uint8_t r = (opcode >> 4) & 0x1f;
1093                                                         uint8_t vr = avr->data[r];
1094                                                         uint8_t res = vr >> 1;
1095                                                         STATE("lsr %s[%02x]\n", avr_regname(r), vr);
1096                                                         _avr_set_r(avr, r, res);
1097                                                         avr->sreg[S_Z] = res == 0;
1098                                                         avr->sreg[S_C] = vr & 1;
1099                                                         avr->sreg[S_N] = 0;
1100                                                         avr->sreg[S_V] = avr->sreg[S_N] ^ avr->sreg[S_C];
1101                                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
1102                                                         SREG();
1103                                                 }       break;
1104                                                 case 0x9407: {  // ROR 1001 010d dddd 0111
1105                                                         uint8_t r = (opcode >> 4) & 0x1f;
1106                                                         uint8_t vr = avr->data[r];
1107                                                         uint8_t res = (avr->sreg[S_C] ? 0x80 : 0) | vr >> 1;
1108                                                         STATE("ror %s[%02x]\n", avr_regname(r), vr);
1109                                                         _avr_set_r(avr, r, res);
1110                                                         avr->sreg[S_Z] = res == 0;
1111                                                         avr->sreg[S_C] = vr & 1;
1112                                                         avr->sreg[S_N] = 0;
1113                                                         avr->sreg[S_V] = avr->sreg[S_N] ^ avr->sreg[S_C];
1114                                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
1115                                                         SREG();
1116                                                 }       break;
1117                                                 case 0x940a: {  // DEC – Decrement
1118                                                         uint8_t r = (opcode >> 4) & 0x1f;
1119                                                         uint8_t res = avr->data[r] - 1;
1120                                                         STATE("dec %s[%02x] = %02x\n", avr_regname(r), avr->data[r], res);
1121                                                         _avr_set_r(avr, r, res);
1122                                                         avr->sreg[S_Z] = res == 0;
1123                                                         avr->sreg[S_N] = res >> 7;
1124                                                         avr->sreg[S_V] = res == 0x80;
1125                                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
1126                                                         SREG();
1127                                                 }       break;
1128                                                 case 0x940c:
1129                                                 case 0x940d: {  // JMP Long Call to sub, 32 bits
1130                                                         uint32_t a = ((opcode & 0x01f0) >> 3) | (opcode & 1);
1131                                                         uint16_t x = (avr->flash[new_pc+1] << 8) | avr->flash[new_pc];
1132                                                         a = (a << 16) | x;
1133                                                         STATE("jmp 0x%06x\n", a);
1134                                                         new_pc = a << 1;
1135                                                         cycle += 2;
1136                                                         TRACE_JUMP();
1137                                                 }       break;
1138                                                 case 0x940e:
1139                                                 case 0x940f: {  // CALL Long Call to sub, 32 bits
1140                                                         uint32_t a = ((opcode & 0x01f0) >> 3) | (opcode & 1);
1141                                                         uint16_t x = (avr->flash[new_pc+1] << 8) | avr->flash[new_pc];
1142                                                         a = (a << 16) | x;
1143                                                         STATE("call 0x%06x\n", a);
1144                                                         new_pc += 2;
1145                                                         _avr_push16(avr, new_pc >> 1);
1146                                                         new_pc = a << 1;
1147                                                         cycle += 3;     // 4 cycles; FIXME 5 on devices with 22 bit PC
1148                                                         TRACE_JUMP();
1149                                                         STACK_FRAME_PUSH();
1150                                                 }       break;
1151
1152                                                 default: {
1153                                                         switch (opcode & 0xff00) {
1154                                                                 case 0x9600: {  // ADIW - Add Immediate to Word 1001 0110 KKdd KKKK
1155                                                                         uint8_t r = 24 + ((opcode >> 3) & 0x6);
1156                                                                         uint8_t k = ((opcode & 0x00c0) >> 2) | (opcode & 0xf);
1157                                                                         uint8_t rdl = avr->data[r], rdh = avr->data[r+1];
1158                                                                         uint32_t res = rdl | (rdh << 8);
1159                                                                         STATE("adiw %s:%s[%04x], 0x%02x\n", avr_regname(r), avr_regname(r+1), res, k);
1160                                                                         res += k;
1161                                                                         _avr_set_r(avr, r + 1, res >> 8);
1162                                                                         _avr_set_r(avr, r, res);
1163                                                                         avr->sreg[S_V] = ~(rdh >> 7) & ((res >> 15) & 1);
1164                                                                         avr->sreg[S_Z] = (res & 0xffff) == 0;
1165                                                                         avr->sreg[S_N] = (res >> 15) & 1;
1166                                                                         avr->sreg[S_C] = ~((res >> 15) & 1) & (rdh >> 7);
1167                                                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
1168                                                                         SREG();
1169                                                                         cycle++;
1170                                                                 }       break;
1171                                                                 case 0x9700: {  // SBIW - Subtract Immediate from Word 1001 0110 KKdd KKKK
1172                                                                         uint8_t r = 24 + ((opcode >> 3) & 0x6);
1173                                                                         uint8_t k = ((opcode & 0x00c0) >> 2) | (opcode & 0xf);
1174                                                                         uint8_t rdl = avr->data[r], rdh = avr->data[r+1];
1175                                                                         uint32_t res = rdl | (rdh << 8);
1176                                                                         STATE("sbiw %s:%s[%04x], 0x%02x\n", avr_regname(r), avr_regname(r+1), res, k);
1177                                                                         res -= k;
1178                                                                         _avr_set_r(avr, r + 1, res >> 8);
1179                                                                         _avr_set_r(avr, r, res);
1180                                                                         avr->sreg[S_V] = (rdh >> 7) & (~(res >> 15) & 1);
1181                                                                         avr->sreg[S_Z] = (res & 0xffff) == 0;
1182                                                                         avr->sreg[S_N] = (res >> 15) & 1;
1183                                                                         avr->sreg[S_C] = ((res >> 15) & 1) & (~rdh >> 7);
1184                                                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
1185                                                                         SREG();
1186                                                                         cycle++;
1187                                                                 }       break;
1188                                                                 case 0x9800: {  // CBI - Clear Bit in I/O Register 1001 1000 AAAA Abbb
1189                                                                         uint8_t io = ((opcode >> 3) & 0x1f) + 32;
1190                                                                         uint8_t b = opcode & 0x7;
1191                                                                         uint8_t res = _avr_get_ram(avr, io) & ~(1 << b);
1192                                                                         STATE("cbi %s[%04x], 0x%02x = %02x\n", avr_regname(io), avr->data[io], 1<<b, res);
1193                                                                         _avr_set_ram(avr, io, res);
1194                                                                         cycle++;
1195                                                                 }       break;
1196                                                                 case 0x9900: {  // SBIC - Skip if Bit in I/O Register is Cleared 1001 0111 AAAA Abbb
1197                                                                         uint8_t io = ((opcode >> 3) & 0x1f) + 32;
1198                                                                         uint8_t b = opcode & 0x7;
1199                                                                         uint8_t res = _avr_get_ram(avr, io) & (1 << b);
1200                                                                         STATE("sbic %s[%04x], 0x%02x\t; Will%s branch\n", avr_regname(io), avr->data[io], 1<<b, !res?"":" not");
1201                                                                         if (!res) {
1202                                                                                 if (_avr_is_instruction_32_bits(avr, new_pc)) {
1203                                                                                         new_pc += 4; cycle += 2;
1204                                                                                 } else {
1205                                                                                         new_pc += 2; cycle++;
1206                                                                                 }
1207                                                                         }
1208                                                                 }       break;
1209                                                                 case 0x9a00: {  // SBI - Set Bit in I/O Register 1001 1000 AAAA Abbb
1210                                                                         uint8_t io = ((opcode >> 3) & 0x1f) + 32;
1211                                                                         uint8_t b = opcode & 0x7;
1212                                                                         uint8_t res = _avr_get_ram(avr, io) | (1 << b);
1213                                                                         STATE("sbi %s[%04x], 0x%02x = %02x\n", avr_regname(io), avr->data[io], 1<<b, res);
1214                                                                         _avr_set_ram(avr, io, res);
1215                                                                         cycle++;
1216                                                                 }       break;
1217                                                                 case 0x9b00: {  // SBIS - Skip if Bit in I/O Register is Set 1001 1011 AAAA Abbb
1218                                                                         uint8_t io = ((opcode >> 3) & 0x1f) + 32;
1219                                                                         uint8_t b = opcode & 0x7;
1220                                                                         uint8_t res = _avr_get_ram(avr, io) & (1 << b);
1221                                                                         STATE("sbis %s[%04x], 0x%02x\t; Will%s branch\n", avr_regname(io), avr->data[io], 1<<b, res?"":" not");
1222                                                                         if (res) {
1223                                                                                 if (_avr_is_instruction_32_bits(avr, new_pc)) {
1224                                                                                         new_pc += 4; cycle += 2;
1225                                                                                 } else {
1226                                                                                         new_pc += 2; cycle++;
1227                                                                                 }
1228                                                                         }
1229                                                                 }       break;
1230                                                                 default:
1231                                                                         switch (opcode & 0xfc00) {
1232                                                                                 case 0x9c00: {  // MUL - Multiply Unsigned 1001 11rd dddd rrrr
1233                                                                                         get_r_d_10(opcode);
1234                                                                                         uint16_t res = vd * vr;
1235                                                                                         STATE("mul %s[%02x], %s[%02x] = %04x\n", avr_regname(d), vd, avr_regname(r), vr, res);
1236                                                                                         cycle++;
1237                                                                                         _avr_set_r(avr, 0, res);
1238                                                                                         _avr_set_r(avr, 1, res >> 8);
1239                                                                                         avr->sreg[S_Z] = res == 0;
1240                                                                                         avr->sreg[S_C] = (res >> 15) & 1;
1241                                                                                         SREG();
1242                                                                                 }       break;
1243                                                                                 default: _avr_invalid_opcode(avr);
1244                                                                         }
1245                                                         }
1246                                                 }       break;
1247                                         }
1248                                 }       break;
1249                         }
1250                 }       break;
1251
1252                 case 0xb000: {
1253                         switch (opcode & 0xf800) {
1254                                 case 0xb800: {  // OUT A,Rr 1011 1AAr rrrr AAAA
1255                                         uint8_t r = (opcode >> 4) & 0x1f;
1256                                         uint8_t A = ((((opcode >> 9) & 3) << 4) | ((opcode) & 0xf)) + 32;
1257                                         STATE("out %s, %s[%02x]\n", avr_regname(A), avr_regname(r), avr->data[r]);
1258                                         _avr_set_ram(avr, A, avr->data[r]);
1259                                 }       break;
1260                                 case 0xb000: {  // IN Rd,A 1011 0AAr rrrr AAAA
1261                                         uint8_t r = (opcode >> 4) & 0x1f;
1262                                         uint8_t A = ((((opcode >> 9) & 3) << 4) | ((opcode) & 0xf)) + 32;
1263                                         STATE("in %s, %s[%02x]\n", avr_regname(r), avr_regname(A), avr->data[A]);
1264                                         _avr_set_r(avr, r, _avr_get_ram(avr, A));
1265                                 }       break;
1266                                 default: _avr_invalid_opcode(avr);
1267                         }
1268                 }       break;
1269
1270                 case 0xc000: {
1271                         // RJMP 1100 kkkk kkkk kkkk
1272                         short o = ((short)(opcode << 4)) >> 4;
1273                         STATE("rjmp .%d [%04x]\n", o, new_pc + (o << 1));
1274                         new_pc = new_pc + (o << 1);
1275                         cycle++;
1276                         TRACE_JUMP();
1277                 }       break;
1278
1279                 case 0xd000: {
1280                         // RCALL 1100 kkkk kkkk kkkk
1281                         short o = ((short)(opcode << 4)) >> 4;
1282                         STATE("rcall .%d [%04x]\n", o, new_pc + (o << 1));
1283                         _avr_push16(avr, new_pc >> 1);
1284                         new_pc = new_pc + (o << 1);
1285                         cycle += 2;
1286                         // 'rcall .1' is used as a cheap "push 16 bits of room on the stack"
1287                         if (o != 0) {
1288                                 TRACE_JUMP();
1289                                 STACK_FRAME_PUSH();
1290                         }
1291                 }       break;
1292
1293                 case 0xe000: {  // LDI Rd, K 1110 KKKK RRRR KKKK -- aka SER (LDI r, 0xff)
1294                         uint8_t d = 16 + ((opcode >> 4) & 0xf);
1295                         uint8_t k = ((opcode & 0x0f00) >> 4) | (opcode & 0xf);
1296                         STATE("ldi %s, 0x%02x\n", avr_regname(d), k);
1297                         _avr_set_r(avr, d, k);
1298                 }       break;
1299
1300                 case 0xf000: {
1301                         switch (opcode & 0xfe00) {
1302                                 case 0xf000:
1303                                 case 0xf200:
1304                                 case 0xf400:
1305                                 case 0xf600: {  // All the SREG branches
1306                                         short o = ((short)(opcode << 6)) >> 9; // offset
1307                                         uint8_t s = opcode & 7;
1308                                         int set = (opcode & 0x0400) == 0;               // this bit means BRXC otherwise BRXS
1309                                         int branch = (avr->sreg[s] && set) || (!avr->sreg[s] && !set);
1310                                         const char *names[2][8] = {
1311                                                         { "brcc", "brne", "brpl", "brvc", NULL, "brhc", "brtc", "brid"},
1312                                                         { "brcs", "breq", "brmi", "brvs", NULL, "brhs", "brts", "brie"},
1313                                         };
1314                                         if (names[set][s]) {
1315                                                 STATE("%s .%d [%04x]\t; Will%s branch\n", names[set][s], o, new_pc + (o << 1), branch ? "":" not");
1316                                         } else {
1317                                                 STATE("%s%c .%d [%04x]\t; Will%s branch\n", set ? "brbs" : "brbc", _sreg_bit_name[s], o, new_pc + (o << 1), branch ? "":" not");
1318                                         }
1319                                         if (branch) {
1320                                                 cycle++; // 2 cycles if taken, 1 otherwise
1321                                                 new_pc = new_pc + (o << 1);
1322                                         }
1323                                 }       break;
1324                                 case 0xf800:
1325                                 case 0xf900: {  // BLD – Bit Store from T into a Bit in Register 1111 100r rrrr 0bbb
1326                                         uint8_t r = (opcode >> 4) & 0x1f; // register index
1327                                         uint8_t s = opcode & 7;
1328                                         uint8_t v = avr->data[r] | (avr->sreg[S_T] ? (1 << s) : 0);
1329                                         STATE("bld %s[%02x], 0x%02x = %02x\n", avr_regname(r), avr->data[r], 1 << s, v);
1330                                         _avr_set_r(avr, r, v);
1331                                 }       break;
1332                                 case 0xfa00:
1333                                 case 0xfb00:{   // BST – Bit Store into T from bit in Register 1111 100r rrrr 0bbb
1334                                         uint8_t r = (opcode >> 4) & 0x1f; // register index
1335                                         uint8_t s = opcode & 7;
1336                                         STATE("bst %s[%02x], 0x%02x\n", avr_regname(r), avr->data[r], 1 << s);
1337                                         avr->sreg[S_T] = (avr->data[r] >> s) & 1;
1338                                         SREG();
1339                                 }       break;
1340                                 case 0xfc00:
1341                                 case 0xfe00: {  // SBRS/SBRC – Skip if Bit in Register is Set/Clear 1111 11sr rrrr 0bbb
1342                                         uint8_t r = (opcode >> 4) & 0x1f; // register index
1343                                         uint8_t s = opcode & 7;
1344                                         int set = (opcode & 0x0200) != 0;
1345                                         int branch = ((avr->data[r] & (1 << s)) && set) || (!(avr->data[r] & (1 << s)) && !set);
1346                                         STATE("%s %s[%02x], 0x%02x\t; Will%s branch\n", set ? "sbrs" : "sbrc", avr_regname(r), avr->data[r], 1 << s, branch ? "":" not");
1347                                         if (branch) {
1348                                                 if (_avr_is_instruction_32_bits(avr, new_pc)) {
1349                                                         new_pc += 4; cycle += 2;
1350                                                 } else {
1351                                                         new_pc += 2; cycle++;
1352                                                 }
1353                                         }
1354                                 }       break;
1355                                 default: _avr_invalid_opcode(avr);
1356                         }
1357                 }       break;
1358
1359                 default: _avr_invalid_opcode(avr);
1360
1361         }
1362         avr->cycle += cycle;
1363         return new_pc;
1364 }
1365
1366