git.rot13.org Git - simavr/blob - simavr/sim/sim_core.c

   1 /*
   2         sim_core.c
   3
   4         Copyright 2008, 2009 Michel Pollet <buserror@gmail.com>
   5
   6         This file is part of simavr.
   7
   8         simavr is free software: you can redistribute it and/or modify
   9         it under the terms of the GNU General Public License as published by
  10         the Free Software Foundation, either version 3 of the License, or
  11         (at your option) any later version.
  12
  13         simavr is distributed in the hope that it will be useful,
  14         but WITHOUT ANY WARRANTY; without even the implied warranty of
  15         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16         GNU General Public License for more details.
  17
  18         You should have received a copy of the GNU General Public License
  19         along with simavr.  If not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include <stdlib.h>
  23 #include <stdio.h>
  24 #include <string.h>
  25 #include <ctype.h>
  26 #include "sim_avr.h"
  27 #include "sim_core.h"
  28 #include "avr_flash.h"
  29 #include "avr_watchdog.h"
  30
  31 // SREG bit names
  32 const char * _sreg_bit_name = "cznvshti";
  33
  34 #ifdef NO_COLOR
  35         #define FONT_RED
  36         #define FONT_DEFAULT
  37 #else
  38         #define FONT_RED                "\e[31m"
  39         #define FONT_DEFAULT    "\e[0m"
  40 #endif
  41
  42 /*
  43  * Handle "touching" registers, marking them changed.
  44  * This is used only for debugging purposes to be able to
  45  * print the effects of each instructions on registers
  46  */
  47 #if CONFIG_SIMAVR_TRACE
  48
  49 #define T(w) w
  50
  51 #define REG_TOUCH(a, r) (a)->trace_data->touched[(r) >> 5] |= (1 << ((r) & 0x1f))
  52 #define REG_ISTOUCHED(a, r) ((a)->trace_data->touched[(r) >> 5] & (1 << ((r) & 0x1f)))
  53
  54 /*
  55  * This allows a "special case" to skip instruction tracing when in these
  56  * symbols since printf() is useful to have, but generates a lot of cycles.
  57  */
  58 int dont_trace(const char * name)
  59 {
  60         return (
  61                 !strcmp(name, "uart_putchar") ||
  62                 !strcmp(name, "fputc") ||
  63                 !strcmp(name, "printf") ||
  64                 !strcmp(name, "vfprintf") ||
  65                 !strcmp(name, "__ultoa_invert") ||
  66                 !strcmp(name, "__prologue_saves__") ||
  67                 !strcmp(name, "__epilogue_restores__"));
  68 }
  69
  70 int donttrace = 0;
  71
  72 #define STATE(_f, args...) { \
  73         if (avr->trace) {\
  74                 if (avr->trace_data->codeline && avr->trace_data->codeline[avr->pc>>1]) {\
  75                         const char * symn = avr->trace_data->codeline[avr->pc>>1]->symbol; \
  76                         int dont = 0 && dont_trace(symn);\
  77                         if (dont!=donttrace) { \
  78                                 donttrace = dont;\
  79                                 DUMP_REG();\
  80                         }\
  81                         if (donttrace==0)\
  82                                 printf("%04x: %-25s " _f, avr->pc, symn, ## args);\
  83                 } else \
  84                         printf("%s: %04x: " _f, __FUNCTION__, avr->pc, ## args);\
  85                 }\
  86         }
  87 #define SREG() if (avr->trace && donttrace == 0) {\
  88         printf("%04x: \t\t\t\t\t\t\t\t\tSREG = ", avr->pc); \
  89         for (int _sbi = 0; _sbi < 8; _sbi++)\
  90                 printf("%c", avr->sreg[_sbi] ? toupper(_sreg_bit_name[_sbi]) : '.');\
  91         printf("\n");\
  92 }
  93 #else
  94 #define T(w)
  95 #define REG_TOUCH(a, r)
  96 #define STATE(_f, args...)
  97 #define SREG()
  98 #endif
  99
 100 void avr_core_watch_write(avr_t *avr, uint16_t addr, uint8_t v)
 101 {
 102         if (addr > avr->ramend) {
 103                 printf("*** Invalid write address PC=%04x SP=%04x O=%04x Address %04x=%02x out of ram\n",
 104                                 avr->pc, _avr_sp_get(avr), avr->flash[avr->pc + 1] | (avr->flash[avr->pc]<<8), addr, v);
 105                 CRASH();
 106         }
 107         if (addr < 32) {
 108                 printf("*** Invalid write address PC=%04x SP=%04x O=%04x Address %04x=%02x low registers\n",
 109                                 avr->pc, _avr_sp_get(avr), avr->flash[avr->pc + 1] | (avr->flash[avr->pc]<<8), addr, v);
 110                 CRASH();
 111         }
 112 #if AVR_STACK_WATCH
 113         /*
 114          * this checks that the current "function" is not doctoring the stack frame that is located
 115          * higher on the stack than it should be. It's a sign of code that has overrun it's stack
 116          * frame and is munching on it's own return address.
 117          */
 118         if (avr->trace_data->stack_frame_index > 1 && addr > avr->trace_data->stack_frame[avr->trace_data->stack_frame_index-2].sp) {
 119                 printf( FONT_RED "%04x : munching stack SP %04x, A=%04x <= %02x\n" FONT_DEFAULT, avr->pc, _avr_sp_get(avr), addr, v);
 120         }
 121 #endif
 122         avr->data[addr] = v;
 123 }
 124
 125 uint8_t avr_core_watch_read(avr_t *avr, uint16_t addr)
 126 {
 127         if (addr > avr->ramend) {
 128                 printf( FONT_RED "*** Invalid read address PC=%04x SP=%04x O=%04x Address %04x out of ram (%04x)\n" FONT_DEFAULT,
 129                                 avr->pc, _avr_sp_get(avr), avr->flash[avr->pc + 1] | (avr->flash[avr->pc]<<8), addr, avr->ramend);
 130                 CRASH();
 131         }
 132         return avr->data[addr];
 133 }
 134
 135 /*
 136  * Set a register (r < 256)
 137  * if it's an IO register (> 31) also (try to) call any callback that was
 138  * registered to track changes to that register.
 139  */
 140 static inline void _avr_set_r(avr_t * avr, uint8_t r, uint8_t v)
 141 {
 142         REG_TOUCH(avr, r);
 143
 144         if (r == R_SREG) {
 145                 avr->data[R_SREG] = v;
 146                 // unsplit the SREG
 147                 for (int i = 0; i < 8; i++)
 148                         avr->sreg[i] = (v & (1 << i)) != 0;
 149                 SREG();
 150         }
 151         if (r > 31) {
 152                 uint8_t io = AVR_DATA_TO_IO(r);
 153                 if (avr->io[io].w.c)
 154                         avr->io[io].w.c(avr, r, v, avr->io[io].w.param);
 155                 else
 156                         avr->data[r] = v;
 157                 if (avr->io[io].irq) {
 158                         avr_raise_irq(avr->io[io].irq + AVR_IOMEM_IRQ_ALL, v);
 159                         for (int i = 0; i < 8; i++)
 160                                 avr_raise_irq(avr->io[io].irq + i, (v >> i) & 1);
 161                 }
 162         } else
 163                 avr->data[r] = v;
 164 }
 165
 166 /*
 167  * Stack pointer access
 168  */
 169 inline uint16_t _avr_sp_get(avr_t * avr)
 170 {
 171         return avr->data[R_SPL] | (avr->data[R_SPH] << 8);
 172 }
 173
 174 inline void _avr_sp_set(avr_t * avr, uint16_t sp)
 175 {
 176         _avr_set_r(avr, R_SPL, sp);
 177         _avr_set_r(avr, R_SPH, sp >> 8);
 178 }
 179
 180 /*
 181  * Set any address to a value; split between registers and SRAM
 182  */
 183 static inline void _avr_set_ram(avr_t * avr, uint16_t addr, uint8_t v)
 184 {
 185         if (addr < 256)
 186                 _avr_set_r(avr, addr, v);
 187         else
 188                 avr_core_watch_write(avr, addr, v);
 189 }
 190
 191 /*
 192  * Get a value from SRAM.
 193  */
 194 static inline uint8_t _avr_get_ram(avr_t * avr, uint16_t addr)
 195 {
 196         if (addr == R_SREG) {
 197                 /*
 198                  * SREG is special it's reconstructed when read
 199                  * while the core itself uses the "shortcut" array
 200                  */
 201                 avr->data[R_SREG] = 0;
 202                 for (int i = 0; i < 8; i++)
 203                         if (avr->sreg[i] > 1) {
 204                                 printf("** Invalid SREG!!\n");
 205                                 CRASH();
 206                         } else if (avr->sreg[i])
 207                                 avr->data[R_SREG] |= (1 << i);
 208
 209         } else if (addr > 31 && addr < 256) {
 210                 uint8_t io = AVR_DATA_TO_IO(addr);
 211
 212                 if (avr->io[io].r.c)
 213                         avr->data[addr] = avr->io[io].r.c(avr, addr, avr->io[io].r.param);
 214
 215                 if (avr->io[io].irq) {
 216                         uint8_t v = avr->data[addr];
 217                         avr_raise_irq(avr->io[io].irq + AVR_IOMEM_IRQ_ALL, v);
 218                         for (int i = 0; i < 8; i++)
 219                                 avr_raise_irq(avr->io[io].irq + i, (v >> i) & 1);
 220                 }
 221         }
 222         return avr_core_watch_read(avr, addr);
 223 }
 224
 225 /*
 226  * Stack push accessors. Push/pop 8 and 16 bits
 227  */
 228 static inline void _avr_push8(avr_t * avr, uint16_t v)
 229 {
 230         uint16_t sp = _avr_sp_get(avr);
 231         _avr_set_ram(avr, sp, v);
 232         _avr_sp_set(avr, sp-1);
 233 }
 234
 235 static inline uint8_t _avr_pop8(avr_t * avr)
 236 {
 237         uint16_t sp = _avr_sp_get(avr) + 1;
 238         uint8_t res = _avr_get_ram(avr, sp);
 239         _avr_sp_set(avr, sp);
 240         return res;
 241 }
 242
 243 inline void _avr_push16(avr_t * avr, uint16_t v)
 244 {
 245         _avr_push8(avr, v);
 246         _avr_push8(avr, v >> 8);
 247 }
 248
 249 static inline uint16_t _avr_pop16(avr_t * avr)
 250 {
 251         uint16_t res = _avr_pop8(avr) << 8;
 252         res |= _avr_pop8(avr);
 253         return res;
 254 }
 255
 256 /*
 257  * "Pretty" register names
 258  */
 259 const char * reg_names[255] = {
 260                 [R_XH] = "XH", [R_XL] = "XL",
 261                 [R_YH] = "YH", [R_YL] = "YL",
 262                 [R_ZH] = "ZH", [R_ZL] = "ZL",
 263                 [R_SPH] = "SPH", [R_SPL] = "SPL",
 264                 [R_SREG] = "SREG",
 265 };
 266
 267
 268 const char * avr_regname(uint8_t reg)
 269 {
 270         if (!reg_names[reg]) {
 271                 char tt[16];
 272                 if (reg < 32)
 273                         sprintf(tt, "r%d", reg);
 274                 else
 275                         sprintf(tt, "io:%02x", reg);
 276                 reg_names[reg] = strdup(tt);
 277         }
 278         return reg_names[reg];
 279 }
 280
 281 /*
 282  * Called when an invalid opcode is decoded
 283  */
 284 static void _avr_invalid_opcode(avr_t * avr)
 285 {
 286 #if CONFIG_SIMAVR_TRACE
 287         printf( FONT_RED "*** %04x: %-25s Invalid Opcode SP=%04x O=%04x \n" FONT_DEFAULT,
 288                         avr->pc, avr->trace_data->codeline[avr->pc>>1]->symbol, _avr_sp_get(avr), avr->flash[avr->pc] | (avr->flash[avr->pc+1]<<8));
 289 #else
 290         printf( FONT_RED "*** %04x: Invalid Opcode SP=%04x O=%04x \n" FONT_DEFAULT,
 291                         avr->pc, _avr_sp_get(avr), avr->flash[avr->pc] | (avr->flash[avr->pc+1]<<8));
 292 #endif
 293 }
 294
 295 #if CONFIG_SIMAVR_TRACE
 296 /*
 297  * Dump changed registers when tracing
 298  */
 299 void avr_dump_state(avr_t * avr)
 300 {
 301         if (!avr->trace || donttrace)
 302                 return;
 303
 304         int doit = 0;
 305
 306         for (int r = 0; r < 3 && !doit; r++)
 307                 if (avr->trace_data->touched[r])
 308                         doit = 1;
 309         if (!doit)
 310                 return;
 311         printf("                                       ->> ");
 312         const int r16[] = { R_SPL, R_XL, R_YL, R_ZL };
 313         for (int i = 0; i < 4; i++)
 314                 if (REG_ISTOUCHED(avr, r16[i]) || REG_ISTOUCHED(avr, r16[i]+1)) {
 315                         REG_TOUCH(avr, r16[i]);
 316                         REG_TOUCH(avr, r16[i]+1);
 317                 }
 318
 319         for (int i = 0; i < 3*32; i++)
 320                 if (REG_ISTOUCHED(avr, i)) {
 321                         printf("%s=%02x ", avr_regname(i), avr->data[i]);
 322                 }
 323         printf("\n");
 324 }
 325 #endif
 326
 327 #define get_r_d_10(o) \
 328                 const uint8_t r = ((o >> 5) & 0x10) | (o & 0xf); \
 329                 const uint8_t d = (o >> 4) & 0x1f;\
 330                 const uint8_t vd = avr->data[d], vr = avr->data[r];
 331 #define get_r_dd_10(o) \
 332                 const uint8_t r = ((o >> 5) & 0x10) | (o & 0xf); \
 333                 const uint8_t d = (o >> 4) & 0x1f;\
 334                 const uint8_t vr = avr->data[r];
 335 #define get_k_r16(o) \
 336                 const uint8_t r = 16 + ((o >> 4) & 0xf); \
 337                 const uint8_t k = ((o & 0x0f00) >> 4) | (o & 0xf);
 338
 339 /*
 340  * Add a "jump" address to the jump trace buffer
 341  */
 342 #if CONFIG_SIMAVR_TRACE
 343 #define TRACE_JUMP()\
 344         avr->trace_data->old[avr->trace_data->old_pci].pc = avr->pc;\
 345         avr->trace_data->old[avr->trace_data->old_pci].sp = _avr_sp_get(avr);\
 346         avr->trace_data->old_pci = (avr->trace_data->old_pci + 1) & (OLD_PC_SIZE-1);\
 347
 348 #if AVR_STACK_WATCH
 349 #define STACK_FRAME_PUSH()\
 350         avr->trace_data->stack_frame[avr->trace_data->stack_frame_index].pc = avr->pc;\
 351         avr->trace_data->stack_frame[avr->trace_data->stack_frame_index].sp = _avr_sp_get(avr);\
 352         avr->trace_data->stack_frame_index++;
 353 #define STACK_FRAME_POP()\
 354         if (avr->trace_data->stack_frame_index > 0) \
 355                 avr->trace_data->stack_frame_index--;
 356 #else
 357 #define STACK_FRAME_PUSH()
 358 #define STACK_FRAME_POP()
 359 #endif
 360 #else /* CONFIG_SIMAVR_TRACE */
 361
 362 #define TRACE_JUMP()
 363 #define STACK_FRAME_PUSH()
 364 #define STACK_FRAME_POP()
 365
 366 #endif
 367
 368 /****************************************************************************\
 369  *
 370  * Helper functions for calculating the status register bit values.
 371  * See the Atmel data sheet for the instruction set for more info.
 372  *
 373 \****************************************************************************/
 374
 375 static uint8_t
 376 get_add_carry (uint8_t res, uint8_t rd, uint8_t rr, int b)
 377 {
 378     uint8_t resb = res >> b & 0x1;
 379     uint8_t rdb = rd >> b & 0x1;
 380     uint8_t rrb = rr >> b & 0x1;
 381     return (rdb & rrb) | (rrb & ~resb) | (~resb & rdb);
 382 }
 383
 384 static  uint8_t
 385 get_add_overflow (uint8_t res, uint8_t rd, uint8_t rr)
 386 {
 387     uint8_t res7 = res >> 7 & 0x1;
 388     uint8_t rd7 = rd >> 7 & 0x1;
 389     uint8_t rr7 = rr >> 7 & 0x1;
 390     return (rd7 & rr7 & ~res7) | (~rd7 & ~rr7 & res7);
 391 }
 392
 393 static  uint8_t
 394 get_sub_carry (uint8_t res, uint8_t rd, uint8_t rr, int b)
 395 {
 396     uint8_t resb = res >> b & 0x1;
 397     uint8_t rdb = rd >> b & 0x1;
 398     uint8_t rrb = rr >> b & 0x1;
 399     return (~rdb & rrb) | (rrb & resb) | (resb & ~rdb);
 400 }
 401
 402 static  uint8_t
 403 get_sub_overflow (uint8_t res, uint8_t rd, uint8_t rr)
 404 {
 405     uint8_t res7 = res >> 7 & 0x1;
 406     uint8_t rd7 = rd >> 7 & 0x1;
 407     uint8_t rr7 = rr >> 7 & 0x1;
 408     return (rd7 & ~rr7 & ~res7) | (~rd7 & rr7 & res7);
 409 }
 410
 411 static  uint8_t
 412 get_compare_carry (uint8_t res, uint8_t rd, uint8_t rr, int b)
 413 {
 414     uint8_t resb = (res >> b) & 0x1;
 415     uint8_t rdb = (rd >> b) & 0x1;
 416     uint8_t rrb = (rr >> b) & 0x1;
 417     return (~rdb & rrb) | (rrb & resb) | (resb & ~rdb);
 418 }
 419
 420 static  uint8_t
 421 get_compare_overflow (uint8_t res, uint8_t rd, uint8_t rr)
 422 {
 423     res >>= 7; rd >>= 7; rr >>= 7;
 424     /* The atmel data sheet says the second term is ~rd7 for CP
 425      * but that doesn't make any sense. You be the judge. */
 426     return (rd & ~rr & ~res) | (~rd & rr & res);
 427 }
 428
 429 static inline int _avr_is_instruction_32_bits(avr_t * avr, avr_flashaddr_t pc)
 430 {
 431         uint16_t o = (avr->flash[pc] | (avr->flash[pc+1] << 8)) & 0xfc0f;
 432         return  o == 0x9200 || // STS ! Store Direct to Data Space
 433                         o == 0x9000 || // LDS Load Direct from Data Space
 434                         o == 0x940c || // JMP Long Jump
 435                         o == 0x940d || // JMP Long Jump
 436                         o == 0x940e ||  // CALL Long Call to sub
 437                         o == 0x940f; // CALL Long Call to sub
 438 }
 439
 440 /*
 441  * Main opcode decoder
 442  *
 443  * The decoder was written by following the datasheet in no particular order.
 444  * As I went along, I noticed "bit patterns" that could be used to factor opcodes
 445  * However, a lot of these only became apparent later on, so SOME instructions
 446  * (skip of bit set etc) are compact, and some could use some refactoring (the ALU
 447  * ones scream to be factored).
 448  * I assume that the decoder could easily be 2/3 of it's current size.
 449  *
 450  * + It lacks the "extended" XMega jumps.
 451  * + It also doesn't check whether the core it's
 452  *   emulating is supposed to have the fancy instructions, like multiply and such.
 453  *
 454  * The number of cycles taken by instruction has been added, but might not be
 455  * entirely accurate.
 456  */
 457 avr_flashaddr_t avr_run_one(avr_t * avr)
 458 {
 459 #if CONFIG_SIMAVR_TRACE
 460         /*
 461          * this traces spurious reset or bad jumps
 462          */
 463         if ((avr->pc == 0 && avr->cycle > 0) || avr->pc >= avr->codeend) {
 464                 avr->trace = 1;
 465                 STATE("RESET\n");
 466                 CRASH();
 467         }
 468         avr->trace_data->touched[0] = avr->trace_data->touched[1] = avr->trace_data->touched[2] = 0;
 469 #endif
 470
 471         uint32_t                opcode = (avr->flash[avr->pc + 1] << 8) | avr->flash[avr->pc];
 472         avr_flashaddr_t new_pc = avr->pc + 2;   // future "default" pc
 473         int                     cycle = 1;
 474
 475         switch (opcode & 0xf000) {
 476                 case 0x0000: {
 477                         switch (opcode) {
 478                                 case 0x0000: {  // NOP
 479                                         STATE("nop\n");
 480                                 }       break;
 481                                 default: {
 482                                         switch (opcode & 0xfc00) {
 483                                                 case 0x0400: {  // CPC compare with carry 0000 01rd dddd rrrr
 484                                                         get_r_d_10(opcode);
 485                                                         uint8_t res = vd - vr - avr->sreg[S_C];
 486                                                         STATE("cpc %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res);
 487                                                         if (res)
 488                                                                 avr->sreg[S_Z] = 0;
 489                                                         avr->sreg[S_H] = get_compare_carry(res, vd, vr, 3);
 490                                                         avr->sreg[S_V] = get_compare_overflow(res, vd, vr);
 491                                                         avr->sreg[S_N] = (res >> 7) & 1;
 492                                                         avr->sreg[S_C] = get_compare_carry(res, vd, vr, 7);
 493                                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 494                                                         SREG();
 495                                                 }       break;
 496                                                 case 0x0c00: {  // ADD without carry 0000 11 rd dddd rrrr
 497                                                         get_r_d_10(opcode);
 498                                                         uint8_t res = vd + vr;
 499                                                         if (r == d) {
 500                                                                 STATE("lsl %s[%02x] = %02x\n", avr_regname(d), vd, res & 0xff);
 501                                                         } else {
 502                                                                 STATE("add %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res);
 503                                                         }
 504                                                         _avr_set_r(avr, d, res);
 505                                                         avr->sreg[S_Z] = res == 0;
 506                                                         avr->sreg[S_H] = get_add_carry(res, vd, vr, 3);
 507                                                         avr->sreg[S_V] = get_add_overflow(res, vd, vr);
 508                                                         avr->sreg[S_N] = (res >> 7) & 1;
 509                                                         avr->sreg[S_C] = get_add_carry(res, vd, vr, 7);
 510                                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 511                                                         SREG();
 512                                                 }       break;
 513                                                 case 0x0800: {  // SBC subtract with carry 0000 10rd dddd rrrr
 514                                                         get_r_d_10(opcode);
 515                                                         uint8_t res = vd - vr - avr->sreg[S_C];
 516                                                         STATE("sbc %s[%02x], %s[%02x] = %02x\n", avr_regname(d), avr->data[d], avr_regname(r), avr->data[r], res);
 517                                                         _avr_set_r(avr, d, res);
 518                                                         if (res)
 519                                                                 avr->sreg[S_Z] = 0;
 520                                                         avr->sreg[S_H] = get_sub_carry(res, vd, vr, 3);
 521                                                         avr->sreg[S_V] = get_sub_overflow(res, vd, vr);
 522                                                         avr->sreg[S_N] = (res >> 7) & 1;
 523                                                         avr->sreg[S_C] = get_sub_carry(res, vd, vr, 7);
 524                                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 525                                                         SREG();
 526                                                 }       break;
 527                                                 default:
 528                                                         switch (opcode & 0xff00) {
 529                                                                 case 0x0100: {  // MOVW – Copy Register Word 0000 0001 dddd rrrr
 530                                                                         uint8_t d = ((opcode >> 4) & 0xf) << 1;
 531                                                                         uint8_t r = ((opcode) & 0xf) << 1;
 532                                                                         STATE("movw %s:%s, %s:%s[%02x%02x]\n", avr_regname(d), avr_regname(d+1), avr_regname(r), avr_regname(r+1), avr->data[r+1], avr->data[r]);
 533                                                                         _avr_set_r(avr, d, avr->data[r]);
 534                                                                         _avr_set_r(avr, d+1, avr->data[r+1]);
 535                                                                 }       break;
 536                                                                 case 0x0200: {  // MULS – Multiply Signed 0000 0010 dddd rrrr
 537                                                                         int8_t r = 16 + (opcode & 0xf);
 538                                                                         int8_t d = 16 + ((opcode >> 4) & 0xf);
 539                                                                         int16_t res = ((int8_t)avr->data[r]) * ((int8_t)avr->data[d]);
 540                                                                         STATE("muls %s[%d], %s[%02x] = %d\n", avr_regname(d), ((int8_t)avr->data[d]), avr_regname(r), ((int8_t)avr->data[r]), res);
 541                                                                         _avr_set_r(avr, 0, res);
 542                                                                         _avr_set_r(avr, 1, res >> 8);
 543                                                                         avr->sreg[S_C] = (res >> 15) & 1;
 544                                                                         avr->sreg[S_Z] = res == 0;
 545                                                                         SREG();
 546                                                                 }       break;
 547                                                                 case 0x0300: {  // MUL Multiply 0000 0011 fddd frrr
 548                                                                         int8_t r = 16 + (opcode & 0x7);
 549                                                                         int8_t d = 16 + ((opcode >> 4) & 0x7);
 550                                                                         int16_t res = 0;
 551                                                                         uint8_t c = 0;
 552                                                                         T(const char * name = "";)
 553                                                                         switch (opcode & 0x88) {
 554                                                                                 case 0x00:      // MULSU – Multiply Signed Unsigned 0000 0011 0ddd 0rrr
 555                                                                                         res = ((uint8_t)avr->data[r]) * ((int8_t)avr->data[d]);
 556                                                                                         c = (res >> 15) & 1;
 557                                                                                         T(name = "mulsu";)
 558                                                                                         break;
 559                                                                                 case 0x08:      // FMUL Fractional Multiply Unsigned 0000 0011 0ddd 1rrr
 560                                                                                         res = ((uint8_t)avr->data[r]) * ((uint8_t)avr->data[d]);
 561                                                                                         c = (res >> 15) & 1;
 562                                                                                         res <<= 1;
 563                                                                                         T(name = "fmul";)
 564                                                                                         break;
 565                                                                                 case 0x80:      // FMULS – Multiply Signed  0000 0011 1ddd 0rrr
 566                                                                                         res = ((int8_t)avr->data[r]) * ((int8_t)avr->data[d]);
 567                                                                                         c = (res >> 15) & 1;
 568                                                                                         res <<= 1;
 569                                                                                         T(name = "fmuls";)
 570                                                                                         break;
 571                                                                                 case 0x88:      // FMULSU – Multiply Signed Unsigned 0000 0011 1ddd 1rrr
 572                                                                                         res = ((uint8_t)avr->data[r]) * ((int8_t)avr->data[d]);
 573                                                                                         c = (res >> 15) & 1;
 574                                                                                         res <<= 1;
 575                                                                                         T(name = "fmulsu";)
 576                                                                                         break;
 577                                                                         }
 578                                                                         cycle++;
 579                                                                         STATE("%s %s[%d], %s[%02x] = %d\n", name, avr_regname(d), ((int8_t)avr->data[d]), avr_regname(r), ((int8_t)avr->data[r]), res);
 580                                                                         _avr_set_r(avr, 0, res);
 581                                                                         _avr_set_r(avr, 1, res >> 8);
 582                                                                         avr->sreg[S_C] = c;
 583                                                                         avr->sreg[S_Z] = res == 0;
 584                                                                         SREG();
 585                                                                 }       break;
 586                                                                 default: _avr_invalid_opcode(avr);
 587                                                         }
 588                                         }
 589                                 }
 590                         }
 591                 }       break;
 592
 593                 case 0x1000: {
 594                         switch (opcode & 0xfc00) {
 595                                 case 0x1800: {  // SUB without carry 0000 10 rd dddd rrrr
 596                                         get_r_d_10(opcode);
 597                                         uint8_t res = vd - vr;
 598                                         STATE("sub %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res);
 599                                         _avr_set_r(avr, d, res);
 600                                         avr->sreg[S_Z] = res == 0;
 601                                         avr->sreg[S_H] = get_sub_carry(res, vd, vr, 3);
 602                                         avr->sreg[S_V] = get_sub_overflow(res, vd, vr);
 603                                         avr->sreg[S_N] = (res >> 7) & 1;
 604                                         avr->sreg[S_C] = get_sub_carry(res, vd, vr, 7);
 605                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 606                                         SREG();
 607                                 }       break;
 608                                 case 0x1000: {  // CPSE Compare, skip if equal 0000 00 rd dddd rrrr
 609                                         get_r_d_10(opcode);
 610                                         uint16_t res = vd == vr;
 611                                         STATE("cpse %s[%02x], %s[%02x]\t; Will%s skip\n", avr_regname(d), avr->data[d], avr_regname(r), avr->data[r], res ? "":" not");
 612                                         if (res) {
 613                                                 if (_avr_is_instruction_32_bits(avr, new_pc)) {
 614                                                         new_pc += 4; cycle += 2;
 615                                                 } else {
 616                                                         new_pc += 2; cycle++;
 617                                                 }
 618                                         }
 619                                 }       break;
 620                                 case 0x1400: {  // CP Compare 0000 01 rd dddd rrrr
 621                                         get_r_d_10(opcode);
 622                                         uint8_t res = vd - vr;
 623                                         STATE("cp %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res);
 624                                         avr->sreg[S_Z] = res == 0;
 625                                         avr->sreg[S_H] = get_compare_carry(res, vd, vr, 3);
 626                                         avr->sreg[S_V] = get_compare_overflow(res, vd, vr);
 627                                         avr->sreg[S_N] = res >> 7;
 628                                         avr->sreg[S_C] = get_compare_carry(res, vd, vr, 7);
 629                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 630                                         SREG();
 631                                 }       break;
 632                                 case 0x1c00: {  // ADD with carry 0001 11 rd dddd rrrr
 633                                         get_r_d_10(opcode);
 634                                         uint8_t res = vd + vr + avr->sreg[S_C];
 635                                         if (r == d) {
 636                                                 STATE("rol %s[%02x] = %02x\n", avr_regname(d), avr->data[d], res);
 637                                         } else {
 638                                                 STATE("addc %s[%02x], %s[%02x] = %02x\n", avr_regname(d), avr->data[d], avr_regname(r), avr->data[r], res);
 639                                         }
 640                                         _avr_set_r(avr, d, res);
 641                                         avr->sreg[S_Z] = res == 0;
 642                                         avr->sreg[S_H] = get_add_carry(res, vd, vr, 3);
 643                                         avr->sreg[S_V] = get_add_overflow(res, vd, vr);
 644                                         avr->sreg[S_N] = (res >> 7) & 1;
 645                                         avr->sreg[S_C] = get_add_carry(res, vd, vr, 7);
 646                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 647                                         SREG();
 648                                 }       break;
 649                                 default: _avr_invalid_opcode(avr);
 650                         }
 651                 }       break;
 652
 653                 case 0x2000: {
 654                         switch (opcode & 0xfc00) {
 655                                 case 0x2000: {  // AND  0010 00rd dddd rrrr
 656                                         get_r_d_10(opcode);
 657                                         uint8_t res = vd & vr;
 658                                         if (r == d) {
 659                                                 STATE("tst %s[%02x]\n", avr_regname(d), avr->data[d]);
 660                                         } else {
 661                                                 STATE("and %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res);
 662                                         }
 663                                         _avr_set_r(avr, d, res);
 664                                         avr->sreg[S_Z] = res == 0;
 665                                         avr->sreg[S_N] = (res >> 7) & 1;
 666                                         avr->sreg[S_V] = 0;
 667                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 668                                         SREG();
 669                                 }       break;
 670                                 case 0x2400: {  // EOR  0010 01rd dddd rrrr
 671                                         get_r_d_10(opcode);
 672                                         uint8_t res = vd ^ vr;
 673                                         if (r==d) {
 674                                                 STATE("clr %s[%02x]\n", avr_regname(d), avr->data[d]);
 675                                         } else {
 676                                                 STATE("eor %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res);
 677                                         }
 678                                         _avr_set_r(avr, d, res);
 679                                         avr->sreg[S_Z] = res == 0;
 680                                         avr->sreg[S_N] = (res >> 7) & 1;
 681                                         avr->sreg[S_V] = 0;
 682                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 683                                         SREG();
 684                                 }       break;
 685                                 case 0x2800: {  // OR Logical OR        0010 10rd dddd rrrr
 686                                         get_r_d_10(opcode);
 687                                         uint8_t res = vd | vr;
 688                                         STATE("or %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res);
 689                                         _avr_set_r(avr, d, res);
 690                                         avr->sreg[S_Z] = res == 0;
 691                                         avr->sreg[S_N] = (res >> 7) & 1;
 692                                         avr->sreg[S_V] = 0;
 693                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 694                                         SREG();
 695                                 }       break;
 696                                 case 0x2c00: {  // MOV  0010 11rd dddd rrrr
 697                                         get_r_dd_10(opcode);
 698                                         uint8_t res = vr;
 699                                         STATE("mov %s, %s[%02x] = %02x\n", avr_regname(d), avr_regname(r), vr, res);
 700                                         _avr_set_r(avr, d, res);
 701                                 }       break;
 702                                 default: _avr_invalid_opcode(avr);
 703                         }
 704                 }       break;
 705
 706                 case 0x3000: {  // CPI 0011 KKKK rrrr KKKK
 707                         get_k_r16(opcode);
 708                         uint8_t vr = avr->data[r];
 709                         uint8_t res = vr - k;
 710                         STATE("cpi %s[%02x], 0x%02x\n", avr_regname(r), vr, k);
 711
 712                         avr->sreg[S_Z] = res == 0;
 713                         avr->sreg[S_H] = get_compare_carry(res, vr, k, 3);
 714                         avr->sreg[S_V] = get_compare_overflow(res, vr, k);
 715                         avr->sreg[S_N] = (res >> 7) & 1;
 716                         avr->sreg[S_C] = get_compare_carry(res, vr, k, 7);
 717                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 718                         SREG();
 719                 }       break;
 720
 721                 case 0x4000: {  // SBCI Subtract Immediate With Carry 0101 10 kkkk dddd kkkk
 722                         get_k_r16(opcode);
 723                         uint8_t vr = avr->data[r];
 724                         uint8_t res = vr - k - avr->sreg[S_C];
 725                         STATE("sbci %s[%02x], 0x%02x = %02x\n", avr_regname(r), avr->data[r], k, res);
 726                         _avr_set_r(avr, r, res);
 727                         if (res)
 728                                 avr->sreg[S_Z] = 0;
 729                         avr->sreg[S_N] = (res >> 7) & 1;
 730                         avr->sreg[S_C] = (k + avr->sreg[S_C]) > vr;
 731                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 732                         SREG();
 733                 }       break;
 734
 735                 case 0x5000: {  // SUB Subtract Immediate 0101 10 kkkk dddd kkkk
 736                         get_k_r16(opcode);
 737                         uint8_t vr = avr->data[r];
 738                         uint8_t res = vr - k;
 739                         STATE("subi %s[%02x], 0x%02x = %02x\n", avr_regname(r), avr->data[r], k, res);
 740                         _avr_set_r(avr, r, res);
 741                         avr->sreg[S_Z] = res  == 0;
 742                         avr->sreg[S_N] = (res >> 7) & 1;
 743                         avr->sreg[S_C] = k > vr;
 744                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 745                         SREG();
 746                 }       break;
 747
 748                 case 0x6000: {  // ORI aka SBR  Logical AND with Immediate      0110 kkkk dddd kkkk
 749                         get_k_r16(opcode);
 750                         uint8_t res = avr->data[r] | k;
 751                         STATE("ori %s[%02x], 0x%02x\n", avr_regname(r), avr->data[r], k);
 752                         _avr_set_r(avr, r, res);
 753                         avr->sreg[S_Z] = res == 0;
 754                         avr->sreg[S_N] = (res >> 7) & 1;
 755                         avr->sreg[S_V] = 0;
 756                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 757                         SREG();
 758                 }       break;
 759
 760                 case 0x7000: {  // ANDI Logical AND with Immediate      0111 kkkk dddd kkkk
 761                         get_k_r16(opcode);
 762                         uint8_t res = avr->data[r] & k;
 763                         STATE("andi %s[%02x], 0x%02x\n", avr_regname(r), avr->data[r], k);
 764                         _avr_set_r(avr, r, res);
 765                         avr->sreg[S_Z] = res == 0;
 766                         avr->sreg[S_N] = (res >> 7) & 1;
 767                         avr->sreg[S_V] = 0;
 768                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 769                         SREG();
 770                 }       break;
 771
 772                 case 0xa000:
 773                 case 0x8000: {
 774                         switch (opcode & 0xd008) {
 775                                 case 0xa000:
 776                                 case 0x8000: {  // LD (LDD) – Load Indirect using Z 10q0 qq0r rrrr 0qqq
 777                                         uint16_t v = avr->data[R_ZL] | (avr->data[R_ZH] << 8);
 778                                         uint8_t r = (opcode >> 4) & 0x1f;
 779                                         uint8_t q = ((opcode & 0x2000) >> 8) | ((opcode & 0x0c00) >> 7) | (opcode & 0x7);
 780
 781                                         if (opcode & 0x0200) {
 782                                                 STATE("st (Z+%d[%04x]), %s[%02x]\n", q, v+q, avr_regname(r), avr->data[r]);
 783                                                 _avr_set_ram(avr, v+q, avr->data[r]);
 784                                         } else {
 785                                                 STATE("ld %s, (Z+%d[%04x])=[%02x]\n", avr_regname(r), q, v+q, avr->data[v+q]);
 786                                                 _avr_set_r(avr, r, _avr_get_ram(avr, v+q));
 787                                         }
 788                                         cycle += 1; // 2 cycles, 3 for tinyavr
 789                                 }       break;
 790                                 case 0xa008:
 791                                 case 0x8008: {  // LD (LDD) – Load Indirect using Y 10q0 qq0r rrrr 1qqq
 792                                         uint16_t v = avr->data[R_YL] | (avr->data[R_YH] << 8);
 793                                         uint8_t r = (opcode >> 4) & 0x1f;
 794                                         uint8_t q = ((opcode & 0x2000) >> 8) | ((opcode & 0x0c00) >> 7) | (opcode & 0x7);
 795
 796                                         if (opcode & 0x0200) {
 797                                                 STATE("st (Y+%d[%04x]), %s[%02x]\n", q, v+q, avr_regname(r), avr->data[r]);
 798                                                 _avr_set_ram(avr, v+q, avr->data[r]);
 799                                         } else {
 800                                                 STATE("ld %s, (Y+%d[%04x])=[%02x]\n", avr_regname(r), q, v+q, avr->data[v+q]);
 801                                                 _avr_set_r(avr, r, _avr_get_ram(avr, v+q));
 802                                         }
 803                                         cycle += 1; // 2 cycles, 3 for tinyavr
 804                                 }       break;
 805                                 default: _avr_invalid_opcode(avr);
 806                         }
 807                 }       break;
 808
 809                 case 0x9000: {
 810                         /* this is an annoying special case, but at least these lines handle all the SREG set/clear opcodes */
 811                         if ((opcode & 0xff0f) == 0x9408) {
 812                                 uint8_t b = (opcode >> 4) & 7;
 813                                 STATE("%s%c\n", opcode & 0x0080 ? "cl" : "se", _sreg_bit_name[b]);
 814                                 avr->sreg[b] = (opcode & 0x0080) == 0;
 815                                 SREG();
 816                         } else switch (opcode) {
 817                                 case 0x9588: { // SLEEP
 818                                         STATE("sleep\n");
 819                                         avr->state = cpu_Sleeping;
 820                                 }       break;
 821                                 case 0x9598: { // BREAK
 822                                         STATE("break\n");
 823                                         if (avr->gdb) {
 824                                                 // if gdb is on, we break here as in here
 825                                                 // and we do so until gdb restores the instruction
 826                                                 // that was here before
 827                                                 avr->state = cpu_StepDone;
 828                                                 new_pc = avr->pc;
 829                                                 cycle = 0;
 830                                         }
 831                                 }       break;
 832                                 case 0x95a8: { // WDR
 833                                         STATE("wdr\n");
 834                                         avr_ioctl(avr, AVR_IOCTL_WATCHDOG_RESET, 0);
 835                                 }       break;
 836                                 case 0x95e8: { // SPM
 837                                         STATE("spm\n");
 838                                         avr_ioctl(avr, AVR_IOCTL_FLASH_SPM, 0);
 839                                 }       break;
 840                                 case 0x9409:   // IJMP Indirect jump                                    1001 0100 0000 1001
 841                                 case 0x9419:   // EIJMP Indirect jump                                   1001 0100 0001 1001   bit 4 is "indirect"
 842                                 case 0x9509:   // ICALL Indirect Call to Subroutine             1001 0101 0000 1001
 843                                 case 0x9519: { // EICALL Indirect Call to Subroutine    1001 0101 0001 1001   bit 8 is "push pc"
 844                                         int e = opcode & 0x10;
 845                                         int p = opcode & 0x100;
 846                                         if (e && !avr->eind)
 847                                                 _avr_invalid_opcode(avr);
 848                                         uint16_t z = avr->data[R_ZL] | (avr->data[R_ZH] << 8);
 849                                         if (e)
 850                                                 z |= avr->data[avr->eind] << 16;
 851                                         STATE("%si%s Z[%04x]\n", e?"e":"", p?"call":"jmp", z << 1);
 852                                         if (p) {
 853                                                 cycle++;
 854                                                 _avr_push16(avr, new_pc >> 1);
 855                                         }
 856                                         new_pc = z << 1;
 857                                         cycle++;
 858                                         TRACE_JUMP();
 859                                 }       break;
 860                                 case 0x9518:    // RETI
 861                                 case 0x9508: {  // RET
 862                                         new_pc = _avr_pop16(avr) << 1;
 863                                         if (opcode & 0x10)      // reti
 864                                                 avr->sreg[S_I] = 1;
 865                                         cycle += 3;
 866                                         STATE("ret%s\n", opcode & 0x10 ? "i" : "");
 867                                         TRACE_JUMP();
 868                                         STACK_FRAME_POP();
 869                                 }       break;
 870                                 case 0x95c8: {  // LPM Load Program Memory R0 <- (Z)
 871                                         uint16_t z = avr->data[R_ZL] | (avr->data[R_ZH] << 8);
 872                                         STATE("lpm %s, (Z[%04x])\n", avr_regname(0), z);
 873                                         cycle += 2; // 3 cycles
 874                                         _avr_set_r(avr, 0, avr->flash[z]);
 875                                 }       break;
 876                                 case 0x9408:case 0x9418:case 0x9428:case 0x9438:case 0x9448:case 0x9458:case 0x9468:
 877                                 case 0x9478:
 878                                 {       // BSET 1001 0100 0ddd 1000
 879                                         uint8_t b = (opcode >> 4) & 7;
 880                                         avr->sreg[b] = 1;
 881                                         STATE("bset %c\n", _sreg_bit_name[b]);
 882                                         SREG();
 883                                 }       break;
 884                                 case 0x9488:case 0x9498:case 0x94a8:case 0x94b8:case 0x94c8:case 0x94d8:case 0x94e8:
 885                                 case 0x94f8:    // bit 7 is 'clear vs set'
 886                                 {       // BCLR 1001 0100 1ddd 1000
 887                                         uint8_t b = (opcode >> 4) & 7;
 888                                         avr->sreg[b] = 0;
 889                                         STATE("bclr %c\n", _sreg_bit_name[b]);
 890                                         SREG();
 891                                 }       break;
 892                                 default:  {
 893                                         switch (opcode & 0xfe0f) {
 894                                                 case 0x9000: {  // LDS Load Direct from Data Space, 32 bits
 895                                                         uint8_t r = (opcode >> 4) & 0x1f;
 896                                                         uint16_t x = (avr->flash[new_pc+1] << 8) | avr->flash[new_pc];
 897                                                         new_pc += 2;
 898                                                         STATE("lds %s[%02x], 0x%04x\n", avr_regname(r), avr->data[r], x);
 899                                                         _avr_set_r(avr, r, _avr_get_ram(avr, x));
 900                                                         cycle++; // 2 cycles
 901                                                 }       break;
 902                                                 case 0x9005:
 903                                                 case 0x9004: {  // LPM Load Program Memory 1001 000d dddd 01oo
 904                                                         uint16_t z = avr->data[R_ZL] | (avr->data[R_ZH] << 8);
 905                                                         uint8_t r = (opcode >> 4) & 0x1f;
 906                                                         int op = opcode & 3;
 907                                                         STATE("lpm %s, (Z[%04x]%s)\n", avr_regname(r), z, opcode?"+":"");
 908                                                         _avr_set_r(avr, r, avr->flash[z]);
 909                                                         if (op == 1) {
 910                                                                 z++;
 911                                                                 _avr_set_r(avr, R_ZH, z >> 8);
 912                                                                 _avr_set_r(avr, R_ZL, z);
 913                                                         }
 914                                                         cycle += 2; // 3 cycles
 915                                                 }       break;
 916                                                 case 0x9006:
 917                                                 case 0x9007: {  // ELPM Extended Load Program Memory 1001 000d dddd 01oo
 918                                                         if (!avr->rampz)
 919                                                                 _avr_invalid_opcode(avr);
 920                                                         uint16_t z = avr->data[R_ZL] | (avr->data[R_ZH] << 8) | (avr->data[avr->rampz] << 16);
 921                                                         uint8_t r = (opcode >> 4) & 0x1f;
 922                                                         int op = opcode & 3;
 923                                                         STATE("elpm %s, (Z[%02x:%04x]%s)\n", avr_regname(r), z >> 16, z&0xffff, opcode?"+":"");
 924                                                         _avr_set_r(avr, r, avr->flash[z]);
 925                                                         if (op == 3) {
 926                                                                 z++;
 927                                                                 _avr_set_r(avr, avr->rampz, z >> 16);
 928                                                                 _avr_set_r(avr, R_ZH, z >> 8);
 929                                                                 _avr_set_r(avr, R_ZL, z);
 930                                                         }
 931                                                         cycle += 2; // 3 cycles
 932                                                 }       break;
 933                                                 /*
 934                                                  * Load store instructions
 935                                                  *
 936                                                  * 1001 00sr rrrr iioo
 937                                                  * s = 0 = load, 1 = store
 938                                                  * ii = 16 bits register index, 11 = Z, 10 = Y, 00 = X
 939                                                  * oo = 1) post increment, 2) pre-decrement
 940                                                  */
 941                                                 case 0x900c:
 942                                                 case 0x900d:
 943                                                 case 0x900e: {  // LD Load Indirect from Data using X 1001 000r rrrr 11oo
 944                                                         int op = opcode & 3;
 945                                                         uint8_t r = (opcode >> 4) & 0x1f;
 946                                                         uint16_t x = (avr->data[R_XH] << 8) | avr->data[R_XL];
 947                                                         STATE("ld %s, %sX[%04x]%s\n", avr_regname(r), op == 2 ? "--" : "", x, op == 1 ? "++" : "");
 948                                                         cycle++; // 2 cycles (1 for tinyavr, except with inc/dec 2)
 949                                                         if (op == 2) x--;
 950                                                         _avr_set_r(avr, r, _avr_get_ram(avr, x));
 951                                                         if (op == 1) x++;
 952                                                         _avr_set_r(avr, R_XH, x >> 8);
 953                                                         _avr_set_r(avr, R_XL, x);
 954                                                 }       break;
 955                                                 case 0x920c:
 956                                                 case 0x920d:
 957                                                 case 0x920e: {  // ST Store Indirect Data Space X 1001 001r rrrr 11oo
 958                                                         int op = opcode & 3;
 959                                                         uint8_t r = (opcode >> 4) & 0x1f;
 960                                                         uint16_t x = (avr->data[R_XH] << 8) | avr->data[R_XL];
 961                                                         STATE("st %sX[%04x]%s, %s[%02x] \n", op == 2 ? "--" : "", x, op == 1 ? "++" : "", avr_regname(r), avr->data[r]);
 962                                                         cycle++; // 2 cycles, except tinyavr
 963                                                         if (op == 2) x--;
 964                                                         _avr_set_ram(avr, x, avr->data[r]);
 965                                                         if (op == 1) x++;
 966                                                         _avr_set_r(avr, R_XH, x >> 8);
 967                                                         _avr_set_r(avr, R_XL, x);
 968                                                 }       break;
 969                                                 case 0x9009:
 970                                                 case 0x900a: {  // LD Load Indirect from Data using Y 1001 000r rrrr 10oo
 971                                                         int op = opcode & 3;
 972                                                         uint8_t r = (opcode >> 4) & 0x1f;
 973                                                         uint16_t y = (avr->data[R_YH] << 8) | avr->data[R_YL];
 974                                                         STATE("ld %s, %sY[%04x]%s\n", avr_regname(r), op == 2 ? "--" : "", y, op == 1 ? "++" : "");
 975                                                         cycle++; // 2 cycles, except tinyavr
 976                                                         if (op == 2) y--;
 977                                                         _avr_set_r(avr, r, _avr_get_ram(avr, y));
 978                                                         if (op == 1) y++;
 979                                                         _avr_set_r(avr, R_YH, y >> 8);
 980                                                         _avr_set_r(avr, R_YL, y);
 981                                                 }       break;
 982                                                 case 0x9209:
 983                                                 case 0x920a: {  // ST Store Indirect Data Space Y 1001 001r rrrr 10oo
 984                                                         int op = opcode & 3;
 985                                                         uint8_t r = (opcode >> 4) & 0x1f;
 986                                                         uint16_t y = (avr->data[R_YH] << 8) | avr->data[R_YL];
 987                                                         STATE("st %sY[%04x]%s, %s[%02x]\n", op == 2 ? "--" : "", y, op == 1 ? "++" : "", avr_regname(r), avr->data[r]);
 988                                                         cycle++;
 989                                                         if (op == 2) y--;
 990                                                         _avr_set_ram(avr, y, avr->data[r]);
 991                                                         if (op == 1) y++;
 992                                                         _avr_set_r(avr, R_YH, y >> 8);
 993                                                         _avr_set_r(avr, R_YL, y);
 994                                                 }       break;
 995                                                 case 0x9200: {  // STS ! Store Direct to Data Space, 32 bits
 996                                                         uint8_t r = (opcode >> 4) & 0x1f;
 997                                                         uint16_t x = (avr->flash[new_pc+1] << 8) | avr->flash[new_pc];
 998                                                         new_pc += 2;
 999                                                         STATE("sts 0x%04x, %s[%02x]\n", x, avr_regname(r), avr->data[r]);
1000                                                         cycle++;
1001                                                         _avr_set_ram(avr, x, avr->data[r]);
1002                                                 }       break;
1003                                                 case 0x9001:
1004                                                 case 0x9002: {  // LD Load Indirect from Data using Z 1001 001r rrrr 00oo
1005                                                         int op = opcode & 3;
1006                                                         uint8_t r = (opcode >> 4) & 0x1f;
1007                                                         uint16_t z = (avr->data[R_ZH] << 8) | avr->data[R_ZL];
1008                                                         STATE("ld %s, %sZ[%04x]%s\n", avr_regname(r), op == 2 ? "--" : "", z, op == 1 ? "++" : "");
1009                                                         cycle++;; // 2 cycles, except tinyavr
1010                                                         if (op == 2) z--;
1011                                                         _avr_set_r(avr, r, _avr_get_ram(avr, z));
1012                                                         if (op == 1) z++;
1013                                                         _avr_set_r(avr, R_ZH, z >> 8);
1014                                                         _avr_set_r(avr, R_ZL, z);
1015                                                 }       break;
1016                                                 case 0x9201:
1017                                                 case 0x9202: {  // ST Store Indirect Data Space Z 1001 001r rrrr 00oo
1018                                                         int op = opcode & 3;
1019                                                         uint8_t r = (opcode >> 4) & 0x1f;
1020                                                         uint16_t z = (avr->data[R_ZH] << 8) | avr->data[R_ZL];
1021                                                         STATE("st %sZ[%04x]%s, %s[%02x] \n", op == 2 ? "--" : "", z, op == 1 ? "++" : "", avr_regname(r), avr->data[r]);
1022                                                         cycle++; // 2 cycles, except tinyavr
1023                                                         if (op == 2) z--;
1024                                                         _avr_set_ram(avr, z, avr->data[r]);
1025                                                         if (op == 1) z++;
1026                                                         _avr_set_r(avr, R_ZH, z >> 8);
1027                                                         _avr_set_r(avr, R_ZL, z);
1028                                                 }       break;
1029                                                 case 0x900f: {  // POP 1001 000d dddd 1111
1030                                                         uint8_t r = (opcode >> 4) & 0x1f;
1031                                                         _avr_set_r(avr, r, _avr_pop8(avr));
1032                                                         T(uint16_t sp = _avr_sp_get(avr);)
1033                                                         STATE("pop %s (@%04x)[%02x]\n", avr_regname(r), sp, avr->data[sp]);
1034                                                         cycle++;
1035                                                 }       break;
1036                                                 case 0x920f: {  // PUSH 1001 001d dddd 1111
1037                                                         uint8_t r = (opcode >> 4) & 0x1f;
1038                                                         _avr_push8(avr, avr->data[r]);
1039                                                         T(uint16_t sp = _avr_sp_get(avr);)
1040                                                         STATE("push %s[%02x] (@%04x)\n", avr_regname(r), avr->data[r], sp);
1041                                                         cycle++;
1042                                                 }       break;
1043                                                 case 0x9400: {  // COM – One’s Complement
1044                                                         uint8_t r = (opcode >> 4) & 0x1f;
1045                                                         uint8_t res = 0xff - avr->data[r];
1046                                                         STATE("com %s[%02x] = %02x\n", avr_regname(r), avr->data[r], res);
1047                                                         _avr_set_r(avr, r, res);
1048                                                         avr->sreg[S_Z] = res == 0;
1049                                                         avr->sreg[S_N] = res >> 7;
1050                                                         avr->sreg[S_V] = 0;
1051                                                         avr->sreg[S_C] = 1;
1052                                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
1053                                                         SREG();
1054                                                 }       break;
1055                                                 case 0x9401: {  // NEG – Two’s Complement
1056                                                         uint8_t r = (opcode >> 4) & 0x1f;
1057                                                         uint8_t rd = avr->data[r];
1058                                                         uint8_t res = 0x00 - rd;
1059                                                         STATE("neg %s[%02x] = %02x\n", avr_regname(r), rd, res);
1060                                                         _avr_set_r(avr, r, res);
1061                                                         avr->sreg[S_H] = ((res >> 3) | (rd >> 3)) & 1;
1062                                                         avr->sreg[S_Z] = res == 0;
1063                                                         avr->sreg[S_N] = res >> 7;
1064                                                         avr->sreg[S_V] = res == 0x80;
1065                                                         avr->sreg[S_C] = res != 0;
1066                                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
1067                                                         SREG();
1068                                                 }       break;
1069                                                 case 0x9402: {  // SWAP – Swap Nibbles
1070                                                         uint8_t r = (opcode >> 4) & 0x1f;
1071                                                         uint8_t res = (avr->data[r] >> 4) | (avr->data[r] << 4) ;
1072                                                         STATE("swap %s[%02x] = %02x\n", avr_regname(r), avr->data[r], res);
1073                                                         _avr_set_r(avr, r, res);
1074                                                 }       break;
1075                                                 case 0x9403: {  // INC – Increment
1076                                                         uint8_t r = (opcode >> 4) & 0x1f;
1077                                                         uint8_t res = avr->data[r] + 1;
1078                                                         STATE("inc %s[%02x] = %02x\n", avr_regname(r), avr->data[r], res);
1079                                                         _avr_set_r(avr, r, res);
1080                                                         avr->sreg[S_Z] = res == 0;
1081                                                         avr->sreg[S_N] = res >> 7;
1082                                                         avr->sreg[S_V] = res == 0x7f;
1083                                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
1084                                                         SREG();
1085                                                 }       break;
1086                                                 case 0x9405: {  // ASR – Arithmetic Shift Right 1001 010d dddd 0101
1087                                                         uint8_t r = (opcode >> 4) & 0x1f;
1088                                                         uint8_t vr = avr->data[r];
1089                                                         uint8_t res = (vr >> 1) | (vr & 0x80);
1090                                                         STATE("asr %s[%02x]\n", avr_regname(r), vr);
1091                                                         _avr_set_r(avr, r, res);
1092                                                         avr->sreg[S_Z] = res == 0;
1093                                                         avr->sreg[S_C] = vr & 1;
1094                                                         avr->sreg[S_N] = res >> 7;
1095                                                         avr->sreg[S_V] = avr->sreg[S_N] ^ avr->sreg[S_C];
1096                                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
1097                                                         SREG();
1098                                                 }       break;
1099                                                 case 0x9406: {  // LSR 1001 010d dddd 0110
1100                                                         uint8_t r = (opcode >> 4) & 0x1f;
1101                                                         uint8_t vr = avr->data[r];
1102                                                         uint8_t res = vr >> 1;
1103                                                         STATE("lsr %s[%02x]\n", avr_regname(r), vr);
1104                                                         _avr_set_r(avr, r, res);
1105                                                         avr->sreg[S_Z] = res == 0;
1106                                                         avr->sreg[S_C] = vr & 1;
1107                                                         avr->sreg[S_N] = 0;
1108                                                         avr->sreg[S_V] = avr->sreg[S_N] ^ avr->sreg[S_C];
1109                                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
1110                                                         SREG();
1111                                                 }       break;
1112                                                 case 0x9407: {  // ROR 1001 010d dddd 0111
1113                                                         uint8_t r = (opcode >> 4) & 0x1f;
1114                                                         uint8_t vr = avr->data[r];
1115                                                         uint8_t res = (avr->sreg[S_C] ? 0x80 : 0) | vr >> 1;
1116                                                         STATE("ror %s[%02x]\n", avr_regname(r), vr);
1117                                                         _avr_set_r(avr, r, res);
1118                                                         avr->sreg[S_Z] = res == 0;
1119                                                         avr->sreg[S_C] = vr & 1;
1120                                                         avr->sreg[S_N] = 0;
1121                                                         avr->sreg[S_V] = avr->sreg[S_N] ^ avr->sreg[S_C];
1122                                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
1123                                                         SREG();
1124                                                 }       break;
1125                                                 case 0x940a: {  // DEC – Decrement
1126                                                         uint8_t r = (opcode >> 4) & 0x1f;
1127                                                         uint8_t res = avr->data[r] - 1;
1128                                                         STATE("dec %s[%02x] = %02x\n", avr_regname(r), avr->data[r], res);
1129                                                         _avr_set_r(avr, r, res);
1130                                                         avr->sreg[S_Z] = res == 0;
1131                                                         avr->sreg[S_N] = res >> 7;
1132                                                         avr->sreg[S_V] = res == 0x80;
1133                                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
1134                                                         SREG();
1135                                                 }       break;
1136                                                 case 0x940c:
1137                                                 case 0x940d: {  // JMP Long Call to sub, 32 bits
1138                                                         avr_flashaddr_t a = ((opcode & 0x01f0) >> 3) | (opcode & 1);
1139                                                         uint16_t x = (avr->flash[new_pc+1] << 8) | avr->flash[new_pc];
1140                                                         a = (a << 16) | x;
1141                                                         STATE("jmp 0x%06x\n", a);
1142                                                         new_pc = a << 1;
1143                                                         cycle += 2;
1144                                                         TRACE_JUMP();
1145                                                 }       break;
1146                                                 case 0x940e:
1147                                                 case 0x940f: {  // CALL Long Call to sub, 32 bits
1148                                                         avr_flashaddr_t a = ((opcode & 0x01f0) >> 3) | (opcode & 1);
1149                                                         uint16_t x = (avr->flash[new_pc+1] << 8) | avr->flash[new_pc];
1150                                                         a = (a << 16) | x;
1151                                                         STATE("call 0x%06x\n", a);
1152                                                         new_pc += 2;
1153                                                         _avr_push16(avr, new_pc >> 1);
1154                                                         new_pc = a << 1;
1155                                                         cycle += 3;     // 4 cycles; FIXME 5 on devices with 22 bit PC
1156                                                         TRACE_JUMP();
1157                                                         STACK_FRAME_PUSH();
1158                                                 }       break;
1159
1160                                                 default: {
1161                                                         switch (opcode & 0xff00) {
1162                                                                 case 0x9600: {  // ADIW - Add Immediate to Word 1001 0110 KKdd KKKK
1163                                                                         uint8_t r = 24 + ((opcode >> 3) & 0x6);
1164                                                                         uint8_t k = ((opcode & 0x00c0) >> 2) | (opcode & 0xf);
1165                                                                         uint8_t rdl = avr->data[r], rdh = avr->data[r+1];
1166                                                                         uint32_t res = rdl | (rdh << 8);
1167                                                                         STATE("adiw %s:%s[%04x], 0x%02x\n", avr_regname(r), avr_regname(r+1), res, k);
1168                                                                         res += k;
1169                                                                         _avr_set_r(avr, r + 1, res >> 8);
1170                                                                         _avr_set_r(avr, r, res);
1171                                                                         avr->sreg[S_V] = ~(rdh >> 7) & ((res >> 15) & 1);
1172                                                                         avr->sreg[S_Z] = (res & 0xffff) == 0;
1173                                                                         avr->sreg[S_N] = (res >> 15) & 1;
1174                                                                         avr->sreg[S_C] = ~((res >> 15) & 1) & (rdh >> 7);
1175                                                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
1176                                                                         SREG();
1177                                                                         cycle++;
1178                                                                 }       break;
1179                                                                 case 0x9700: {  // SBIW - Subtract Immediate from Word 1001 0110 KKdd KKKK
1180                                                                         uint8_t r = 24 + ((opcode >> 3) & 0x6);
1181                                                                         uint8_t k = ((opcode & 0x00c0) >> 2) | (opcode & 0xf);
1182                                                                         uint8_t rdl = avr->data[r], rdh = avr->data[r+1];
1183                                                                         uint32_t res = rdl | (rdh << 8);
1184                                                                         STATE("sbiw %s:%s[%04x], 0x%02x\n", avr_regname(r), avr_regname(r+1), res, k);
1185                                                                         res -= k;
1186                                                                         _avr_set_r(avr, r + 1, res >> 8);
1187                                                                         _avr_set_r(avr, r, res);
1188                                                                         avr->sreg[S_V] = (rdh >> 7) & (~(res >> 15) & 1);
1189                                                                         avr->sreg[S_Z] = (res & 0xffff) == 0;
1190                                                                         avr->sreg[S_N] = (res >> 15) & 1;
1191                                                                         avr->sreg[S_C] = ((res >> 15) & 1) & (~rdh >> 7);
1192                                                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
1193                                                                         SREG();
1194                                                                         cycle++;
1195                                                                 }       break;
1196                                                                 case 0x9800: {  // CBI - Clear Bit in I/O Register 1001 1000 AAAA Abbb
1197                                                                         uint8_t io = ((opcode >> 3) & 0x1f) + 32;
1198                                                                         uint8_t b = opcode & 0x7;
1199                                                                         uint8_t res = _avr_get_ram(avr, io) & ~(1 << b);
1200                                                                         STATE("cbi %s[%04x], 0x%02x = %02x\n", avr_regname(io), avr->data[io], 1<<b, res);
1201                                                                         _avr_set_ram(avr, io, res);
1202                                                                         cycle++;
1203                                                                 }       break;
1204                                                                 case 0x9900: {  // SBIC - Skip if Bit in I/O Register is Cleared 1001 0111 AAAA Abbb
1205                                                                         uint8_t io = ((opcode >> 3) & 0x1f) + 32;
1206                                                                         uint8_t b = opcode & 0x7;
1207                                                                         uint8_t res = _avr_get_ram(avr, io) & (1 << b);
1208                                                                         STATE("sbic %s[%04x], 0x%02x\t; Will%s branch\n", avr_regname(io), avr->data[io], 1<<b, !res?"":" not");
1209                                                                         if (!res) {
1210                                                                                 if (_avr_is_instruction_32_bits(avr, new_pc)) {
1211                                                                                         new_pc += 4; cycle += 2;
1212                                                                                 } else {
1213                                                                                         new_pc += 2; cycle++;
1214                                                                                 }
1215                                                                         }
1216                                                                 }       break;
1217                                                                 case 0x9a00: {  // SBI - Set Bit in I/O Register 1001 1000 AAAA Abbb
1218                                                                         uint8_t io = ((opcode >> 3) & 0x1f) + 32;
1219                                                                         uint8_t b = opcode & 0x7;
1220                                                                         uint8_t res = _avr_get_ram(avr, io) | (1 << b);
1221                                                                         STATE("sbi %s[%04x], 0x%02x = %02x\n", avr_regname(io), avr->data[io], 1<<b, res);
1222                                                                         _avr_set_ram(avr, io, res);
1223                                                                         cycle++;
1224                                                                 }       break;
1225                                                                 case 0x9b00: {  // SBIS - Skip if Bit in I/O Register is Set 1001 1011 AAAA Abbb
1226                                                                         uint8_t io = ((opcode >> 3) & 0x1f) + 32;
1227                                                                         uint8_t b = opcode & 0x7;
1228                                                                         uint8_t res = _avr_get_ram(avr, io) & (1 << b);
1229                                                                         STATE("sbis %s[%04x], 0x%02x\t; Will%s branch\n", avr_regname(io), avr->data[io], 1<<b, res?"":" not");
1230                                                                         if (res) {
1231                                                                                 if (_avr_is_instruction_32_bits(avr, new_pc)) {
1232                                                                                         new_pc += 4; cycle += 2;
1233                                                                                 } else {
1234                                                                                         new_pc += 2; cycle++;
1235                                                                                 }
1236                                                                         }
1237                                                                 }       break;
1238                                                                 default:
1239                                                                         switch (opcode & 0xfc00) {
1240                                                                                 case 0x9c00: {  // MUL - Multiply Unsigned 1001 11rd dddd rrrr
1241                                                                                         get_r_d_10(opcode);
1242                                                                                         uint16_t res = vd * vr;
1243                                                                                         STATE("mul %s[%02x], %s[%02x] = %04x\n", avr_regname(d), vd, avr_regname(r), vr, res);
1244                                                                                         cycle++;
1245                                                                                         _avr_set_r(avr, 0, res);
1246                                                                                         _avr_set_r(avr, 1, res >> 8);
1247                                                                                         avr->sreg[S_Z] = res == 0;
1248                                                                                         avr->sreg[S_C] = (res >> 15) & 1;
1249                                                                                         SREG();
1250                                                                                 }       break;
1251                                                                                 default: _avr_invalid_opcode(avr);
1252                                                                         }
1253                                                         }
1254                                                 }       break;
1255                                         }
1256                                 }       break;
1257                         }
1258                 }       break;
1259
1260                 case 0xb000: {
1261                         switch (opcode & 0xf800) {
1262                                 case 0xb800: {  // OUT A,Rr 1011 1AAr rrrr AAAA
1263                                         uint8_t r = (opcode >> 4) & 0x1f;
1264                                         uint8_t A = ((((opcode >> 9) & 3) << 4) | ((opcode) & 0xf)) + 32;
1265                                         STATE("out %s, %s[%02x]\n", avr_regname(A), avr_regname(r), avr->data[r]);
1266                                         _avr_set_ram(avr, A, avr->data[r]);
1267                                 }       break;
1268                                 case 0xb000: {  // IN Rd,A 1011 0AAr rrrr AAAA
1269                                         uint8_t r = (opcode >> 4) & 0x1f;
1270                                         uint8_t A = ((((opcode >> 9) & 3) << 4) | ((opcode) & 0xf)) + 32;
1271                                         STATE("in %s, %s[%02x]\n", avr_regname(r), avr_regname(A), avr->data[A]);
1272                                         _avr_set_r(avr, r, _avr_get_ram(avr, A));
1273                                 }       break;
1274                                 default: _avr_invalid_opcode(avr);
1275                         }
1276                 }       break;
1277
1278                 case 0xc000: {
1279                         // RJMP 1100 kkkk kkkk kkkk
1280 //                      int16_t o = ((int16_t)(opcode << 4)) >> 4; // CLANG BUG!
1281                         int16_t o = ((int16_t)((opcode << 4)&0xffff)) >> 4;
1282                         STATE("rjmp .%d [%04x]\n", o, new_pc + (o << 1));
1283                         new_pc = new_pc + (o << 1);
1284                         cycle++;
1285                         TRACE_JUMP();
1286                 }       break;
1287
1288                 case 0xd000: {
1289                         // RCALL 1100 kkkk kkkk kkkk
1290 //                      int16_t o = ((int16_t)(opcode << 4)) >> 4; // CLANG BUG!
1291                         int16_t o = ((int16_t)((opcode << 4)&0xffff)) >> 4;
1292                         STATE("rcall .%d [%04x]\n", o, new_pc + (o << 1));
1293                         _avr_push16(avr, new_pc >> 1);
1294                         new_pc = new_pc + (o << 1);
1295                         cycle += 2;
1296                         // 'rcall .1' is used as a cheap "push 16 bits of room on the stack"
1297                         if (o != 0) {
1298                                 TRACE_JUMP();
1299                                 STACK_FRAME_PUSH();
1300                         }
1301                 }       break;
1302
1303                 case 0xe000: {  // LDI Rd, K 1110 KKKK RRRR KKKK -- aka SER (LDI r, 0xff)
1304                         uint8_t d = 16 + ((opcode >> 4) & 0xf);
1305                         uint8_t k = ((opcode & 0x0f00) >> 4) | (opcode & 0xf);
1306                         STATE("ldi %s, 0x%02x\n", avr_regname(d), k);
1307                         _avr_set_r(avr, d, k);
1308                 }       break;
1309
1310                 case 0xf000: {
1311                         switch (opcode & 0xfe00) {
1312                                 case 0xf000:
1313                                 case 0xf200:
1314                                 case 0xf400:
1315                                 case 0xf600: {  // All the SREG branches
1316                                         int16_t o = ((int16_t)(opcode << 6)) >> 9; // offset
1317                                         uint8_t s = opcode & 7;
1318                                         int set = (opcode & 0x0400) == 0;               // this bit means BRXC otherwise BRXS
1319                                         int branch = (avr->sreg[s] && set) || (!avr->sreg[s] && !set);
1320                                         const char *names[2][8] = {
1321                                                         { "brcc", "brne", "brpl", "brvc", NULL, "brhc", "brtc", "brid"},
1322                                                         { "brcs", "breq", "brmi", "brvs", NULL, "brhs", "brts", "brie"},
1323                                         };
1324                                         if (names[set][s]) {
1325                                                 STATE("%s .%d [%04x]\t; Will%s branch\n", names[set][s], o, new_pc + (o << 1), branch ? "":" not");
1326                                         } else {
1327                                                 STATE("%s%c .%d [%04x]\t; Will%s branch\n", set ? "brbs" : "brbc", _sreg_bit_name[s], o, new_pc + (o << 1), branch ? "":" not");
1328                                         }
1329                                         if (branch) {
1330                                                 cycle++; // 2 cycles if taken, 1 otherwise
1331                                                 new_pc = new_pc + (o << 1);
1332                                         }
1333                                 }       break;
1334                                 case 0xf800:
1335                                 case 0xf900: {  // BLD – Bit Store from T into a Bit in Register 1111 100r rrrr 0bbb
1336                                         uint8_t r = (opcode >> 4) & 0x1f; // register index
1337                                         uint8_t s = opcode & 7;
1338                                         uint8_t v = avr->data[r] | (avr->sreg[S_T] ? (1 << s) : 0);
1339                                         STATE("bld %s[%02x], 0x%02x = %02x\n", avr_regname(r), avr->data[r], 1 << s, v);
1340                                         _avr_set_r(avr, r, v);
1341                                 }       break;
1342                                 case 0xfa00:
1343                                 case 0xfb00:{   // BST – Bit Store into T from bit in Register 1111 100r rrrr 0bbb
1344                                         uint8_t r = (opcode >> 4) & 0x1f; // register index
1345                                         uint8_t s = opcode & 7;
1346                                         STATE("bst %s[%02x], 0x%02x\n", avr_regname(r), avr->data[r], 1 << s);
1347                                         avr->sreg[S_T] = (avr->data[r] >> s) & 1;
1348                                         SREG();
1349                                 }       break;
1350                                 case 0xfc00:
1351                                 case 0xfe00: {  // SBRS/SBRC – Skip if Bit in Register is Set/Clear 1111 11sr rrrr 0bbb
1352                                         uint8_t r = (opcode >> 4) & 0x1f; // register index
1353                                         uint8_t s = opcode & 7;
1354                                         int set = (opcode & 0x0200) != 0;
1355                                         int branch = ((avr->data[r] & (1 << s)) && set) || (!(avr->data[r] & (1 << s)) && !set);
1356                                         STATE("%s %s[%02x], 0x%02x\t; Will%s branch\n", set ? "sbrs" : "sbrc", avr_regname(r), avr->data[r], 1 << s, branch ? "":" not");
1357                                         if (branch) {
1358                                                 if (_avr_is_instruction_32_bits(avr, new_pc)) {
1359                                                         new_pc += 4; cycle += 2;
1360                                                 } else {
1361                                                         new_pc += 2; cycle++;
1362                                                 }
1363                                         }
1364                                 }       break;
1365                                 default: _avr_invalid_opcode(avr);
1366                         }
1367                 }       break;
1368
1369                 default: _avr_invalid_opcode(avr);
1370
1371         }
1372         avr->cycle += cycle;
1373         return new_pc;
1374 }
1375
1376