// https://www.fpga4fun.com/SPI2.html
-module SPI_slave(clk, SCK, MOSI, MISO, SSEL, LED);
+module SPI_slave(clk, SCK, MOSI, MISO, SSEL, LED,
+ d0,d1,d2,d3,d4,d5,d6,d7,d8,d9,d10,d11
+);
input clk;
output LED;
+input d0,d1,d2,d3,d4,d5,d6,d7,d8,d9,d10,d11;
+
// sync SCK to the FPGA clock using a 3-bits shift register
reg [2:0] SCKr; always @(posedge clk) SCKr <= {SCKr[1:0], SCK};
wire SCK_risingedge = (SCKr[2:1]==2'b01); // now we can detect SCK rising edges
// we handle SPI in 8-bits format, so we need a 3 bits counter to count the bits as they come in
reg [2:0] bitcnt;
+reg [1:0] bit_hl;
reg byte_received; // high when a byte has been received
reg [7:0] byte_data_received;
always @(posedge clk)
begin
if(~SSEL_active)
+ begin
bitcnt <= 3'b000;
+ bit_hl <= 1'b0;
+ end
else
if(SCK_risingedge)
begin
if(SCK_fallingedge)
begin
if(bitcnt==3'b000)
- byte_data_sent <= 8'h00; // after that, we send 0s
+ //byte_data_sent <= 8'h00; // after that, we send 0s
+ if(bit_hl == 0)
+ begin
+ byte_data_sent <= { d4,d5,d6,d7,d8,d9,d10,d11 };
+ bit_hl <= bit_hl + 1'b1;
+ end
+ else
+ begin
+ byte_data_sent <= { 4'b0000, d0,d1,d2,d3 };
+ bit_hl <= bit_hl + 1'b1;
+ end
else
byte_data_sent <= {byte_data_sent[6:0], 1'b0};
end
+`default_nettype none
+
`include "i2c_bridge.v"
`include "ecp5pll.sv"
`include "SPI_slave.v"
input spi_sclk, spi_mosi, spi_cs0,
output spi_miso,
+ input a2dq2, a2dq3, a2dq4, a2dq5, a2dq6, a2dq7, a2dq8, a2dq9, a2dq10, a2dq11, a2dq12, a2dq13,
+
output green_led_d7,
output orange_led_d8,
output red_led_d5,
#(
.in_hz(24000000),
.out0_hz(16000000),.out0_tol_hz(0) ,
- .out1_hz(96000000), .out1_deg( 0), .out1_tol_hz(0)//,
- //.out2_hz(60000000), .out2_deg(180), .out2_tol_hz(0),
+ .out1_hz(96000000), .out1_deg( 0), .out1_tol_hz(0),
+ .out2_hz(192000000), .out2_deg(0), .out2_tol_hz(0)
)
ecp5pll_inst
(
wire [1:0] i2c_sda_t;
i2c_bridge i2c_sda_bridge_i
(
- .clk(clk),
+ .clk(mhz_96),
.clk_en(clk_bridge_en),
.i(i2c_sda_i),
.t(i2c_sda_t)
assign rtc_scl = i2c_scl_t[1] ? 1'bz : 1'b0;
assign tuner_scl = i2c_scl_t[0] ? 1'bz : 1'b0;
-
SPI_slave SPI_slave(
- .clk(clk),
+ .clk(clocks[2]),
.SCK(spi_sclk),
.MOSI(spi_mosi),
.MISO(spi_miso),
.SSEL(spi_cs0),
- .LED(red_led_d5)
+ .LED(red_led_d5),
+ .d0(a2dq2),
+ .d1(a2dq3),
+ .d2(a2dq4),
+ .d3(a2dq5),
+ .d4(a2dq6),
+ .d5(a2dq7),
+ .d6(a2dq8),
+ .d7(a2dq9),
+ .d8(a2dq10),
+ .d9(a2dq11),
+ .d10(a2dq12),
+ .d11(a2dq13),
);
endmodule