#define MCCR1VAL (CFG_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CFG_ROMFAL << MCCR1_ROMFAL_SHIFT)
#endif
+
+#define UART1 0xfc004500
+#define UART1_IER 0xfc004501
+#define UART1_FCR 0xfc004502
+#define UART1_LCR 0xfc004503
+#define UART1_DCR 0xfc004511
+
+#define WM8(address,data) \
+ lis r3, address@h; \
+ ori r3, r3, address@l; \
+ li r4, data; \
+ stb r4, 0(r3); \
+ sync; \
+ isync;
+
.text
/* Values to program into memory controller registers */
early_init_f:
mflr r10
+ WM8(0xfc004500,0x44);
+
+#if 0
+
/* basic memory controller configuration */
lis r3, CONFIG_ADDR_HIGH
lis r4, CONFIG_DATA_HIGH
/* set up stack pointer */
lis r1, CFG_INIT_SP_OFFSET@h
ori r1, r1, CFG_INIT_SP_OFFSET@l
+#endif
mtlr r10
blr