#undef USE_DINK32
#endif
-#define CONFIG_CONS_INDEX 3 /* set to '3' for on-chip DUART */
+#define CONFIG_CONS_INDEX 1 /* set to '3' for on-chip DUART */
#define CONFIG_BAUDRATE 9600
#define CONFIG_DRAM_SPEED 100 /* MHz */
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_ELF | \
- CFG_CMD_I2C | \
- CFG_CMD_EEPROM | \
- CFG_CMD_NFS | \
- CFG_CMD_PCI | \
- CFG_CMD_SNTP )
+#define CONFIG_COMMANDS ( \
+ CFG_CMD_BDI | \
+ CFG_CMD_FLASH | \
+ CFG_CMD_LOADS | \
+ CFG_CMD_LOADB | \
+ CFG_CMD_MEMORY | \
+ CFG_CMD_CONSOLE | \
+ CFG_CMD_RUN | \
+ CFG_CMD_ECHO | \
+ CFG_CMD_PCI )
+
+#undef CONFIG_VIDEO
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
+/* 0x00 for 66 MHz, 0x40 for 33 MHz */
+#define CFG_PCI_HOLD_DEL 0x40
/*
* Miscellaneous configurable options
*/
#define CONFIG_PCI /* include pci support */
#undef CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW
-#define CONFIG_NET_MULTI /* Multi ethernet cards support */
-
-#define CONFIG_EEPRO100
-#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
-#define CONFIG_NATSEMI
-#define CONFIG_NS8382X
-
-#define PCI_ENET0_IOADDR 0x80000000
-#define PCI_ENET0_MEMADDR 0x80000000
-#define PCI_ENET1_IOADDR 0x81000000
-#define PCI_ENET1_MEMADDR 0x81000000
+/*-----------------------------------------------------------------------
+ * Change TEXT_BASE in bord/linkstation/config.mk to get a RAM build
+ *
+ * RAM based builds are for testing purposes. A Linux module, uloader.o,
+ * exists to load U-Boot and pass control to it
+ *
+ * Always do "make clean" after changing the build type
+ */
+#if CFG_MONITOR_BASE < CFG_FLASH_BASE
+#define CFG_RAMBOOT
+#warn CFG_RAMBOOT
+#endif
/*-----------------------------------------------------------------------
#endif
-#define CFG_FLASH_BASE 0xFFF00000
+#define CFG_FLASH_BASE 0xFFC00000
#if 0
#define CFG_FLASH_SIZE (512 * 1024) /* sandpoint has tiny eeprom */
#else
-#define CFG_FLASH_SIZE (1024 * 1024) /* Unity has onboard 1MByte flash */
+#define CFG_FLASH_SIZE (4 * 1024 * 1024) /* 4MByte flash */
#endif
+
+#if 0
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_OFFSET 0x00004000 /* Offset of Environment Sector */
#define CFG_ENV_SIZE 0x00002000 /* Total Size of Environment Sector */
+#endif
+
+#undef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_IS_NOWHERE
+#define CFG_ENV_SIZE 0x20000
#define CFG_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */
#define CFG_MEMTEST_START 0x00000000 /* memtest works on */
-#define CFG_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */
+#define CFG_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
#define CFG_EUMB_ADDR 0xFC000000
-
+/*
#define CFG_ISA_MEM 0xFD000000
#define CFG_ISA_IO 0xFE000000
-
-#define CFG_FLASH_RANGE_BASE 0xFF000000 /* flash memory address range */
-#define CFG_FLASH_RANGE_SIZE 0x01000000
-#define FLASH_BASE0_PRELIM 0xFFF00000 /* sandpoint flash */
+*/
+#define CFG_FLASH_RANGE_BASE 0xFFC00000 /* flash memory address range */
+#define CFG_FLASH_RANGE_SIZE 0x00400000
+#define FLASH_BASE0_PRELIM 0xFFC00000 /* sandpoint flash */
#define FLASH_BASE1_PRELIM 0xFF000000 /* PMC onboard flash */
/*
* If the software driver is chosen, there are some additional
* configuration items that the driver uses to drive the port pins.
*/
+#if 0
#define CONFIG_HARD_I2C 1 /* To enable I2C support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
+#endif
#ifdef CONFIG_SOFT_I2C
#error "Soft I2C is not configured properly. Please review!"
#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
#endif /* CONFIG_SOFT_I2C */
+#if 0
#define CFG_I2C_EEPROM_ADDR 0x57 /* EEPROM IS24C02 */
#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
#define CFG_EEPROM_PAGE_WRITE_BITS 3
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
+#endif
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-#define CFG_FLASH_BANKS { FLASH_BASE0_PRELIM , FLASH_BASE1_PRELIM }
+#define CFG_FLASH_BANKS { FLASH_BASE0_PRELIM }
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
-
+#if 0
#define CFG_WINBOND_83C553 1 /*has a winbond bridge */
#define CFG_USE_WINBOND_IDE 0 /*use winbond 83c553 internal IDE ctrlr */
#define CFG_WINBOND_ISA_CFG_ADDR 0x80005800 /*pci-isa bridge config addr */
#define CFG_NS87308_CS2_BASE 0x0074
#define CFG_NS87308_CS2_CONF 0x30
+#endif
+
/*
* NS16550 Configuration
*/
#define CFG_NS16550_REG_SIZE 1
-#if (CONFIG_CONS_INDEX > 2)
-#define CFG_NS16550_CLK CONFIG_DRAM_SPEED*1000000
-#else
-#define CFG_NS16550_CLK 1843200
-#endif
+#define CFG_NS16550_CLK 100000000
-#define CFG_NS16550_COM1 (CFG_ISA_IO + CFG_NS87308_UART1_BASE)
-#define CFG_NS16550_COM2 (CFG_ISA_IO + CFG_NS87308_UART2_BASE)
-#define CFG_NS16550_COM3 (CFG_EUMB_ADDR + 0x4500)
-#define CFG_NS16550_COM4 (CFG_EUMB_ADDR + 0x4600)
+#define CFG_NS16550_COM1 (CFG_EUMB_ADDR + 0x4500)
+#define CFG_NS16550_COM2 (CFG_EUMB_ADDR + 0x4600)
/*
* Low Level Configuration Settings
* You should know what you are doing if you make changes here.
*/
-#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
+#define CONFIG_SYS_CLK_FREQ 100000000 /* external frequency to pll */
-#define CFG_ROMNAL 7 /*rom/flash next access time */
-#define CFG_ROMFAL 11 /*rom/flash access time */
+#define CFG_ROMNAL 8 /*rom/flash next access time */
+#define CFG_ROMFAL 13 /*rom/flash access time */
#define CFG_REFINT 430 /* no of clock cycles between CBR refresh cycles */
#define CFG_REFREC 8 /* Refresh to activate interval */
#define CFG_RDLAT 4 /* data latency from read command */
#define CFG_PRETOACT 3 /* Precharge to activate interval */
-#define CFG_ACTTOPRE 5 /* Activate to Precharge interval */
+#define CFG_ACTTOPRE 6 /* Activate to Precharge interval */
#define CFG_ACTORW 3 /* Activate to R/W */
#define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */
#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */
/*-----------------------------------------------------------------------
* FLASH organization
*/
-#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
-#define CFG_MAX_FLASH_SECT 20 /* max number of sectors on one chip */
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
+/*-----------------------------------------------------------------------
+ * Partitions and file system
+ */
+#define CONFIG_DOS_PARTITION
/*
* Internal Definitions
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-/* values according to the manual */
-
-#define CONFIG_DRAM_50MHZ 1
-#define CONFIG_SDRAM_50MHZ
-
-#undef NR_8259_INTS
-#define NR_8259_INTS 1
-
-
-#define CONFIG_DISK_SPINUP_TIME 1000000
-
-
#endif /* __CONFIG_H */
projects / u-boot.git / blobdiff