1 //////////////////////////////////////////////////////////////////////////////
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8 // Company: JYE Tech Ltd.
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9 // Web: www.jyetech.com
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11 //-----------------------------------------------------------------------------
13 // Target: STM32F103C8
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14 // Tool chain: CodeSourcery G++
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16 //-----------------------------------------------------------------------------
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19 //-----------------------------------------------------------------------------
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23 //-----------------------------------------------------------------------------
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24 // Revision History:
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26 ///////////////////////////////////////////////////////////////////////////////
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28 //-----------------------------------------------------------------------------
30 //-----------------------------------------------------------------------------
32 #include "stm32f10x.h"
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36 #include "libdso138.h"
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38 // ===========================================================
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39 // File Scope Variables
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40 // ===========================================================
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48 //U8 GeneralBuf[50];
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50 // ===========================================================
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51 // Function Definitions
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52 // ===========================================================
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54 //-----------------------------------------------------------------------------
56 //-----------------------------------------------------------------------------
58 void Clock_Init(void)
\r
60 RCC->CR = (1 << HSION) /*!< Internal High Speed clock enable */
\r
61 |(0 << HSIRDY) /*!< Internal High Speed clock ready flag */
\r
62 |(0x10 << HSITRIM) /*!< Internal High Speed clock trimming */
\r
63 |(0 << HSICAL) /*!< Internal High Speed clock Calibration */
\r
64 |(1 << HSEON) /*!< External High Speed clock enable */
\r
65 |(0 << HSERDY) /*!< External High Speed clock ready flag */
\r
66 |(0 << HSEBYP) /*!< External High Speed clock Bypass */
\r
67 |(0 << CSSON) /*!< Clock Security System enable */
\r
68 |(0 << PLLON) /*!< PLL enable */
\r
69 |(0 << PLLRDY); /*!< PLL clock ready flag */
\r
71 // MCO[2:0] : Microcontroller clock output
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73 // 100: System clock (SYSCLK) selected
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74 // 101: HSI clock selected
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75 // 110: HSE clock selected
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76 // 111: PLL clock divided by 2 selected
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78 // USBPRE: USB prescaler
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79 // Set and cleared by software to generate 48 MHz USB clock. This bit must be valid before
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80 // enabling the USB clock in the RCC_APB1ENR register. This bit can¡¯t be reset if the USB
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81 // clock is enabled.
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82 // 0: PLL clock is divided by 1.5
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83 // 1: PLL clock is not divided
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85 // PLLMUL[3:0] : PLL multiplication factor
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86 // These bits are written by software to define the PLL multiplication factor. These bits can be
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87 // written only when PLL is disabled.
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88 // 0000: PLL input clock x 2
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89 // 0001: PLL input clock x 3
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90 // 0010: PLL input clock x 4
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91 // 0011: PLL input clock x 5
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92 // 0100: PLL input clock x 6
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93 // 0101: PLL input clock x 7
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94 // 0110: PLL input clock x 8
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95 // 0111: PLL input clock x 9
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96 // 1000: PLL input clock x 10
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97 // 1001: PLL input clock x 11
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98 // 1010: PLL input clock x 12
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99 // 1011: PLL input clock x 13
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100 // 1100: PLL input clock x 14
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101 // 1101: PLL input clock x 15
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102 // 1110: PLL input clock x 16
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103 // 1111: PLL input clock x 16
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105 // PLLXTPRE: HSE divider for PLL entry
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106 // Set and cleared by software to divide HSE before PLL entry. This bit can be written only
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107 // when PLL is disabled.
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108 // 0: HSE clock not divided
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109 // 1: HSE clock divided by 2
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111 // PLLSRC: PLL entry clock source
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112 // Set and cleared by software to select PLL clock source. This bit can be written only when
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113 // PLL is disabled.
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114 // 0: HSI oscillator clock / 2 selected as PLL input clock
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115 // 1: HSE oscillator clock selected as PLL input clock
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117 // ADCPRE[1:0] : ADC prescaler
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118 // Set and cleared by software to select the frequency of the clock to the ADCs.
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119 // 00: PLCK2 divided by 2
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120 // 01: PLCK2 divided by 4
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121 // 10: PLCK2 divided by 6
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122 // 11: PLCK2 divided by 8
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124 // PPRE2[2:0] : APB high-speed prescaler (APB2)
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125 // Set and cleared by software to control the division factor of the APB high-speed clock
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127 // 0xx: HCLK not divided
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128 // 100: HCLK divided by 2
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129 // 101: HCLK divided by 4
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130 // 110: HCLK divided by 8
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131 // 111: HCLK divided by 16
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133 // PPRE1[2:0] : APB low-speed prescaler (APB1)
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134 // Set and cleared by software to control the division factor of the APB low-speed clock
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136 // Warning: the software has to set correctly these bits to not exceed 36 MHz on this domain.
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137 // 0xx: HCLK not divided
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138 // 100: HCLK divided by 2
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139 // 101: HCLK divided by 4
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140 // 110: HCLK divided by 8
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141 // 111: HCLK divided by 16
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143 // HPRE[3:0] : AHB prescaler
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144 // Set and cleared by software to control the division factor of the AHB clock.
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145 // 0xxx: SYSCLK not divided
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146 // 1000: SYSCLK divided by 2
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147 // 1001: SYSCLK divided by 4
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148 // 1010: SYSCLK divided by 8
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149 // 1011: SYSCLK divided by 16
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150 // 1100: SYSCLK divided by 64
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151 // 1101: SYSCLK divided by 128
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152 // 1110: SYSCLK divided by 256
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153 // 1111: SYSCLK divided by 512
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155 // SWS[1:0] : System clock switch status
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156 // Set and cleared by hardware to indicate which clock source is used as system clock.
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157 // 00: HSI oscillator used as system clock
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158 // 01: HSE oscillator used as system clock
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159 // 10: PLL used as system clock
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160 // 11: not applicable
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162 // SW[1:0] : System clock switch
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163 // Set and cleared by software to select SYSCLK source.
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164 // Set by hardware to force HSI selection when leaving Stop and Standby mode or in case of
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165 // failure of the HSE oscillator used directly or indirectly as system clock (if the Clock Security
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166 // System is enabled).
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167 // 00: HSI selected as system clock
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168 // 01: HSE selected as system clock
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169 // 10: PLL selected as system clock
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172 RCC->CFGR = (0 << SW) /*!< SW[1:0] bits (System clock Switch) */
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173 |(0 << SWS) /*!< SWS[1:0] bits (System Clock Switch Status) */
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174 |(0 << HPRE) /*!< HPRE[3:0] bits (AHB prescaler) [HCLK] */
\r
175 |(0b100 << PPRE1) /*!< PRE1[2:0] bits (APB1 prescaler) [PCLK1] */
\r
176 |(0 << PPRE2) /*!< PRE2[2:0] bits (APB2 prescaler) [PCLK2] */
\r
177 |(2 << ADCPRE) /*!< ADCPRE[1:0] bits (ADC prescaler) */
\r
178 |(1 << PLLSRC) /*!< PLL entry clock source */
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179 |(0 << PLLXTPRE) /*!< HSE divider for PLL entry */
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180 |(7 << PLLMULL) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
\r
181 |(0 << USBPRE) /*!< USB Device prescaler */
\r
182 |(0 << MCO); /*!< MCO[2:0] bits (Microcontroller Clock Output) */
\r
184 RCC->CR = (1 << HSION) /*!< Internal High Speed clock enable */
\r
185 |(0 << HSIRDY) /*!< Internal High Speed clock ready flag */
\r
186 |(0x10 << HSITRIM) /*!< Internal High Speed clock trimming */
\r
187 |(0 << HSICAL) /*!< Internal High Speed clock Calibration */
\r
188 |(1 << HSEON) /*!< External High Speed clock enable */
\r
189 |(0 << HSERDY) /*!< External High Speed clock ready flag */
\r
190 |(0 << HSEBYP) /*!< External High Speed clock Bypass */
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191 |(0 << CSSON) /*!< Clock Security System enable */
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192 |(1 << PLLON) /*!< PLL enable */
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193 |(0 << PLLRDY); /*!< PLL clock ready flag */
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196 RCC->CIR = (0 << LSIRDYF) /*!< LSI Ready Interrupt flag */
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197 |(0 << LSERDYF) /*!< LSE Ready Interrupt flag */
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198 |(0 << HSIRDYF) /*!< HSI Ready Interrupt flag */
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199 |(0 << HSERDYF) /*!< HSE Ready Interrupt flag */
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200 |(0 << PLLRDYF) /*!< PLL Ready Interrupt flag */
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201 |(0 << CSSF) /*!< Clock Security System Interrupt flag */
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202 |(0 << LSIRDYIE ) /*!< LSI Ready Interrupt Enable */
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203 |(0 << LSERDYIE) /*!< LSE Ready Interrupt Enable */
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204 |(0 << HSIRDYIE) /*!< HSI Ready Interrupt Enable */
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205 |(0 << HSERDYIE) /*!< HSE Ready Interrupt Enable */
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206 |(0 << PLLRDYIE) /*!< PLL Ready Interrupt Enable */
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207 |(0 << LSIRDYC) /*!< LSI Ready Interrupt Clear */
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208 |(0 << LSERDYC) /*!< LSE Ready Interrupt Clear */
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209 |(0 << HSIRDYC) /*!< HSI Ready Interrupt Clear */
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210 |(0 << HSERDYC) /*!< HSE Ready Interrupt Clear */
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211 |(0 << PLLRDYC) /*!< PLL Ready Interrupt Clear */
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212 |(0 << CSSC); /*!< Clock Security System Interrupt Clear */
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215 RCC->APB2RSTR = (0 << AFIORST) /*!< Alternate Function I/O reset */
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216 |(0 << IOPARST) /*!< I/O port A reset */
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217 |(0 << IOPBRST) /*!< I/O port B reset */
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218 |(0 << IOPCRST) /*!< I/O port C reset */
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219 |(0 << IOPDRST) /*!< I/O port D reset */
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220 |(0 << IOPERST) /*!< I/O port E reset */
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221 |(0 << IOPFRST) /*!< I/O port F reset */
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222 |(0 << IOPGRST) /*!< I/O port G reset */
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223 |(0 << ADC1RST) /*!< ADC 1 interface reset */
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224 |(0 << ADC2RST) /*!< ADC 2 interface reset */
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225 |(0 << TIM1RST) /*!< TIM1 Timer reset */
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226 |(0 << SPI1RST) /*!< SPI 1 reset */
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227 |(0 << TIM8RST) /*!< TIM8 Timer reset */
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228 |(0 << USART1RST) /*!< USART1 reset */
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229 |(0 << ADC3RST); /*!< ADC3 interface reset */
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231 RCC->APB1RSTR = (0 << TIM2RST) /*!< Timer 2 reset */
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232 |(0 << TIM3RST) /*!< Timer 3 reset */
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233 |(0 << TIM4RST) /*!< Timer 4 reset */
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234 |(0 << TIM5RST) /*!< Timer 5 reset */
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235 |(0 << TIM6RST) /*!< Timer 6 reset */
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236 |(0 << TIM7RST) /*!< Timer 7 reset */
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237 |(0 << WWDGRST) /*!< Window Watchdog reset */
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238 |(0 << SPI2RST) /*!< SPI 2 reset */
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239 |(0 << SPI3RST) /*!< SPI 3 reset */
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240 |(0 << USART2RST) /*!< USART 2 reset */
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241 |(0 << USART3RST) /*!< RUSART 3 reset */
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242 |(0 << UART4RST ) /*!< UART 4 reset */
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243 |(0 << UART5RST) /*!< UART 5 reset */
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244 |(0 << I2C1RST) /*!< I2C 1 reset */
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245 |(0 << I2C2RST) /*!< I2C 2 reset */
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246 |(0 << USBRST) /*!< USB Device reset */
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247 |(0 << CAN1RST) /*!< CAN1 reset */
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248 |(0 << BKPRST) /*!< Backup interface reset */
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249 |(0 << PWRRST) /*!< Power interface reset */
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250 |(0 << DACRST); /*!< DAC interface reset */
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253 RCC->AHBENR = (0 << SDIOEN)
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261 RCC->APB1ENR = (0 << DACEN)
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282 RCC->APB2ENR = (0 << ADC3EN)
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298 RCC->BDCR = 0x00000000;
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299 RCC->CSR = 0x00000000;
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301 // Switch to HSE if it is ready
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302 if(BitTest(RCC->CR, (1 << HSERDY))) {
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303 RCC->CFGR &= ~RCC_CFGR_SW;
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304 RCC->CFGR |= RCC_CFGR_SW_HSE;
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307 // Switch to PLL if it is ready
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308 if(BitTest(RCC->CR, (1 << PLLRDY))) {
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309 RCC->CFGR &= ~RCC_CFGR_SW;
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310 RCC->CFGR |= RCC_CFGR_SW_PLL;
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315 //-----------------------------------------------------------------------------
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317 //-----------------------------------------------------------------------------
319 //-----------------------------------------------------------------------------
321 //-----------------------------------------------------------------------------
323 // This routine configures the crossbar and GPIO ports.
325 void Port_Init(void)
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327 GPIOA->CRL = ((GPIO_CNF_AnalogIn | GPIO_Mode_In) << (0*4)) // ADC1_IN0
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328 |((GPIO_CNF_Floating | GPIO_Mode_In) << (1*4))
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329 |((GPIO_CNF_Floating|GPIO_Mode_In) << (2*4))
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330 |((GPIO_CNF_Floating |GPIO_Mode_In) << (3*4))
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331 |((GPIO_CNF_Floating | GPIO_Mode_In) << (4*4))
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332 |((GPIO_CNF_Floating | GPIO_Mode_In) << (5*4))
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333 |((GPIO_CNF_Floating | GPIO_Mode_In) << (6*4))
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334 |((GPIO_CNF_AF_PP | GPIO_Mode_Out50M) << (7*4)); //Test signal
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337 GPIOA->CRH = ((GPIO_CNF_Floating| GPIO_Mode_In) << (8 - 8)*4) // TrigIn
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338 |((GPIO_CNF_AF_PP |GPIO_Mode_Out50M) << (9 - 8)*4) // TX1
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339 |((GPIO_CNF_Floating | GPIO_Mode_In) << (10 - 8)*4) // RX1
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340 |((GPIO_CNF_Floating | GPIO_Mode_In) << (11 - 8)*4)
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341 |((GPIO_CNF_Floating | GPIO_Mode_In) << (12 - 8)*4)
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342 |((GPIO_CNF_Floating | GPIO_Mode_In) << (13 - 8)*4)
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343 |((GPIO_CNF_Floating | GPIO_Mode_In) << (14 - 8)*4)
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344 |((GPIO_CNF_GP_PP | GPIO_Mode_Out50M) << (15 - 8)*4); // LED
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346 GPIOA->ODR = 0xFFFF;
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348 GPIOB->CRL = ((GPIO_CNF_GP_PP | GPIO_Mode_Out50M) << (0*4)) // TFT port - D0
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349 |((GPIO_CNF_GP_PP | GPIO_Mode_Out50M) << (1*4)) // TFT port - D1
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350 |((GPIO_CNF_GP_PP | GPIO_Mode_Out50M) << (2*4)) // TFT port - D2
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351 |((GPIO_CNF_GP_PP | GPIO_Mode_Out50M) << (3*4)) // TFT port - D3
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352 |((GPIO_CNF_GP_PP | GPIO_Mode_Out50M) << (4*4)) // TFT port - D4
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353 |((GPIO_CNF_GP_PP | GPIO_Mode_Out50M) << (5*4)) // TFT port - D5
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354 |((GPIO_CNF_GP_PP | GPIO_Mode_Out50M) << (6*4)) // TFT port - D6
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355 |((GPIO_CNF_GP_PP | GPIO_Mode_Out50M) << (7*4)); // TFT port - D7
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357 GPIOB->CRH = ((GPIO_CNF_AF_PP| GPIO_Mode_Out50M) << ((8 - 8)*4)) // Output, Trigger level
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358 |((GPIO_CNF_AF_PP| GPIO_Mode_Out50M) << ((9 - 8)*4)) // Output, Gen
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359 |((GPIO_CNF_GP_PP | GPIO_Mode_Out50M) << ((10 - 8)*4)) // Output, TFT_nRD
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360 |((GPIO_CNF_GP_PP | GPIO_Mode_Out50M) << ((11 - 8)*4)) // Output, TFT_nReset
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361 |((GPIO_CNF_IPU | GPIO_Mode_In) << ((12 - 8)*4)) // SW4
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362 |((GPIO_CNF_IPU | GPIO_Mode_In) << ((13 - 8)*4)) // SW3
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363 |((GPIO_CNF_IPU | GPIO_Mode_In) << ((14 - 8)*4)) // SW2
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364 |((GPIO_CNF_IPU | GPIO_Mode_In) << ((15 - 8)*4)); // SW1
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366 GPIOB->ODR = 0xFFFF;
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368 GPIOC->CRH = ((GPIO_CNF_GP_PP | GPIO_Mode_Out50M) << (13 - 8)*4) // TFT_nCS
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369 |((GPIO_CNF_GP_PP | GPIO_Mode_Out50M) << (14 - 8)*4) // TFT_RS
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370 |((GPIO_CNF_GP_PP | GPIO_Mode_Out50M) << (15 - 8)*4); // TFT_nWR
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372 GPIOC->ODR = 0xFFFF;
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374 GPIOD->CRL = ((GPIO_CNF_Floating | GPIO_Mode_In) << (0*4))
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375 |((GPIO_CNF_Floating | GPIO_Mode_In) << (1*4));
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377 // Remap to make PB3 & PB4 available
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378 AFIO->MAPR &= ~AFIO_MAPR_SWJ_CFG;
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379 AFIO->MAPR |= AFIO_MAPR_SWJ_CFG_1;
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383 void USART1_Init(void)
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385 USART_InitTypeDef USART_InitStructure;
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387 USART_InitStructure.USART_BaudRate = 38400;
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388 USART_InitStructure.USART_WordLength = USART_WordLength_8b;
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389 USART_InitStructure.USART_StopBits = USART_StopBits_1;
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390 USART_InitStructure.USART_Parity = USART_Parity_No;
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391 USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
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392 USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
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394 /* Configure USART1 */
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395 USART_Init(USART1, &USART_InitStructure);
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397 /* Enable the USART1 */
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398 USART_Cmd(USART1, ENABLE);
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402 void UartPutc(U8 ch, USART_TypeDef* USARTx)
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404 while(USART_GetFlagStatus(USARTx, USART_FLAG_TXE) == RESET) {
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406 USART_SendData(USARTx, ch);
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409 void uputs(U8 *s, USART_TypeDef* USARTx)
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412 UartPutc(*s, USARTx);
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417 void TIM3_Init(void)
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419 // Disable counter first
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420 TIM3->CR1 = (0 << CEN) //!<Counter enable //
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421 | (0 << UDIS) //!<Update disable //
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422 | (0 << URS) //!<Update request source //
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423 | (0 << OPM) //!<One pulse mode //
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424 | (0 << DIR) //!<Direction. 0: Up, 1: Down
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425 | (0 << CMS) //!<CMS[1:0] bits (Center-aligned mode selection) //
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426 | (1 << ARPE) //!<Auto-reload preload enable //
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427 | (0 << CKD); //!<CKD[1:0] bits (clock division for filtering) 0 = 1/1, 1 = 1/2, 2 = 1/4
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429 TIM3->CR2 = (0 << CCPC) //<Capture/Compare Preloaded Control //
\r
430 | (0 << CCUS) //<Capture/Compare Control Update Selection //
\r
431 | (0 << CCDS) //<Capture/Compare DMA Selection //
\r
432 | (0 << MMS) //<MMS[2:0] bits (Master Mode Selection) //
\r
433 | (0 << TI1S) //<TI1 Selection //
\r
434 | (0 << OIS1) //<Output Idle state 1 (OC1 output) //
\r
435 | (0 << OIS1N) //<Output Idle state 1 (OC1N output) //
\r
436 | (0 << OIS2) //<Output Idle state 2 (OC2 output) //
\r
437 | (0 << OIS2N) //<Output Idle state 2 (OC2N output) //
\r
438 | (0 << OIS3) //<Output Idle state 3 (OC3 output) //
\r
439 | (0 << OIS3N) //<Output Idle state 3 (OC3N output) //
\r
440 | (0 << OIS4); //<Output Idle state 4 (OC4 output) //
\r
442 TIM3->SMCR = (0 << SMS) //<SMS[2:0] bits (Slave mode selection) //
\r
443 | (0 << TS) //<TS[2:0] bits (Trigger selection) //
\r
444 | (0 << MSM) //<Master/slave mode //
\r
445 | (0 << ETF) //<ETF[3:0] bits (External trigger filter) //
\r
446 | (0 << ETPS) //<ETPS[1:0] bits (External trigger prescaler) //
\r
447 | (0 << ECE) //<External clock enable //
\r
448 | (0 << ETP); //<External trigger polarity //
\r
451 TIM3->DIER = (0 << UIE) //<Update interrupt enable //
\r
452 | (0 << CC1IE) //<Capture/Compare 1 interrupt enable //
\r
453 | (0 << CC2IE) //<Capture/Compare 2 interrupt enable //
\r
454 | (0 << CC3IE) //<Capture/Compare 3 interrupt enable //
\r
455 | (0 << CC4IE) //<Capture/Compare 4 interrupt enable //
\r
456 | (0 << COMIE) //<COM interrupt enable //
\r
457 | (0 << TIE) //<Trigger interrupt enable //
\r
458 | (0 << BIE) //<Break interrupt enable //
\r
459 | (0 << UDE) //<Update DMA request enable //
\r
460 | (0 << CC1DE) //<Capture/Compare 1 DMA request enable //
\r
461 | (0 << CC2DE) //<Capture/Compare 2 DMA request enable //
\r
462 | (0 << CC3DE) //<Capture/Compare 3 DMA request enable //
\r
463 | (0 << CC4DE) //<Capture/Compare 4 DMA request enable //
\r
464 | (0 << COMDE) //<COM DMA request enable //
\r
465 | (0 << TDE); //<Trigger DMA request enable //
\r
469 TIM3->EGR = 0x0000;
\r
471 //----------------------------------------------------------------------------
\r
472 // TIMx capture/compare usage (x = 2 ~ 5, n = 1 ~ 4)
\r
475 // 00: CCn channel is configured as output.
\r
476 // 01: CCn channel is configured as input, ICn is mapped on TI1.
\r
477 // 10: CCn channel is configured as input, ICn is mapped on TI2.
\r
478 // 11: CCn channel is configured as input, ICn is mapped on TRC. This mode is working only
\r
479 // if an internal trigger input is selected through TS bit (TIMx_SMCR register)
\r
480 // Note: CCnS bits are writable only when the channel is OFF (CCnE = 0 in TIMx_CCER).
\r
481 // Output compare mode
\r
485 // 001: Set channel n to active level on match.
\r
486 // 010: Set channel n to inactive level on match.
\r
487 // 011: Toggle - OCnREF toggles when TIMx_CNT=TIMx_CCRn.
\r
488 // 100: Force inactive level - OCnREF is forced low.
\r
489 // 101: Force active level - OCnREF is forced high.
\r
490 // 110: PWM mode 1 - In upcounting, channel n is active as long as TIMx_CNT<TIMx_CCRn
\r
491 // else inactive. In downcounting, channel 1 is inactive (OCnREF=0) as long as
\r
492 // TIMx_CNT>TIMx_CCRn else active (OCnREF=1).
\r
493 // 111: PWM mode 2 - In upcounting, channel n is inactive as long as
\r
494 // TIMx_CNT<TIMx_CCRn else active. In downcounting, channel n is active as long as
\r
495 // TIMx_CNT>TIMx_CCRn else inactive.
\r
496 // Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed
\r
497 // (LOCK bits in TIMx_BDTR register) and CC1S=00 (the channel is configured in output).
\r
498 // 2: In PWM mode 1 or 2, the OCREF level changes only when the result of the
\r
499 // comparison changes or when the output compare mode switches from "frozen" mode
\r
503 // This bit-field defines the ratio of the prescaler acting on CCn input (ICn).
\r
504 // The prescaler is reset as soon as CC1E= 0 (TIMx_CCER register).
\r
505 // 00: no prescaler, capture is done each time an edge is detected on the capture input.
\r
506 // 01: capture is done once every 2 events.
\r
507 // 10: capture is done once every 4 events.
\r
508 // 11: capture is done once every 8 events.
\r
511 // This bit-field defines the frequency used to sample TIn input and the length of the digital
\r
512 // filter applied to TIn. The digital filter is made of an event counter in which N events are
\r
513 // needed to validate a transition on the output:
\r
514 // 0000: No filter, sampling is done at fDTS.
\r
515 // 0001: fSAMPLING=fCK_INT, N=2.
\r
516 // 0010: fSAMPLING=fCK_INT, N=4.
\r
517 // 0011: fSAMPLING=fCK_INT, N=8.
\r
518 // 0100: fSAMPLING=fDTS/2, N=6.
\r
519 // 0101: fSAMPLING=fDTS/2, N=8.
\r
520 // 0110: fSAMPLING=fDTS/4, N=6.
\r
521 // 0111: fSAMPLING=fDTS/4, N=8.
\r
522 // 1000: fSAMPLING=fDTS/8, N=6.
\r
523 // 1001: fSAMPLING=fDTS/8, N=8.
\r
524 // 1010: fSAMPLING=fDTS/16, N=5.
\r
525 // 1011: fSAMPLING=fDTS/16, N=6.
\r
526 // 1100: fSAMPLING=fDTS/16, N=8.
\r
527 // 1101: fSAMPLING=fDTS/32, N=5.
\r
528 // 1110: fSAMPLING=fDTS/32, N=6.
\r
529 // 1111: fSAMPLING=fDTS/32, N=8.
\r
530 // Note: In current silicon revision, fDTS is replaced in the formula by CK_INT
\r
531 // when ICnF[3:0]= 1, 2 or 3.
\r
533 // Output compare mode
\r
534 TIM3->CCMR1 = (0 << CC1S) //!<CC1S[1:0] bits (Capture/Compare 1 Selection)
\r
535 | (0 << OC1FE) //!<Output Compare 1 Fast enable
\r
536 | (0 << OC1PE) //!<Output Compare 1 Preload enable
\r
537 | (0 << OC1M) //!<OC1M[2:0] bits (Output Compare 1 Mode)
\r
538 | (0 << OC1CE) //!<Output Compare 1Clear Enable
\r
539 | (0 << CC2S) //!<CC2S[1:0] bits (Capture/Compare 2 Selection)
\r
540 | (0 << OC2FE) //!<Output Compare 2 Fast enable
\r
541 | (0 << OC2PE) //!<Output Compare 2 Preload enable
\r
542 | (3 << OC2M) //!<OC2M[2:0] bits (Output Compare 2 Mode)
\r
543 | (0 << OC2CE); //!<Output Compare 2 Clear Enable
\r
545 // Input capture mode
\r
546 // TIM3->CCMR1 = (0 << CC1S) //!<CC1S[1:0] bits (Capture/Compare 1 Selection)
\r
547 // | (0 << IC1PSC) //!<IC1PSC[1:0] bits (Input Capture 1 Prescaler)
\r
548 // | (0 << IC1F) //!<IC1F[3:0] bits (Input Capture 1 Filter)
\r
549 // | (0 << CC2S) //!<CC2S[1:0] bits (Capture/Compare 2 Selection)
\r
550 // | (0 << IC2PSC) //!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)
\r
551 // | (0 << IC2F); //!<IC2F[3:0] bits (Input Capture 2 Filter)
\r
553 // Output compare mode
\r
554 TIM3->CCMR2 = (0 << CC3S) //!<CC3S[1:0] bits (Capture/Compare 3 Selection)
\r
555 | (0 << OC3FE) //!<Output Compare 3 Fast enable
\r
556 | (0 << OC3PE) //!<Output Compare 3 Preload enable
\r
557 | (0 << OC3M) //!<OC3M[2:0] bits (Output Compare 3 Mode)
\r
558 | (0 << OC3CE) //!<Output Compare 3Clear Enable
\r
559 | (0 << CC4S) //!<CC4S[1:0] bits (Capture/Compare 4 Selection)
\r
560 | (0 << OC4FE) //!<Output Compare 4 Fast enable
\r
561 | (0 << OC4PE) //!<Output Compare 4 Preload enable
\r
562 | (0 << OC4M) //!<OC4M[2:0] bits (Output Compare 4 Mode)
\r
563 | (0 << OC4CE); //!<Output Compare 4 Clear Enable
\r
565 // Input capture mode
\r
566 // TIM3->CCMR2 = (0 << CC3S) //!<CC3S[1:0] bits (Capture/Compare 3 Selection)
\r
567 // | (0 << IC3PSC) //!<IC3PSC[1:0] bits (Input Capture 3 Prescaler)
\r
568 // | (0 << IC3F) //!<IC3F[3:0] bits (Input Capture 3 Filter)
\r
569 // | (0 << CC4S) //!<CC4S[1:0] bits (Capture/Compare 4 Selection)
\r
570 // | (0 << IC4PSC) //!<IC4PSC[1:0] bits (Input Capture 4 Prescaler)
\r
571 // | (0 << IC4F); //!<IC4F[3:0] bits (Input Capture 4 Filter)
\r
573 TIM3->CCER = (0 << CC1E) //<Capture/Compare 1 output enable //
\r
574 | (0 << CC1P) //<Capture/Compare 1 output Polarity //
\r
575 | (0 << CC1NE) //<Capture/Compare 1 Complementary output enable //
\r
576 | (0 << CC1NP) //<Capture/Compare 1 Complementary output Polarity //
\r
577 | (1 << CC2E) //<Capture/Compare 2 output enable //
\r
578 | (0 << CC2P) //<Capture/Compare 2 output Polarity //
\r
579 | (0 << CC2NE) //<Capture/Compare 2 Complementary output enable //
\r
580 | (0 << CC2NP) //<Capture/Compare 2 Complementary output Polarity //
\r
581 | (0 << CC3E) //<Capture/Compare 3 output enable //
\r
582 | (0 << CC3P) //<Capture/Compare 3 output Polarity //
\r
583 | (0 << CC3NE) //<Capture/Compare 3 Complementary output enable //
\r
584 | (0 << CC3NP) //<Capture/Compare 3 Complementary output Polarity //
\r
585 | (0 << CC4E) //<Capture/Compare 4 output enable //
\r
586 | (0 << CC4P); //<Capture/Compare 4 output Polarity //
\r
589 TIM3->CNT = 0x0000;
\r
591 TIM3->PSC = 3600 - 1; // 0.5ms clock cycle
\r
593 TIM3->ARR = 10 - 1;
\r
597 TIM3->CCR3 = 0x0000;
\r
598 TIM3->CCR4 = 0x0000;
\r
599 TIM3->DCR = 0x0000;
\r
600 TIM3->DMAR = 0x0000;
\r
602 TIM3->CR1 = (1 << CEN) //<Counter enable //
\r
603 | (0 << UDIS) //<Update disable //
\r
604 | (0 << URS) //<Update request source //
\r
605 | (0 << OPM) //<One pulse mode //
\r
606 | (0 << DIR) //<Direction //
\r
607 | (0 << CMS) //<CMS[1:0] bits (Center-aligned mode selection) //
\r
608 | (1 << ARPE) //<Auto-reload preload enable //
\r
609 | (0 << CKD); //<CKD[1:0] bits (clock division) //
\r
613 void TIM4_Init(void)
\r
615 // Disable counter first
\r
616 TIM4->CR1 = (0 << CEN) //!<Counter enable //
\r
617 | (0 << UDIS) //!<Update disable //
\r
618 | (0 << URS) //!<Update request source //
\r
619 | (0 << OPM) //!<One pulse mode //
\r
620 | (0 << DIR) //!<Direction. 0: Up, 1: Down
\r
621 | (0 << CMS) //!<CMS[1:0] bits (Center-aligned mode selection) //
\r
622 | (1 << ARPE) //!<Auto-reload preload enable //
\r
623 | (0 << CKD); //!<CKD[1:0] bits (clock division for filtering) 0 = 1/1, 1 = 1/2, 2 = 1/4
\r
625 TIM4->CR2 = (0 << CCPC) //!<Capture/Compare Preloaded Control //
\r
626 | (0 << CCUS) //!<Capture/Compare Control Update Selection //
\r
627 | (0 << CCDS) //!<Capture/Compare DMA Selection //
\r
628 | (0 << MMS) //!<MMS[2:0] bits (Master Mode Selection) //
\r
629 | (0 << TI1S) //!<TI1 Selection //
\r
630 | (0 << OIS1) //!<Output Idle state 1 (OC1 output) //
\r
631 | (0 << OIS1N) //!<Output Idle state 1 (OC1N output) //
\r
632 | (0 << OIS2) //!<Output Idle state 2 (OC2 output) //
\r
633 | (0 << OIS2N) //!<Output Idle state 2 (OC2N output) //
\r
634 | (0 << OIS3) //!<Output Idle state 3 (OC3 output) //
\r
635 | (0 << OIS3N) //!<Output Idle state 3 (OC3N output) //
\r
636 | (0 << OIS4); //!<Output Idle state 4 (OC4 output) //
\r
638 TIM4->SMCR = (0 << SMS) //!<SMS[2:0] bits (Slave mode selection) //
\r
639 | (0 << TS) //!<TS[2:0] bits (Trigger selection) //
\r
640 | (0 << MSM) //!<Master/slave mode //
\r
641 | (0 << ETF) //!<ETF[3:0] bits (External trigger filter) //
\r
642 | (0 << ETPS) //!<ETPS[1:0] bits (External trigger prescaler) //
\r
643 | (0 << ECE) //!<External clock enable //
\r
644 | (0 << ETP); //!<External trigger polarity //
\r
648 TIM4->EGR = 0x0000;
\r
650 //----------------------------------------------------------------------------
\r
651 // TIMx capture/compare usage (x = 2 ~ 5, n = 1 ~ 4)
\r
654 // 00: CCn channel is configured as output.
\r
655 // 01: CCn channel is configured as input, ICn is mapped on TI1.
\r
656 // 10: CCn channel is configured as input, ICn is mapped on TI2.
\r
657 // 11: CCn channel is configured as input, ICn is mapped on TRC. This mode is working only
\r
658 // if an internal trigger input is selected through TS bit (TIMx_SMCR register)
\r
659 // Note: CCnS bits are writable only when the channel is OFF (CCnE = 0 in TIMx_CCER).
\r
660 // Output compare mode
\r
664 // 001: Set channel n to active level on match.
\r
665 // 010: Set channel n to inactive level on match.
\r
666 // 011: Toggle - OCnREF toggles when TIMx_CNT=TIMx_CCRn.
\r
667 // 100: Force inactive level - OCnREF is forced low.
\r
668 // 101: Force active level - OCnREF is forced high.
\r
669 // 110: PWM mode 1 - In upcounting, channel n is active as long as TIMx_CNT<TIMx_CCRn
\r
670 // else inactive. In downcounting, channel 1 is inactive (OCnREF=0) as long as
\r
671 // TIMx_CNT>TIMx_CCRn else active (OCnREF=1).
\r
672 // 111: PWM mode 2 - In upcounting, channel n is inactive as long as
\r
673 // TIMx_CNT<TIMx_CCRn else active. In downcounting, channel n is active as long as
\r
674 // TIMx_CNT>TIMx_CCRn else inactive.
\r
675 // Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed
\r
676 // (LOCK bits in TIMx_BDTR register) and CC1S=00 (the channel is configured in output).
\r
677 // 2: In PWM mode 1 or 2, the OCREF level changes only when the result of the
\r
678 // comparison changes or when the output compare mode switches from "frozen" mode
\r
682 // This bit-field defines the ratio of the prescaler acting on CCn input (ICn).
\r
683 // The prescaler is reset as soon as CC1E= 0 (TIMx_CCER register).
\r
684 // 00: no prescaler, capture is done each time an edge is detected on the capture input.
\r
685 // 01: capture is done once every 2 events.
\r
686 // 10: capture is done once every 4 events.
\r
687 // 11: capture is done once every 8 events.
\r
690 // This bit-field defines the frequency used to sample TIn input and the length of the digital
\r
691 // filter applied to TIn. The digital filter is made of an event counter in which N events are
\r
692 // needed to validate a transition on the output:
\r
693 // 0000: No filter, sampling is done at fDTS.
\r
694 // 0001: fSAMPLING=fCK_INT, N=2.
\r
695 // 0010: fSAMPLING=fCK_INT, N=4.
\r
696 // 0011: fSAMPLING=fCK_INT, N=8.
\r
697 // 0100: fSAMPLING=fDTS/2, N=6.
\r
698 // 0101: fSAMPLING=fDTS/2, N=8.
\r
699 // 0110: fSAMPLING=fDTS/4, N=6.
\r
700 // 0111: fSAMPLING=fDTS/4, N=8.
\r
701 // 1000: fSAMPLING=fDTS/8, N=6.
\r
702 // 1001: fSAMPLING=fDTS/8, N=8.
\r
703 // 1010: fSAMPLING=fDTS/16, N=5.
\r
704 // 1011: fSAMPLING=fDTS/16, N=6.
\r
705 // 1100: fSAMPLING=fDTS/16, N=8.
\r
706 // 1101: fSAMPLING=fDTS/32, N=5.
\r
707 // 1110: fSAMPLING=fDTS/32, N=6.
\r
708 // 1111: fSAMPLING=fDTS/32, N=8.
\r
709 // Note: In current silicon revision, fDTS is replaced in the formula by CK_INT
\r
710 // when ICnF[3:0]= 1, 2 or 3.
\r
712 // Output compare mode
\r
713 // CH3 for VGEN generation
\r
714 // -- Set OC3 to output mode (CC3S[1:0] = 00)
\r
715 // -- Set output to PWM mode 1 (OC3M[2:0] = 110)
\r
716 // -- Set OC4 to output mode (CC4S[1:0] = 00)
\r
717 // -- Set output to PWM mode 1 (OC4M[2:0] = 110)
\r
719 TIM4->CCMR1 = (0 << CC1S) //!<CC1S[1:0] bits (Capture/Compare 1 Selection)
\r
720 | (0 << OC1FE) //!<Output Compare 1 Fast enable
\r
721 | (0 << OC1PE) //!<Output Compare 1 Preload enable
\r
722 | (0 << OC1M) //!<OC1M[2:0] bits (Output Compare 1 Mode)
\r
723 | (0 << OC1CE) //!<Output Compare 1Clear Enable
\r
724 | (0 << CC2S) //!<CC2S[1:0] bits (Capture/Compare 2 Selection)
\r
725 | (0 << OC2FE) //!<Output Compare 2 Fast enable
\r
726 | (0 << OC2PE) //!<Output Compare 2 Preload enable
\r
727 | (0 << OC2M) //!<OC2M[2:0] bits (Output Compare 2 Mode)
\r
728 | (0 << OC2CE); //!<Output Compare 2 Clear Enable
\r
730 // Input capture mode
\r
732 TIM4->CCMR1 = (0 << CC1S) //!<CC1S[1:0] bits (Capture/Compare 1 Selection)
\r
733 | (0 << IC1PSC) //!<IC1PSC[1:0] bits (Input Capture 1 Prescaler)
\r
734 | (0 << IC1F) //!<IC1F[3:0] bits (Input Capture 1 Filter)
\r
735 | (0 << CC2S) //!<CC2S[1:0] bits (Capture/Compare 2 Selection)
\r
736 | (0 << IC2PSC) //!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)
\r
737 | (0 << IC2F); //!<IC2F[3:0] bits (Input Capture 2 Filter)
\r
740 // Output compare mode
\r
741 TIM4->CCMR2 = (0 << CC3S) //!<CC3S[1:0] bits (Capture/Compare 3 Selection)
\r
742 | (0 << OC3FE) //!<Output Compare 3 Fast enable
\r
743 | (0 << OC3PE) //!<Output Compare 3 Preload enable
\r
744 | (0x06 << OC3M) //!<OC3M[2:0] bits (Output Compare 3 Mode)
\r
745 | (0 << OC3CE) //!<Output Compare 3Clear Enable
\r
746 | (0 << CC4S) //!<CC4S[1:0] bits (Capture/Compare 4 Selection)
\r
747 | (0 << OC4FE) //!<Output Compare 4 Fast enable
\r
748 | (0 << OC4PE) //!<Output Compare 4 Preload enable
\r
749 | (0x06 << OC4M) //!<OC4M[2:0] bits (Output Compare 4 Mode)
\r
750 | (0 << OC4CE); //!<Output Compare 4 Clear Enable
\r
752 // Input capture mode
\r
754 TIM4->CCMR2 = (0 << CC3S) //!<CC3S[1:0] bits (Capture/Compare 3 Selection)
\r
755 | (0 << IC3PSC) //!<IC3PSC[1:0] bits (Input Capture 3 Prescaler)
\r
756 | (0 << IC3F) //!<IC3F[3:0] bits (Input Capture 3 Filter)
\r
757 | (0 << CC4S) //!<CC4S[1:0] bits (Capture/Compare 4 Selection)
\r
758 | (0 << IC4PSC) //!<IC4PSC[1:0] bits (Input Capture 4 Prescaler)
\r
759 | (0 << IC4F); //!<IC4F[3:0] bits (Input Capture 4 Filter)
\r
762 TIM4->CCER = (0 << CC1E) //!<Capture/Compare 1 output enable //
\r
763 | (0 << CC1P) //!<Capture/Compare 1 output Polarity //
\r
764 | (0 << CC1NE) //!<Capture/Compare 1 Complementary output enable //
\r
765 | (0 << CC1NP) //!<Capture/Compare 1 Complementary output Polarity //
\r
766 | (0 << CC2E) //!<Capture/Compare 2 output enable //
\r
767 | (0 << CC2P) //!<Capture/Compare 2 output Polarity //
\r
768 | (0 << CC2NE) //!<Capture/Compare 2 Complementary output enable //
\r
769 | (0 << CC2NP) //!<Capture/Compare 2 Complementary output Polarity //
\r
770 | (1 << CC3E) //!<Capture/Compare 3 output enable //
\r
771 | (0 << CC3P) //!<Capture/Compare 3 output Polarity //
\r
772 | (0 << CC3NE) //!<Capture/Compare 3 Complementary output enable //
\r
773 | (0 << CC3NP) //!<Capture/Compare 3 Complementary output Polarity //
\r
774 | (1 << CC4E) //!<Capture/Compare 4 output enable //
\r
775 | (0 << CC4P); //!<Capture/Compare 4 output Polarity //
\r
778 TIM4->CNT = 0x0000;
\r
780 TIM4->PSC = 1 - 1; // Make 1M (36M/36) as basic clock
\r
782 TIM4->ARR = 4096 - 1; // 1KHz
\r
784 TIM4->CCR1 = 0x0000; // This value must be set to smaller than ARR. Otherwise there is no
\r
785 // compare match and no output generated at pin.
\r
786 TIM4->CCR2 = 0x0000;
\r
787 TIM4->CCR3 = 0x800 - 1;
\r
788 TIM4->CCR4 = 0x400 - 1;
\r
789 TIM4->DCR = 0x0000;
\r
790 TIM4->DMAR = 0x0000;
\r
792 TIM4->DIER = (0 << UIE) //!<Update interrupt enable //
\r
793 | (0 << CC1IE) //!<Capture/Compare 1 interrupt enable //
\r
794 | (0 << CC2IE) //!<Capture/Compare 2 interrupt enable //
\r
795 | (0 << CC3IE) //!<Capture/Compare 3 interrupt enable //
\r
796 | (0 << CC4IE) //!<Capture/Compare 4 interrupt enable //
\r
797 | (0 << COMIE) //!<COM interrupt enable //
\r
798 | (0 << TIE) //!<Trigger interrupt enable //
\r
799 | (0 << BIE) //!<Break interrupt enable //
\r
800 | (0 << UDE) //!<Update DMA request enable //
\r
801 | (0 << CC1DE) //!<Capture/Compare 1 DMA request enable //
\r
802 | (0 << CC2DE) //!<Capture/Compare 2 DMA request enable //
\r
803 | (0 << CC3DE) //!<Capture/Compare 3 DMA request enable //
\r
804 | (0 << CC4DE) //!<Capture/Compare 4 DMA request enable //
\r
805 | (0 << COMDE) //!<COM DMA request enable //
\r
806 | (0 << TDE); //!<Trigger DMA request enable //
\r
808 TIM4->CR1 = (1 << CEN) //!<Counter enable //
\r
809 | (0 << UDIS) //!<Update disable //
\r
810 | (0 << URS) //!<Update request source //
\r
811 | (0 << OPM) //!<One pulse mode //
\r
812 | (0 << DIR) //!<Direction //
\r
813 | (0 << CMS) //!<CMS[1:0] bits (Center-aligned mode selection) //
\r
814 | (1 << ARPE) //!<Auto-reload preload enable //
\r
815 | (0 << CKD); //!<CKD[1:0] bits (clock division) //
\r
820 void SysTick_Init(void)
\r
822 SysTick->VAL = 0; // Write this register will clear itself and the settings in
\r
825 SysTick->CTRL = (1 << SysTick_ENABLE)
\r
826 | (1 << SysTick_TICKINT) // Counting down to 0 pends the SysTick handler
\r
827 | (1 << SysTick_CLKSOURCE) // Clock source. 0 = HCLK/8; 1 = HCLK
\r
828 | (0 << SysTick_COUNTFLAG); // Count Flag
\r
830 SysTick->LOAD = 72000;
\r
833 // This register is read-only. When clock source is set to HCLK/8 (CLKSOURCE bit is 0) the
\r
834 // TENMS value in this register will be used to generate 1ms tick.
\r
840 void ADC2_Init(void)
\r
842 // NOTE: Remember to program ADC clock in RCC->CFGR
\r
844 ADC2->SR = (0 << AWD) /*!<Analog watchdog flag */
\r
845 | (0 << EOC) /*!<End of conversion */
\r
846 | (0 << JEOC) /*!<Injected channel end of conversion */
\r
847 | (0 << JSTRT) /*!<Injected channel Start flag */
\r
848 | (0 << STRT); /*!<Regular channel Start flag */
\r
850 ADC2->CR1 = (0 << AWDCH) /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
\r
851 | (0 << EOCIE) /*!<Interrupt enable for EOC */
\r
852 | (0 << AWDIE) /*!<AAnalog Watchdog interrupt enable */
\r
853 | (0 << JEOCIE) /*!<Interrupt enable for injected channels */
\r
854 | (0 << SCAN ) /*!<Scan mode */
\r
855 | (0 << AWDSGL) /*!<Enable the watchdog on a single channel in scan mode */
\r
856 | (0 << JAUTO) /*!<Automatic injected group conversion */
\r
857 | (0 << DISCEN) /*!<Discontinuous mode on regular channels */
\r
858 | (0 << JDISCEN) /*!<Discontinuous mode on injected channels */
\r
859 | (0 << DISCNUM ) /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
\r
860 | (0 << DUALMOD) /*!<DUALMOD[3:0] bits (Dual mode selection) */
\r
861 | (0 << JAWDEN ) /*!<Analog watchdog enable on injected channels */
\r
862 | (0 << AWDEN); /*!<Analog watchdog enable on regular channels */
\r
864 ADC2->CR2 = (0 << ADON) // /*!<A/D Converter ON / OFF */
\r
865 | (0 << CONT) // /*!<Continuous Conversion */
\r
866 | (0 << CAL) // /*!<A/D Calibration */
\r
867 | (0 << RSTCAL) // /*!<Reset Calibration */
\r
868 | (0 << DMA) // /*!<Direct Memory access mode */
\r
869 // 0: DMA mode disabled
\r
870 // 1: DMA mode enabled
\r
871 | (0 << ALIGN) // /*!<Data Alignment */
\r
872 | (0 << JEXTSEL) // /*!<JEXTSEL[2:0] bits (External event select for injected group) */
\r
873 | (0 << JEXTTRIG) // /*!<External Trigger Conversion mode for injected channels */
\r
874 | (0 << EXTSEL) // /*!<EXTSEL[2:0] bits (External Event Select for regular group) */
\r
875 // For ADC2 and ADC2, the assigned triggers are:
\r
876 // 000: Timer 1 CC1 event
\r
877 // 001: Timer 1 CC2 event
\r
878 // 010: Timer 1 CC3 event
\r
879 // 011: Timer 2 CC2 event
\r
880 // 100: Timer 3 TRGO event
\r
881 // 101: Timer 4 CC4 event
\r
882 // 110: EXTI line11/TIM8_TRGO event (TIM8_TRGO is available only in high-density devices)
\r
884 | (0 << EXTTRIG) // /*!<External Trigger Conversion mode for regular channels */
\r
885 | (0 << JSWSTART) // /*!<Start Conversion of injected channels */
\r
886 | (0 << SWSTART) // /*!<Start Conversion of regular channels */
\r
887 | (0 << TSVREFE); // /*!<Temperature Sensor and VREFINT Enable */
\r
889 // Sample time selection
\r
893 // 010: 13.5 cycles
\r
894 // 011: 28.5 cycles
\r
895 // 100: 41.5 cycles
\r
896 // 101: 55.5 cycles
\r
897 // 110: 71.5 cycles
\r
898 // 111: 239.5 cycles
\r
899 ADC2->SMPR1 = (0 << SMP10) // /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
\r
900 | (0 << SMP11) // /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
\r
901 | (0 << SMP12) // /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
\r
902 | (0 << SMP13) // /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
\r
903 | (0 << SMP14) // /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
\r
904 | (0 << SMP15) // /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
\r
905 | (0 << SMP16) // /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
\r
906 | (0 << SMP17); // /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
\r
908 ADC2->SMPR2 = (0 << SMP0 ) // /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
\r
909 | (0 << SMP1) // /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
\r
910 | (0 << SMP2) // /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
\r
911 | (0 << SMP3) // /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
\r
912 | (0 << SMP4 ) // /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
\r
913 | (0 << SMP5) // /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
\r
914 | (0 << SMP6) // /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
\r
915 | (0 << SMP7) // /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
\r
916 | (0 << SMP8) // /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
\r
917 | (0 << SMP9); // /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
\r
919 ADC2->JOFR1 = 0x0000;
\r
920 ADC2->JOFR2 = 0x0000;
\r
921 ADC2->JOFR3 = 0x0000;
\r
922 ADC2->JOFR4 = 0x0000;
\r
924 ADC2->HTR = 0x0FFF;
\r
925 ADC2->LTR = 0x0000;
\r
927 // L[3:0]: Regular channel sequence length, i.e. number of channels in the sequence.
\r
928 // These bits are written by software to define the total number of conversions in the regular
\r
929 // channel conversion sequence.
\r
930 // 0000: 1 conversion
\r
931 // 0001: 2 conversions
\r
933 // 1111: 16 conversions
\r
934 // SQn[4:0]: The order of conversion in regular sequence
\r
935 // These bits are written by software with the channel number (0..17) assigned as the n-th conversion in the
\r
936 // sequence to be converted.
\r
938 ADC2->SQR1 = (0 << SQ13 ) // /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
\r
939 | (0 << SQ14) // /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
\r
940 | (0 << SQ15) // /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
\r
941 | (0 << SQ16) // /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
\r
942 | (0 << L ); // /*!<L[3:0] bits (Regular channel sequence length) */
\r
944 ADC2->SQR2 = (0 << SQ7) // /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
\r
945 | (0 << SQ8) // /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
\r
946 | (0 << SQ9) // /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
\r
947 | (0 << SQ10) // /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
\r
948 | (0 << SQ11) // /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
\r
949 | (0 << SQ12); // /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
\r
951 ADC2->SQR3 = (0 << SQ1) // /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
\r
952 | (0 << SQ2) // /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
\r
953 | (0 << SQ3) // /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
\r
954 | (0 << SQ4) // /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
\r
955 | (0 << SQ5) // /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
\r
956 | (0 << SQ6); // /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
\r
958 // JL[1:0]: Injected sequence length
\r
959 // These bits are written by software to define the total number of conversions in the injected
\r
960 // channel conversion sequence.
\r
961 // 00: 1 conversion
\r
962 // 01: 2 conversions
\r
963 // 10: 3 conversions
\r
964 // 11: 4 conversions
\r
965 // JSQ4[4:0]: 4th conversion in injected sequence
\r
966 // These bits are written by software with the channel number (0..17) assigned as the 4th in
\r
967 // the sequence to be converted.
\r
968 // Note: Unlike a regular conversion sequence, if JL[1:0] length is less than four, the channels
\r
969 // are converted in a sequence starting from (4-JL). Example: ADC_JSQR[21:0] = 10
\r
970 // 00011 00011 00111 00010 means that a scan conversion will convert the following
\r
971 // channel sequence: 7, 3, 3. (not 2, 7, 3)
\r
973 ADC2->JSQR = (0 << JSQ1) // /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
\r
974 | (0 << JSQ2) // /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
\r
975 | (0 << JSQ3) // /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
\r
976 | (0 << JSQ4) // /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
\r
977 | (0 << JL); // /*!<JL[1:0] bits (Injected Sequence length) */
\r
979 // These registers are read-only
\r
987 ADC2->CR2 |= (1 << CAL);
\r
988 while(!BitTest(ADC2->CR2, (1 << CAL))) {
\r
989 // Wait for end of calibration
\r
992 // Start ADC (the first ADON set turn on ADC power)
\r
993 ADC2->CR2 |= (1 << ADON); // /*!<A/D Converter ON / OFF */
\r
997 U16 ADC_Poll(ADC_TypeDef * adc, U8 chn)
\r
999 // Assuming that the ADC refered has been properly initialized with channel and sample time selected.
\r
1000 adc->SQR3 = (chn << SQ1); // /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
\r
1002 // Start conversion
\r
1003 adc->CR2 |= (1 << ADON);
\r
1004 while(!BitTest(adc->SR, (1 << EOC))) {
\r
1005 // Wait for end of conversion
\r
1010 void TFT_Init_Ili9341(void)
\r
1014 // Reset TFT controller (Ili9341)
\r
1015 SetToHigh(TFT_nRESET_Port, (1 << TFT_nRESET_Bit));
\r
1016 Delay(5000); // About 1.1ms
\r
1017 SetToLow(TFT_nRESET_Port, (1 << TFT_nRESET_Bit));
\r
1018 Delay(65000); // About 15ms
\r
1019 SetToHigh(TFT_nRESET_Port, (1 << TFT_nRESET_Bit));
\r
1026 write_comm(0xcf);
\r
1031 write_comm(0xed);
\r
1037 write_comm(0xcb);
\r
1044 write_comm(0xea);
\r
1048 write_comm(0xe8);
\r
1053 write_comm(0xF7);
\r
1056 write_comm(0xC0); //Power control
\r
1057 write_data(0x26); //VRH[5:0]
\r
1059 write_comm(0xC1); //Power control
\r
1060 write_data(0x01); //SAP[2:0];BT[3:0]
\r
1062 write_comm(0xC5); //VCM control
\r
1066 write_comm(0xc7);
\r
1069 write_comm(0x3A);
\r
1072 write_comm(0x36); // Memory Access Control
\r
1073 // write_data(0x08);
\r
1076 write_comm(0xB1); // Frame Rate Control
\r
1080 write_comm(0xB6); // Display Function Control
\r
1084 write_comm(0xF2); // 3Gamma Function Disable
\r
1086 write_comm(0x26); //Gamma curve selected
\r
1088 write_comm(0xE0); //Set Gamma
\r
1105 write_comm(0XE1); //Set Gamma
\r
1122 write_comm(0x11); //Exit Sleep
\r
1129 write_comm(0x29); //display on
\r
1130 // write_comm(0x2C);
\r
1138 void write_comm(U8 commport)
\r
1140 // Set TFT_nCS low
\r
1141 SetToLow(TFT_nCS_Port, (1 << TFT_nCS_Bit));
\r
1142 // Set up to access Index Register (RS == 0)
\r
1143 SetToLow(TFT_RS_Port, (1 << TFT_RS_Bit));
\r
1146 TFT_Port = (TFT_Port & 0xFF00) | commport;
\r
1147 SetToLow(TFT_nWR_Port, (1 << TFT_nWR_Bit));
\r
1148 SetToHigh(TFT_nWR_Port, (1 << TFT_nWR_Bit));
\r
1150 // Set up to access Data Register (RS == 1)
\r
1151 SetToHigh(TFT_RS_Port, (1 << TFT_RS_Bit));
\r
1154 // Set TFT_nCS high
\r
1155 SetToHigh(TFT_nCS_Port, (1 << TFT_nCS_Bit));
\r
1159 void write_data(U8 data)
\r
1161 // Set TFT_nCS low
\r
1162 SetToLow(TFT_nCS_Port, (1 << TFT_nCS_Bit));
\r
1164 // Set up to access Data Register (RS == 1)
\r
1165 SetToHigh(TFT_RS_Port, (1 << TFT_RS_Bit));
\r
1167 TFT_Port = (TFT_Port & 0xFF00) | data;
\r
1168 SetToLow(TFT_nWR_Port, (1 << TFT_nWR_Bit));
\r
1169 SetToHigh(TFT_nWR_Port, (1 << TFT_nWR_Bit));
\r
1171 // Set TFT_nCS high
\r
1172 SetToHigh(TFT_nCS_Port, (1 << TFT_nCS_Bit));
\r
1177 void assert_failed(U8 * file, U32 line)
\r
1178 //void assert_failed((U8 *) file, U32 line)
\r
1184 * @brief Configures the nested vectored interrupt controller.
\r
1188 void NVIC_Configuration(void)
\r
1190 NVIC_InitTypeDef NVIC_InitStructure;
\r
1192 // NVIC_SetVectorTable(NVIC_VectTab_RAM, 0);
\r
1193 NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0);
\r
1196 // Enable the TIM1 Interrupt
\r
1197 NVIC_InitStructure.NVIC_IRQChannel = TIM1_CC_IRQn;
\r
1198 NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
\r
1199 NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
\r
1200 NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
\r
1201 NVIC_Init(&NVIC_InitStructure);
\r
1204 // Enable the ADC1 Interrupt
\r
1205 NVIC_InitStructure.NVIC_IRQChannel = ADC1_2_IRQn;
\r
1206 NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
\r
1207 NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
\r
1208 NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
\r
1209 NVIC_Init(&NVIC_InitStructure);
\r
1211 // Enable the DMA1 channel1 Interrupt
\r
1212 NVIC_InitStructure.NVIC_IRQChannel = DMA1_Channel1_IRQn;
\r
1213 NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
\r
1214 NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
\r
1215 NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
\r
1216 NVIC_Init(&NVIC_InitStructure);
\r
1221 void OutputTLvl(void)
\r
1223 TIM4->CCR3 = GetTrigLvl() + GetVPosOfs() + 0x800;
\r
projects / DSO138 / blob