1 //////////////////////////////////////////////////////////////////////////////
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8 // Company: JYE Tech Ltd.
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9 // Web: www.jyetech.com
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11 //-----------------------------------------------------------------------------
13 // Target: STM32F103C8
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14 // Tool chain: CodeSourcery G++
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16 //-----------------------------------------------------------------------------
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19 //-----------------------------------------------------------------------------
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23 //-----------------------------------------------------------------------------
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24 // Revision History:
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26 ///////////////////////////////////////////////////////////////////////////////
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36 #include "stm32f10x.h"
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37 //#include "stm32f10x_conf.h"
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39 // TFT control ports
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41 #define TFT_nRESET_Port GPIOB
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42 #define TFT_nRESET_Bit 11
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43 #define TFT_RS_Port GPIOC
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44 #define TFT_RS_Bit 14
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45 #define TFT_nCS_Port GPIOC
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46 #define TFT_nCS_Bit 13
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47 #define TFT_nWR_Port GPIOC
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48 #define TFT_nWR_Bit 15
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49 #define TFT_nRD_Port GPIOB
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50 #define TFT_nRD_Bit 10
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52 #define TFT_Port (GPIOB->ODR)
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54 #define LED_Base GPIOA
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55 #define LED_Port (GPIOA->ODR)
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59 #define PB_Port (GPIOB->IDR)
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60 #define PB_Bits 0xF000
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63 // ======== STM32 Register Constants =====================
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65 // -------- Register address -----------------
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67 #define RCC_AHBENR (*((unsigned int *)(0x40021014)))
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68 #define RCC_APB2ENR (*((unsigned int *)(0x40021018)))
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69 #define RCC_APB1ENR (*((unsigned int *)(0x4002101C)))
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72 #define GPIOA_CRL (*((unsigned int *)(0x40010800)))
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73 #define GPIOA_BSRR (*((unsigned int *)(0x40010810)))
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74 #define GPIOA_BRR (*((unsigned int *)(0x40010814)))
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76 #define GPIOB_CRL (*((unsigned int *)(0x40010C00)))
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77 #define GPIOB_CRH (*((unsigned int *)(0x40010C04)))
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78 #define GPIOB_IDR (*((unsigned int *)(0x40010C08)))
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79 #define GPIOB_ODR (*((unsigned int *)(0x40010C0C)))
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80 #define GPIOB_BSRR (*((unsigned int *)(0x40010C10)))
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81 #define GPIOB_BRR (*((unsigned int *)(0x40010C14)))
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82 #define GPIOB_LCKR (*((unsigned int *)(0x40010C18)))
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84 #define GPIOD_CRL (*((unsigned int *)(0x40011400)))
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85 #define GPIOD_CRH (*((unsigned int *)(0x40011404)))
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86 #define GPIOD_IDR (*((unsigned int *)(0x40011408)))
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87 #define GPIOD_ODR (*((unsigned int *)(0x4001140C)))
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88 #define GPIOD_BSRR (*((unsigned int *)(0x40011410)))
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89 #define GPIOD_BRR (*((unsigned int *)(0x40011414)))
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90 #define GPIOD_LCKR (*((unsigned int *)(0x40011418)))
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92 #define GPIOE_CRL (*((unsigned int *)(0x40011800)))
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93 #define GPIOE_CRH (*((unsigned int *)(0x40011804)))
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94 #define GPIOE_IDR (*((unsigned int *)(0x40011808)))
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95 #define GPIOE_ODR (*((unsigned int *)(0x4001180C)))
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96 #define GPIOE_BSRR (*((unsigned int *)(0x40011810)))
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97 #define GPIOE_BRR (*((unsigned int *)(0x40011814)))
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98 #define GPIOE_LCKR (*((unsigned int *)(0x40011818)))
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101 #define FSMC_BCR1 (*((U32 *)(0xA0000000)))
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102 #define FSMC_BTR1 (*((U32 *)(0xA0000004)))
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103 #define FSMC_BWTR1 (*((U32 *)(0xA0000104)))
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105 #define FSMC_BCR2 (*((U32 *)(0xA0000008)))
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106 #define FSMC_BTR2 (*((U32 *)(0xA000000C)))
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107 #define FSMC_BWTR2 (*((U32 *)(0xA000010C)))
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109 // ---------------- Bit fields ------------------------
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130 #define USART3EN 18
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131 #define USART2EN 17
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145 #define USART1EN 14
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161 // ---------------- Bit fields ------------------------
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164 /******************** Bit definition for RCC_CR register ********************/
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165 #define HSION 0 /*!< Internal High Speed clock enable */
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166 #define HSIRDY 1 /*!< Internal High Speed clock ready flag */
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167 #define HSITRIM 3 /*!< Internal High Speed clock trimming */
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168 #define HSICAL 8 /*!< Internal High Speed clock Calibration */
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169 #define HSEON 16 /*!< External High Speed clock enable */
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170 #define HSERDY 17 /*!< External High Speed clock ready flag */
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171 #define HSEBYP 18 /*!< External High Speed clock Bypass */
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172 #define CSSON 19 /*!< Clock Security System enable */
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173 #define PLLON 24 /*!< PLL enable */
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174 #define PLLRDY 25 /*!< PLL clock ready flag */
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176 /******************* Bit definition for RCC_CFGR register *******************/
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177 /*!< SW configuration */
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178 #define SW 0 /*!< SW[1:0] bits (System clock Switch) */
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180 /*!< SWS configuration */
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181 #define SWS 2 /*!< SWS[1:0] bits (System Clock Switch Status) */
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183 /*!< HPRE configuration */
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184 #define HPRE 4 /*!< HPRE[3:0] bits (AHB prescaler) */
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186 /*!< PPRE1 configuration */
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187 #define PPRE1 8 /*!< PRE1[2:0] bits (APB1 prescaler) */
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189 /*!< PPRE2 configuration */
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190 #define PPRE2 11 /*!< PRE2[2:0] bits (APB2 prescaler) */
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192 /*!< ADCPPRE configuration */
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193 #define ADCPRE 14 /*!< ADCPRE[1:0] bits (ADC prescaler) */
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195 #define PLLSRC 16 /*!< PLL entry clock source */
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197 #define PLLXTPRE 17 /*!< HSE divider for PLL entry */
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199 /*!< PLLMUL configuration */
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200 #define PLLMULL 18 /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
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202 #define USBPRE 22 /*!< USB Device prescaler */
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204 /*!< MCO configuration */
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205 #define MCO 24 /*!< MCO[2:0] bits (Microcontroller Clock Output) */
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207 /*!<****************** Bit definition for RCC_CIR register ********************/
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208 #define LSIRDYF 0 /*!< LSI Ready Interrupt flag */
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209 #define LSERDYF 1 /*!< LSE Ready Interrupt flag */
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210 #define HSIRDYF 2 /*!< HSI Ready Interrupt flag */
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211 #define HSERDYF 3 /*!< HSE Ready Interrupt flag */
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212 #define PLLRDYF 4 /*!< PLL Ready Interrupt flag */
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213 #define CSSF 7 /*!< Clock Security System Interrupt flag */
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214 #define LSIRDYIE 8 /*!< LSI Ready Interrupt Enable */
\r
215 #define LSERDYIE 9 /*!< LSE Ready Interrupt Enable */
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216 #define HSIRDYIE 10 /*!< HSI Ready Interrupt Enable */
\r
217 #define HSERDYIE 11 /*!< HSE Ready Interrupt Enable */
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218 #define PLLRDYIE 12 /*!< PLL Ready Interrupt Enable */
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219 #define LSIRDYC 16 /*!< LSI Ready Interrupt Clear */
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220 #define LSERDYC 17 /*!< LSE Ready Interrupt Clear */
\r
221 #define HSIRDYC 18 /*!< HSI Ready Interrupt Clear */
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222 #define HSERDYC 19 /*!< HSE Ready Interrupt Clear */
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223 #define PLLRDYC 20 /*!< PLL Ready Interrupt Clear */
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224 #define CSSC 23 /*!< Clock Security System Interrupt Clear */
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226 /***************** Bit definition for RCC_APB2RSTR register *****************/
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227 #define AFIORST 0 /*!< Alternate Function I/O reset */
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228 #define IOPARST 2 /*!< I/O port A reset */
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229 #define IOPBRST 3 /*!< I/O port B reset */
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230 #define IOPCRST 4 /*!< I/O port C reset */
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231 #define IOPDRST 5 /*!< I/O port D reset */
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232 #define IOPERST 6 /*!< I/O port E reset */
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233 #define IOPFRST 7 /*!< I/O port F reset */
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234 #define IOPGRST 8 /*!< I/O port G reset */
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235 #define ADC1RST 9 /*!< ADC 1 interface reset */
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236 #define ADC2RST 10 /*!< ADC 2 interface reset */
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237 #define TIM1RST 11 /*!< TIM1 Timer reset */
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238 #define SPI1RST 12 /*!< SPI 1 reset */
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239 #define TIM8RST 13 /*!< TIM8 Timer reset */
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240 #define USART1RST 14 /*!< USART1 reset */
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241 #define ADC3RST 15 /*!< ADC3 interface reset */
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243 /***************** Bit definition for RCC_APB1RSTR register *****************/
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244 #define TIM2RST 0 /*!< Timer 2 reset */
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245 #define TIM3RST 1 /*!< Timer 3 reset */
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246 #define TIM4RST 2 /*!< Timer 4 reset */
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247 #define TIM5RST 3 /*!< Timer 5 reset */
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248 #define TIM6RST 4 /*!< Timer 6 reset */
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249 #define TIM7RST 5 /*!< Timer 7 reset */
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250 #define WWDGRST 11 /*!< Window Watchdog reset */
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251 #define SPI2RST 14 /*!< SPI 2 reset */
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252 #define SPI3RST 15 /*!< SPI 3 reset */
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253 #define USART2RST 17 /*!< USART 2 reset */
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254 #define USART3RST 18 /*!< RUSART 3 reset */
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255 #define UART4RST 19 /*!< UART 4 reset */
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256 #define UART5RST 20 /*!< UART 5 reset */
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257 #define I2C1RST 21 /*!< I2C 1 reset */
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258 #define I2C2RST 22 /*!< I2C 2 reset */
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259 #define USBRST 23 /*!< USB Device reset */
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260 #define CAN1RST 25 /*!< CAN1 reset */
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261 #define BKPRST 27 /*!< Backup interface reset */
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262 #define PWRRST 28 /*!< Power interface reset */
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263 #define DACRST 29 /*!< DAC interface reset */
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265 /****************** Bit definition for RCC_AHBENR register ******************/
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266 #define DMA1EN 0 /*!< DMA1 clock enable */
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267 #define DMA2EN 1 /*!< DMA2 clock enable */
\r
268 #define SRAMEN 2 /*!< SRAM interface clock enable */
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269 #define FLITFEN 4 /*!< FLITF clock enable */
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270 #define CRCEN 6 /*!< CRC clock enable */
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271 #define FSMCEN 8 /*!< FSMC clock enable */
\r
272 #define SDIOEN 10 /*!< SDIO clock enable */
\r
274 /****************** Bit definition for RCC_APB2ENR register *****************/
\r
275 #define AFIOEN 0 /*!< Alternate Function I/O clock enable */
\r
276 #define IOPAEN 2 /*!< I/O port A clock enable */
\r
277 #define IOPBEN 3 /*!< I/O port B clock enable */
\r
278 #define IOPCEN 4 /*!< I/O port C clock enable */
\r
279 #define IOPDEN 5 /*!< I/O port D clock enable */
\r
280 #define IOPEEN 6 /*!< I/O port E clock enable */
\r
281 #define IOPFEN 7 /*!< I/O port F clock enable */
\r
282 #define IOPGEN 8 /*!< I/O port G clock enable */
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283 #define ADC1EN 9 /*!< ADC 1 interface clock enable */
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284 #define ADC2EN 10 /*!< ADC 2 interface clock enable */
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285 #define TIM1EN 11 /*!< TIM1 Timer clock enable */
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286 #define SPI1EN 12 /*!< SPI 1 clock enable */
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287 #define TIM8EN 13 /*!< TIM8 Timer clock enable */
\r
288 #define USART1EN 14 /*!< USART1 clock enable */
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289 #define ADC3EN 15 /*!< DMA1 clock enable */
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291 /***************** Bit definition for RCC_APB1ENR register ******************/
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292 #define TIM2EN 0 /*!< Timer 2 clock enabled*/
\r
293 #define TIM3EN 1 /*!< Timer 3 clock enable */
\r
294 #define TIM4EN 2 /*!< Timer 4 clock enable */
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295 #define TIM5EN 3 /*!< Timer 5 clock enable */
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296 #define TIM6EN 4 /*!< Timer 6 clock enable */
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297 #define TIM7EN 5 /*!< Timer 7 clock enable */
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298 #define WWDGEN 11 /*!< Window Watchdog clock enable */
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299 #define SPI2EN 14 /*!< SPI 2 clock enable */
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300 #define SPI3EN 15 /*!< SPI 3 clock enable */
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301 #define USART2EN 17 /*!< USART 2 clock enable */
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302 #define USART3EN 18 /*!< USART 3 clock enable */
\r
303 #define UART4EN 19 /*!< UART 4 clock enable */
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304 #define UART5EN 20 /*!< UART 5 clock enable */
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305 #define I2C1EN 21 /*!< I2C 1 clock enable */
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306 #define I2C2EN 22 /*!< I2C 2 clock enable */
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307 #define USBEN 23 /*!< USB Device clock enable */
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308 #define CAN1EN 25 /*!< CAN1 clock enable */
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309 #define BKPEN 27 /*!< Backup interface clock enable */
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310 #define PWREN 28 /*!< Power interface clock enable */
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311 #define DACEN 29 /*!< DAC interface clock enable */
\r
314 /******************* Bit definition for RCC_BDCR register *******************/
\r
315 #define LSEON 0 /*!< External Low Speed oscillator enable */
\r
316 #define LSERDY 1 /*!< External Low Speed oscillator Ready */
\r
317 #define LSEBYP 2 /*!< External Low Speed oscillator Bypass */
\r
319 #define RTCSEL 8 /*!< RTCSEL[1:0] bits (RTC clock source selection) */
\r
321 #define RTCEN 15 /*!< RTC clock enable */
\r
322 #define BDRST 16 /*!< Backup domain software reset */
\r
324 /******************* Bit definition for RCC_CSR register ********************/
\r
325 #define LSION 0 /*!< Internal Low Speed oscillator enable */
\r
326 #define LSIRDY 1 /*!< Internal Low Speed oscillator Ready */
\r
327 #define RMVF 24 /*!< Remove reset flag */
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328 #define PINRSTF 26 /*!< PIN reset flag */
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329 #define PORRSTF 27 /*!< POR/PDR reset flag */
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330 #define SFTRSTF 28 /*!< Software Reset flag */
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331 #define IWDGRSTF 29 /*!< Independent Watchdog reset flag */
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332 #define WWDGRSTF 30 /*!< Window watchdog reset flag */
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333 #define LPWRRSTF 31 /*!< Low-Power reset flag */
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335 /******************************************************************************/
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339 /******************************************************************************/
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341 /******************* Bit definition for TIM_CR1 register ********************/
\r
342 #define CEN 0 /*!<Counter enable */
\r
343 #define UDIS 1 /*!<Update disable */
\r
344 #define URS 2 /*!<Update request source */
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345 #define OPM 3 /*!<One pulse mode */
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346 #define DIR 4 /*!<Direction */
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348 #define CMS 5 /*!<CMS[1:0] bits (Center-aligned mode selection) */
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350 #define ARPE 7 /*!<Auto-reload preload enable */
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352 #define CKD 8 /*!<CKD[1:0] bits (clock division) */
\r
354 /******************* Bit definition for TIM_CR2 register ********************/
\r
355 #define CCPC 0 /*!<Capture/Compare Preloaded Control */
\r
356 #define CCUS 2 /*!<Capture/Compare Control Update Selection */
\r
357 #define CCDS 3 /*!<Capture/Compare DMA Selection */
\r
359 #define MMS 4 /*!<MMS[2:0] bits (Master Mode Selection) */
\r
361 #define TI1S 7 /*!<TI1 Selection */
\r
362 #define OIS1 8 /*!<Output Idle state 1 (OC1 output) */
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363 #define OIS1N 9 /*!<Output Idle state 1 (OC1N output) */
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364 #define OIS2 10 /*!<Output Idle state 2 (OC2 output) */
\r
365 #define OIS2N 11 /*!<Output Idle state 2 (OC2N output) */
\r
366 #define OIS3 12 /*!<Output Idle state 3 (OC3 output) */
\r
367 #define OIS3N 13 /*!<Output Idle state 3 (OC3N output) */
\r
368 #define OIS4 14 /*!<Output Idle state 4 (OC4 output) */
\r
370 /******************* Bit definition for TIM_SMCR register *******************/
\r
371 #define SMS 0 /*!<SMS[2:0] bits (Slave mode selection) */
\r
373 #define TS 4 /*!<TS[2:0] bits (Trigger selection) */
\r
375 #define MSM 7 /*!<Master/slave mode */
\r
377 #define ETF 8 /*!<ETF[3:0] bits (External trigger filter) */
\r
379 #define ETPS 12 /*!<ETPS[1:0] bits (External trigger prescaler) */
\r
381 #define ECE 14 /*!<External clock enable */
\r
382 #define ETP 15 /*!<External trigger polarity */
\r
384 /******************* Bit definition for TIM_DIER register *******************/
\r
385 #define UIE 0 /*!<Update interrupt enable */
\r
386 #define CC1IE 1 /*!<Capture/Compare 1 interrupt enable */
\r
387 #define CC2IE 2 /*!<Capture/Compare 2 interrupt enable */
\r
388 #define CC3IE 3 /*!<Capture/Compare 3 interrupt enable */
\r
389 #define CC4IE 4 /*!<Capture/Compare 4 interrupt enable */
\r
390 #define COMIE 5 /*!<COM interrupt enable */
\r
391 #define TIE 6 /*!<Trigger interrupt enable */
\r
392 #define BIE 7 /*!<Break interrupt enable */
\r
393 #define UDE 8 /*!<Update DMA request enable */
\r
394 #define CC1DE 9 /*!<Capture/Compare 1 DMA request enable */
\r
395 #define CC2DE 10 /*!<Capture/Compare 2 DMA request enable */
\r
396 #define CC3DE 11 /*!<Capture/Compare 3 DMA request enable */
\r
397 #define CC4DE 12 /*!<Capture/Compare 4 DMA request enable */
\r
398 #define COMDE 13 /*!<COM DMA request enable */
\r
399 #define TDE 14 /*!<Trigger DMA request enable */
\r
401 /******************** Bit definition for TIM_SR register ********************/
\r
402 #define UIF 0 /*!<Update interrupt Flag */
\r
403 #define CC1IF 1 /*!<Capture/Compare 1 interrupt Flag */
\r
404 #define CC2IF 2 /*!<Capture/Compare 2 interrupt Flag */
\r
405 #define CC3IF 3 /*!<Capture/Compare 3 interrupt Flag */
\r
406 #define CC4IF 4 /*!<Capture/Compare 4 interrupt Flag */
\r
407 #define COMIF 5 /*!<COM interrupt Flag */
\r
408 #define TIF 6 /*!<Trigger interrupt Flag */
\r
409 #define BIF 7 /*!<Break interrupt Flag */
\r
410 #define CC1OF 9 /*!<Capture/Compare 1 Overcapture Flag */
\r
411 #define CC2OF 10 /*!<Capture/Compare 2 Overcapture Flag */
\r
412 #define CC3OF 11 /*!<Capture/Compare 3 Overcapture Flag */
\r
413 #define CC4OF 12 /*!<Capture/Compare 4 Overcapture Flag */
\r
415 /******************* Bit definition for TIM_EGR register ********************/
\r
416 #define UG 0 /*!<Update Generation */
\r
417 #define CC1G 1 /*!<Capture/Compare 1 Generation */
\r
418 #define CC2G 2 /*!<Capture/Compare 2 Generation */
\r
419 #define CC3G 3 /*!<Capture/Compare 3 Generation */
\r
420 #define CC4G 4 /*!<Capture/Compare 4 Generation */
\r
421 #define COMG 5 /*!<Capture/Compare Control Update Generation */
\r
422 #define TG 6 /*!<Trigger Generation */
\r
423 #define BG 7 /*!<Break Generation */
\r
425 /****************** Bit definition for TIM_CCMR1 register *******************/
\r
426 #define CC1S 0 /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
\r
428 #define OC1FE 2 /*!<Output Compare 1 Fast enable */
\r
429 #define OC1PE 3 /*!<Output Compare 1 Preload enable */
\r
431 #define OC1M 4 /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
\r
433 #define OC1CE 7 /*!<Output Compare 1Clear Enable */
\r
435 #define CC2S 8 /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
\r
437 #define OC2FE 10 /*!<Output Compare 2 Fast enable */
\r
438 #define OC2PE 11 /*!<Output Compare 2 Preload enable */
\r
440 #define OC2M 12 /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
\r
442 #define OC2CE 15 /*!<Output Compare 2 Clear Enable */
\r
444 /*----------------------------------------------------------------------------*/
\r
446 #define IC1PSC 2 /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
\r
448 #define IC1F 4 /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
\r
450 #define IC2PSC 10 /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
\r
452 #define IC2F 12 /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
\r
454 /****************** Bit definition for TIM_CCMR2 register *******************/
\r
455 #define CC3S 0 /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
\r
457 #define OC3FE 2 /*!<Output Compare 3 Fast enable */
\r
458 #define OC3PE 3 /*!<Output Compare 3 Preload enable */
\r
460 #define OC3M 4 /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
\r
462 #define OC3CE 7 /*!<Output Compare 3 Clear Enable */
\r
464 #define CC4S 8 /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
\r
466 #define OC4FE 10 /*!<Output Compare 4 Fast enable */
\r
467 #define OC4PE 11 /*!<Output Compare 4 Preload enable */
\r
469 #define OC4M 12 /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
\r
471 #define OC4CE 15 /*!<Output Compare 4 Clear Enable */
\r
473 /*----------------------------------------------------------------------------*/
\r
475 #define IC3PSC 2 /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
\r
477 #define IC3F 4 /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
\r
479 #define IC4PSC 10 /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
\r
481 #define IC4F 12 /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
\r
483 /******************* Bit definition for TIM_CCER register *******************/
\r
484 #define CC1E 0 /*!<Capture/Compare 1 output enable */
\r
485 #define CC1P 1 /*!<Capture/Compare 1 output Polarity */
\r
486 #define CC1NE 2 /*!<Capture/Compare 1 Complementary output enable */
\r
487 #define CC1NP 3 /*!<Capture/Compare 1 Complementary output Polarity */
\r
488 #define CC2E 4 /*!<Capture/Compare 2 output enable */
\r
489 #define CC2P 5 /*!<Capture/Compare 2 output Polarity */
\r
490 #define CC2NE 6 /*!<Capture/Compare 2 Complementary output enable */
\r
491 #define CC2NP 7 /*!<Capture/Compare 2 Complementary output Polarity */
\r
492 #define CC3E 8 /*!<Capture/Compare 3 output enable */
\r
493 #define CC3P 9 /*!<Capture/Compare 3 output Polarity */
\r
494 #define CC3NE 10 /*!<Capture/Compare 3 Complementary output enable */
\r
495 #define CC3NP 11 /*!<Capture/Compare 3 Complementary output Polarity */
\r
496 #define CC4E 12 /*!<Capture/Compare 4 output enable */
\r
497 #define CC4P 13 /*!<Capture/Compare 4 output Polarity */
\r
499 /******************* Bit definition for TIM_BDTR register *******************/
\r
500 #define DTG 0 /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
\r
502 #define LOCK 8 /*!<LOCK[1:0] bits (Lock Configuration) */
\r
504 #define OSSI 10 /*!<Off-State Selection for Idle mode */
\r
505 #define OSSR 11 /*!<Off-State Selection for Run mode */
\r
506 #define BKE 12 /*!<Break enable */
\r
507 //#define BKP 13 /*!<Break Polarity */
\r
508 #define AOE 14 /*!<Automatic Output enable */
\r
509 #define MOE 15 /*!<Main Output enable */
\r
511 /******************* Bit definition for TIM_DCR register ********************/
\r
512 #define DBA 0 /*!<DBA[4:0] bits (DMA Base Address) */
\r
514 #define DBL 8 /*!<DBL[4:0] bits (DMA Burst Length) */
\r
516 /******************* Bit definition for TIM_DMAR register *******************/
\r
517 #define DMAB 0 /*!<DMA register for burst accesses */
\r
519 /******************************************************************************/
\r
523 /******************************************************************************/
\r
525 /***************** Bit definition for SysTick_CTRL register *****************/
\r
526 #define SysTick_ENABLE 0 // ((uint32_t)0x00000001) /*!< Counter enable */
\r
527 #define SysTick_TICKINT 1 // ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */
\r
528 #define SysTick_CLKSOURCE 2 // ((uint32_t)0x00000004) /*!< Clock source */
\r
529 #define SysTick_COUNTFLAG 16 // ((uint32_t)0x00010000) /*!< Count Flag */
\r
531 /***************** Bit definition for SysTick_LOAD register *****************/
\r
532 #define SysTick_RELOAD 0 // ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
\r
534 /***************** Bit definition for SysTick_VAL register ******************/
\r
535 #define SysTick_CURRENT 0 // ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */
\r
537 /***************** Bit definition for SysTick_CALIB register ****************/
\r
538 #define SysTick_TENMS 0 // ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */
\r
539 #define SysTick_SKEW 30 // ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */
\r
540 #define SysTick_NOREF 31 // ((uint32_t)0x80000000) /*!< The reference clock is not provided */
\r
542 // GPIO port configuration constants
\r
543 #define GPIO_Mode_In 0x00
\r
544 #define GPIO_Mode_Out10M 0x01
\r
545 #define GPIO_Mode_Out2M 0x02
\r
546 #define GPIO_Mode_Out50M 0x03
\r
548 #define GPIO_CNF_GP_PP 0x00
\r
549 #define GPIO_CNF_GP_OD 0x04
\r
550 #define GPIO_CNF_AF_PP 0x08
\r
551 #define GPIO_CNF_AF_OD 0x0C
\r
552 #define GPIO_CNF_AnalogIn 0x00
\r
553 #define GPIO_CNF_Floating 0x04
\r
554 #define GPIO_CNF_IPD 0x08
\r
555 #define GPIO_CNF_IPU 0x08
\r
557 /****************** Bit definition for FSMC_BCR registers *******************/
\r
558 #define CBURSTRW 16 /*!<Write burst enable */
\r
559 #define EXTMOD 14 /*!<Extended mode enable */
\r
560 #define WAITEN 13 /*!<Wait enable bit */
\r
561 #define WREN 12 /*!<Write enable bit */
\r
562 #define WAITCFG 11 /*!<Wait timing configuration */
\r
563 #define WRAPMOD 10 /*!<Wrapped burst mode support */
\r
564 #define WAITPOL 9 /*!<Wait signal polarity bit */
\r
565 #define BURSTEN 8 /*!<Burst enable bit */
\r
566 #define FACCEN 6 /*!<Flash access enable */
\r
567 #define MWID 4 /*!<MWID[1:0] bits (Memory data bus width) */
\r
568 #define MTYP 2 /*!<MTYP[1:0] bits (Memory type) */
\r
569 #define MUXEN 1 /*!<Address/data multiplexing enable bit */
\r
570 #define MBKEN 0 /*!<Memory bank enable bit */
\r
572 /****************** Bit definition for FSMC_BTR and FSMC_BWTR registers ******************/
\r
573 #define ACCMOD 28 /*!<ACCMOD[1:0] bits (Access mode) */
\r
574 #define DATLAT 24 /*!<DATLA[3:0] bits (Data latency) */
\r
575 #define CLKDIV 20 /*!<CLKDIV[3:0] bits (Clock divide ratio) */
\r
576 #define BUSTURN 16 /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
\r
577 #define DATAST 8 /*!<DATAST [3:0] bits (Data-phase duration) */
\r
578 #define ADDHLD 4 /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
\r
579 #define ADDSET 0 /*!<ADDSET[3:0] bits (Address setup phase duration) */
\r
581 /******************************************************************************/
\r
583 /* Analog to Digital Converter */
\r
585 /******************************************************************************/
\r
587 /******************** Bit definition for ADC_SR register ********************/
\r
588 #define AWD 0 /*!<Analog watchdog flag */
\r
589 #define EOC 1 /*!<End of conversion */
\r
590 #define JEOC 2 /*!<Injected channel end of conversion */
\r
591 #define JSTRT 3 /*!<Injected channel Start flag */
\r
592 #define STRT 4 /*!<Regular channel Start flag */
\r
594 /******************* Bit definition for ADC_CR1 register ********************/
\r
595 #define AWDCH 0 /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
\r
596 #define EOCIE 5 /*!<Interrupt enable for EOC */
\r
597 #define AWDIE 6 /*!<AAnalog Watchdog interrupt enable */
\r
598 #define JEOCIE 7 /*!<Interrupt enable for injected channels */
\r
599 #define SCAN 8 /*!<Scan mode */
\r
600 #define AWDSGL 9 /*!<Enable the watchdog on a single channel in scan mode */
\r
601 #define JAUTO 10 /*!<Automatic injected group conversion */
\r
602 #define DISCEN 11 /*!<Discontinuous mode on regular channels */
\r
603 #define JDISCEN 12 /*!<Discontinuous mode on injected channels */
\r
604 #define DISCNUM 13 /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
\r
605 #define DUALMOD 16 /*!<DUALMOD[3:0] bits (Dual mode selection) */
\r
606 #define JAWDEN 22 /*!<Analog watchdog enable on injected channels */
\r
607 #define AWDEN 23 /*!<Analog watchdog enable on regular channels */
\r
610 /******************* Bit definition for ADC_CR2 register ********************/
\r
611 #define ADON 0 // ((uint32_t)0x00000001) /*!<A/D Converter ON / OFF */
\r
612 #define CONT 1 // ((uint32_t)0x00000002) /*!<Continuous Conversion */
\r
613 #define CAL 2 // ((uint32_t)0x00000004) /*!<A/D Calibration */
\r
614 #define RSTCAL 3 // ((uint32_t)0x00000008) /*!<Reset Calibration */
\r
615 #define DMA 8 // ((uint32_t)0x00000100) /*!<Direct Memory access mode */
\r
616 #define ALIGN 11 // ((uint32_t)0x00000800) /*!<Data Alignment */
\r
617 #define JEXTSEL 12 // ((uint32_t)0x00007000) /*!<JEXTSEL[2:0] bits (External event select for injected group) */
\r
618 #define JEXTTRIG 15 // ((uint32_t)0x00008000) /*!<External Trigger Conversion mode for injected channels */
\r
619 #define EXTSEL 17 // ((uint32_t)0x000E0000) /*!<EXTSEL[2:0] bits (External Event Select for regular group) */
\r
620 #define EXTTRIG 20 // ((uint32_t)0x00100000) /*!<External Trigger Conversion mode for regular channels */
\r
621 #define JSWSTART 21 // ((uint32_t)0x00200000) /*!<Start Conversion of injected channels */
\r
622 #define SWSTART 22 // ((uint32_t)0x00400000) /*!<Start Conversion of regular channels */
\r
623 #define TSVREFE 23 // ((uint32_t)0x00800000) /*!<Temperature Sensor and VREFINT Enable */
\r
625 /****************** Bit definition for ADC_SMPR1 register *******************/
\r
626 #define SMP10 0 // ((uint32_t)0x00000007) /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
\r
627 #define SMP11 3 // ((uint32_t)0x00000038) /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
\r
628 #define SMP12 6 // ((uint32_t)0x000001C0) /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
\r
629 #define SMP13 9 // ((uint32_t)0x00000E00) /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
\r
630 #define SMP14 12 // ((uint32_t)0x00007000) /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
\r
631 #define SMP15 15 // ((uint32_t)0x00038000) /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
\r
632 #define SMP16 18 // ((uint32_t)0x001C0000) /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
\r
633 #define SMP17 21 // ((uint32_t)0x00E00000) /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
\r
635 /****************** Bit definition for ADC_SMPR2 register *******************/
\r
636 #define SMP0 0 // ((uint32_t)0x00000007) /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
\r
637 #define SMP1 3 // ((uint32_t)0x00000038) /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
\r
638 #define SMP2 6 // ((uint32_t)0x000001C0) /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
\r
639 #define SMP3 9 // ((uint32_t)0x00000E00) /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
\r
640 #define SMP4 12 // ((uint32_t)0x00007000) /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
\r
641 #define SMP5 15 // ((uint32_t)0x00038000) /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
\r
642 #define SMP6 18 // ((uint32_t)0x001C0000) /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
\r
643 #define SMP7 21 // ((uint32_t)0x00E00000) /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
\r
644 #define SMP8 24 // ((uint32_t)0x07000000) /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
\r
645 #define SMP9 27 // ((uint32_t)0x38000000) /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
\r
647 /****************** Bit definition for ADC_JOFR1 register *******************/
\r
648 #define ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 1 */
\r
650 /****************** Bit definition for ADC_JOFR2 register *******************/
\r
651 #define ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 2 */
\r
653 /****************** Bit definition for ADC_JOFR3 register *******************/
\r
654 #define ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 3 */
\r
656 /****************** Bit definition for ADC_JOFR4 register *******************/
\r
657 #define ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 4 */
\r
659 /******************* Bit definition for ADC_HTR register ********************/
\r
660 #define ADC_HTR_HT ((uint16_t)0x0FFF) /*!<Analog watchdog high threshold */
\r
662 /******************* Bit definition for ADC_LTR register ********************/
\r
663 #define ADC_LTR_LT ((uint16_t)0x0FFF) /*!<Analog watchdog low threshold */
\r
665 /******************* Bit definition for ADC_SQR1 register *******************/
\r
666 #define SQ13 0 // ((uint32_t)0x0000001F) /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
\r
667 #define SQ14 5 // ((uint32_t)0x000003E0) /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
\r
668 #define SQ15 10 // ((uint32_t)0x00007C00) /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
\r
669 #define SQ16 15 // ((uint32_t)0x000F8000) /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
\r
670 #define L 20 // ((uint32_t)0x00F00000) /*!<L[3:0] bits (Regular channel sequence length) */
\r
672 /******************* Bit definition for ADC_SQR2 register *******************/
\r
673 #define SQ7 0 // ((uint32_t)0x0000001F) /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
\r
674 #define SQ8 5 // ((uint32_t)0x000003E0) /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
\r
675 #define SQ9 10 // ((uint32_t)0x00007C00) /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
\r
676 #define SQ10 15 // ((uint32_t)0x000F8000) /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
\r
677 #define SQ11 20 // ((uint32_t)0x01F00000) /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
\r
678 #define SQ12 25 // ((uint32_t)0x3E000000) /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
\r
680 /******************* Bit definition for ADC_SQR3 register *******************/
\r
681 #define SQ1 0 // ((uint32_t)0x0000001F) /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
\r
682 #define SQ2 5 // ((uint32_t)0x000003E0) /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
\r
683 #define SQ3 10 // ((uint32_t)0x00007C00) /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
\r
684 #define SQ4 15 // ((uint32_t)0x000F8000) /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
\r
685 #define SQ5 20 // ((uint32_t)0x01F00000) /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
\r
686 #define SQ6 25 // ((uint32_t)0x3E000000) /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
\r
688 /******************* Bit definition for ADC_JSQR register *******************/
\r
689 #define JSQ1 0 // ((uint32_t)0x0000001F) /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
\r
690 #define JSQ2 5 // ((uint32_t)0x000003E0) /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
\r
691 #define JSQ3 10 // ((uint32_t)0x00007C00) /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
\r
692 #define JSQ4 15 // ((uint32_t)0x000F8000) /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
\r
693 #define JL 20 // ((uint32_t)0x00300000) /*!<JL[1:0] bits (Injected Sequence length) */
\r
695 /******************* Bit definition for ADC_JDR1 register *******************/
\r
696 #define ADC_JDR1_JDATA ((uint16_t)0xFFFF) /*!<Injected data */
\r
698 /******************* Bit definition for ADC_JDR2 register *******************/
\r
699 #define ADC_JDR2_JDATA ((uint16_t)0xFFFF) /*!<Injected data */
\r
701 /******************* Bit definition for ADC_JDR3 register *******************/
\r
702 #define ADC_JDR3_JDATA ((uint16_t)0xFFFF) /*!<Injected data */
\r
704 /******************* Bit definition for ADC_JDR4 register *******************/
\r
705 #define ADC_JDR4_JDATA ((uint16_t)0xFFFF) /*!<Injected data */
\r
707 /******************** Bit definition for ADC_DR register ********************/
\r
708 #define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!<Regular data */
\r
709 #define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!<ADC2 data */
\r
711 /******************* Bit definition for DMA_IFCR register *******************/
\r
712 #define CGIF1 0 // /*!< Channel 1 Global interrupt clearr */
\r
713 #define CTCIF1 1 // /*!< Channel 1 Transfer Complete clear */
\r
714 #define CHTIF1 2 // /*!< Channel 1 Half Transfer clear */
\r
715 #define CTEIF1 3 // /*!< Channel 1 Transfer Error clear */
\r
716 #define CGIF2 4 // /*!< Channel 2 Global interrupt clear */
\r
717 #define CTCIF2 5 // /*!< Channel 2 Transfer Complete clear */
\r
718 #define CHTIF2 6 // /*!< Channel 2 Half Transfer clear */
\r
719 #define CTEIF2 7 // /*!< Channel 2 Transfer Error clear */
\r
720 #define CGIF3 8 // /*!< Channel 3 Global interrupt clear */
\r
721 #define CTCIF3 9 // /*!< Channel 3 Transfer Complete clear */
\r
722 #define CHTIF3 10 // /*!< Channel 3 Half Transfer clear */
\r
723 #define CTEIF3 11 // /*!< Channel 3 Transfer Error clear */
\r
724 #define CGIF4 12 // /*!< Channel 4 Global interrupt clear */
\r
725 #define CTCIF4 13 // /*!< Channel 4 Transfer Complete clear */
\r
726 #define CHTIF4 14 // /*!< Channel 4 Half Transfer clear */
\r
727 #define CTEIF4 15 // /*!< Channel 4 Transfer Error clear */
\r
728 #define CGIF5 16 // /*!< Channel 5 Global interrupt clear */
\r
729 #define CTCIF5 17 // /*!< Channel 5 Transfer Complete clear */
\r
730 #define CHTIF5 18 // /*!< Channel 5 Half Transfer clear */
\r
731 #define CTEIF5 19 // /*!< Channel 5 Transfer Error clear */
\r
732 #define CGIF6 20 // /*!< Channel 6 Global interrupt clear */
\r
733 #define CTCIF6 21 // /*!< Channel 6 Transfer Complete clear */
\r
734 #define CHTIF6 22 // /*!< Channel 6 Half Transfer clear */
\r
735 #define CTEIF6 23 // /*!< Channel 6 Transfer Error clear */
\r
736 #define CGIF7 24 // /*!< Channel 7 Global interrupt clear */
\r
737 #define CTCIF7 25 // /*!< Channel 7 Transfer Complete clear */
\r
738 #define CHTIF7 26 // /*!< Channel 7 Half Transfer clear */
\r
739 #define CTEIF7 27 // /*!< Channel 7 Transfer Error clear */
\r
741 /******************* Bit definition for DMA_CCRx register *******************/
\r
742 #define EN 0 // /*!< Channel enable*/
\r
743 #define TCIE 1 // /*!< Transfer complete interrupt enable */
\r
744 #define HTIE 2 // /*!< Half Transfer interrupt enable */
\r
745 #define TEIE 3 // /*!< Transfer error interrupt enable */
\r
746 #define DIR 4 // /*!< Data transfer direction */
\r
747 // 0: Read from peripheral
\r
748 // 1: Read from memory
\r
749 #define CIRC 5 // /*!< Circular mode */
\r
750 // 0: Circular mode disabled
\r
751 // 1: Circular mode enabled
\r
752 #define PINC 6 // /*!< Peripheral increment mode */
\r
753 // 0: Peripheral increment mode disabled
\r
754 // 1: Peripheral increment mode enabled
\r
755 #define MINC 7 // /*!< Memory increment mode */
\r
756 // 0: Memory increment mode disabled
\r
757 // 1: Memory increment mode enabled
\r
758 #define PSIZE 8 // /*!< PSIZE[1:0] bits (Peripheral size) */
\r
763 #define MSIZE 10 // /*!< MSIZE[1:0] bits (Memory size) */
\r
768 #define PL 12 // /*!< PL[1:0] bits(Channel Priority level) */
\r
773 #define MEM2MEM 14 // /*!< Memory to memory mode */
\r
777 extern U8 GTimeout;
\r
779 extern U16 TimerKeyScan;
\r
780 extern U8 GeneralBuf[];
\r
782 // ====================================================
\r
786 // ====================================================
\r
787 // Function Prototype Declarations
\r
789 void Clock_Init(void);
\r
790 void Port_Init(void);
\r
791 void USART1_Init(void);
\r
792 void UartPutc(U8 ch, USART_TypeDef* USARTx);
\r
793 void uputs(U8 *s, USART_TypeDef* USARTx);
\r
794 void ADC2_Init(void);
\r
795 U16 ADC_Poll(ADC_TypeDef * adc, U8 chn);
\r
796 void TIM3_Init(void);
\r
797 void TIM4_Init(void);
\r
798 void SysTick_Init(void);
\r
799 void TFT_Init_Ili9341(void);
\r
800 void write_comm(U8 commport);
\r
801 void write_data(U8 data);
\r
802 void assert_failed(U8 * file, U32 line);
\r
803 void NVIC_Configuration(void);
\r
804 void OutputTLvl(void);
\r
projects / DSO138 / blob