2 ******************************************************************************
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3 * @file stm32f10x_rcc.h
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4 * @author MCD Application Team
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7 * @brief This file contains all the functions prototypes for the RCC firmware
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9 ******************************************************************************
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12 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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13 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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14 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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15 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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16 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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17 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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19 * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
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22 /* Define to prevent recursive inclusion -------------------------------------*/
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23 #ifndef __STM32F10x_RCC_H
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24 #define __STM32F10x_RCC_H
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30 /* Includes ------------------------------------------------------------------*/
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31 #include "stm32f10x.h"
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33 /** @addtogroup STM32F10x_StdPeriph_Driver
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41 /** @defgroup RCC_Exported_Types
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47 uint32_t SYSCLK_Frequency; /*!< returns SYSCLK clock frequency expressed in Hz */
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48 uint32_t HCLK_Frequency; /*!< returns HCLK clock frequency expressed in Hz */
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49 uint32_t PCLK1_Frequency; /*!< returns PCLK1 clock frequency expressed in Hz */
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50 uint32_t PCLK2_Frequency; /*!< returns PCLK2 clock frequency expressed in Hz */
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51 uint32_t ADCCLK_Frequency; /*!< returns ADCCLK clock frequency expressed in Hz */
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58 /** @defgroup RCC_Exported_Constants
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62 /** @defgroup HSE_configuration
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66 #define RCC_HSE_OFF ((uint32_t)0x00000000)
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67 #define RCC_HSE_ON ((uint32_t)0x00010000)
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68 #define RCC_HSE_Bypass ((uint32_t)0x00040000)
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69 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
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70 ((HSE) == RCC_HSE_Bypass))
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76 /** @defgroup PLL_entry_clock_source
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80 #define RCC_PLLSource_HSI_Div2 ((uint32_t)0x00000000)
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82 #if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_CL)
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83 #define RCC_PLLSource_HSE_Div1 ((uint32_t)0x00010000)
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84 #define RCC_PLLSource_HSE_Div2 ((uint32_t)0x00030000)
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85 #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \
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86 ((SOURCE) == RCC_PLLSource_HSE_Div1) || \
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87 ((SOURCE) == RCC_PLLSource_HSE_Div2))
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89 #define RCC_PLLSource_PREDIV1 ((uint32_t)0x00010000)
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90 #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \
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91 ((SOURCE) == RCC_PLLSource_PREDIV1))
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92 #endif /* STM32F10X_CL */
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98 /** @defgroup PLL_multiplication_factor
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101 #ifndef STM32F10X_CL
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102 #define RCC_PLLMul_2 ((uint32_t)0x00000000)
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103 #define RCC_PLLMul_3 ((uint32_t)0x00040000)
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104 #define RCC_PLLMul_4 ((uint32_t)0x00080000)
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105 #define RCC_PLLMul_5 ((uint32_t)0x000C0000)
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106 #define RCC_PLLMul_6 ((uint32_t)0x00100000)
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107 #define RCC_PLLMul_7 ((uint32_t)0x00140000)
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108 #define RCC_PLLMul_8 ((uint32_t)0x00180000)
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109 #define RCC_PLLMul_9 ((uint32_t)0x001C0000)
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110 #define RCC_PLLMul_10 ((uint32_t)0x00200000)
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111 #define RCC_PLLMul_11 ((uint32_t)0x00240000)
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112 #define RCC_PLLMul_12 ((uint32_t)0x00280000)
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113 #define RCC_PLLMul_13 ((uint32_t)0x002C0000)
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114 #define RCC_PLLMul_14 ((uint32_t)0x00300000)
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115 #define RCC_PLLMul_15 ((uint32_t)0x00340000)
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116 #define RCC_PLLMul_16 ((uint32_t)0x00380000)
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117 #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \
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118 ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \
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119 ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \
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120 ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \
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121 ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \
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122 ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \
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123 ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \
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124 ((MUL) == RCC_PLLMul_16))
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127 #define RCC_PLLMul_4 ((uint32_t)0x00080000)
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128 #define RCC_PLLMul_5 ((uint32_t)0x000C0000)
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129 #define RCC_PLLMul_6 ((uint32_t)0x00100000)
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130 #define RCC_PLLMul_7 ((uint32_t)0x00140000)
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131 #define RCC_PLLMul_8 ((uint32_t)0x00180000)
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132 #define RCC_PLLMul_9 ((uint32_t)0x001C0000)
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133 #define RCC_PLLMul_6_5 ((uint32_t)0x00340000)
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135 #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \
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136 ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \
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137 ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \
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138 ((MUL) == RCC_PLLMul_6_5))
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139 #endif /* STM32F10X_CL */
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144 /** @defgroup PREDIV1_division_factor
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147 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_CL)
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148 #define RCC_PREDIV1_Div1 ((uint32_t)0x00000000)
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149 #define RCC_PREDIV1_Div2 ((uint32_t)0x00000001)
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150 #define RCC_PREDIV1_Div3 ((uint32_t)0x00000002)
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151 #define RCC_PREDIV1_Div4 ((uint32_t)0x00000003)
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152 #define RCC_PREDIV1_Div5 ((uint32_t)0x00000004)
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153 #define RCC_PREDIV1_Div6 ((uint32_t)0x00000005)
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154 #define RCC_PREDIV1_Div7 ((uint32_t)0x00000006)
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155 #define RCC_PREDIV1_Div8 ((uint32_t)0x00000007)
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156 #define RCC_PREDIV1_Div9 ((uint32_t)0x00000008)
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157 #define RCC_PREDIV1_Div10 ((uint32_t)0x00000009)
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158 #define RCC_PREDIV1_Div11 ((uint32_t)0x0000000A)
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159 #define RCC_PREDIV1_Div12 ((uint32_t)0x0000000B)
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160 #define RCC_PREDIV1_Div13 ((uint32_t)0x0000000C)
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161 #define RCC_PREDIV1_Div14 ((uint32_t)0x0000000D)
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162 #define RCC_PREDIV1_Div15 ((uint32_t)0x0000000E)
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163 #define RCC_PREDIV1_Div16 ((uint32_t)0x0000000F)
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165 #define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \
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166 ((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \
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167 ((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \
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168 ((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \
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169 ((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \
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170 ((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \
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171 ((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \
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172 ((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16))
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179 /** @defgroup PREDIV1_clock_source
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182 #ifdef STM32F10X_CL
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183 /* PREDIV1 clock source (for STM32 connectivity line devices) */
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184 #define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000)
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185 #define RCC_PREDIV1_Source_PLL2 ((uint32_t)0x00010000)
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187 #define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE) || \
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188 ((SOURCE) == RCC_PREDIV1_Source_PLL2))
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189 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL)
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190 /* PREDIV1 clock source (for STM32 Value line devices) */
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191 #define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000)
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193 #define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE))
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199 #ifdef STM32F10X_CL
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200 /** @defgroup PREDIV2_division_factor
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204 #define RCC_PREDIV2_Div1 ((uint32_t)0x00000000)
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205 #define RCC_PREDIV2_Div2 ((uint32_t)0x00000010)
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206 #define RCC_PREDIV2_Div3 ((uint32_t)0x00000020)
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207 #define RCC_PREDIV2_Div4 ((uint32_t)0x00000030)
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208 #define RCC_PREDIV2_Div5 ((uint32_t)0x00000040)
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209 #define RCC_PREDIV2_Div6 ((uint32_t)0x00000050)
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210 #define RCC_PREDIV2_Div7 ((uint32_t)0x00000060)
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211 #define RCC_PREDIV2_Div8 ((uint32_t)0x00000070)
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212 #define RCC_PREDIV2_Div9 ((uint32_t)0x00000080)
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213 #define RCC_PREDIV2_Div10 ((uint32_t)0x00000090)
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214 #define RCC_PREDIV2_Div11 ((uint32_t)0x000000A0)
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215 #define RCC_PREDIV2_Div12 ((uint32_t)0x000000B0)
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216 #define RCC_PREDIV2_Div13 ((uint32_t)0x000000C0)
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217 #define RCC_PREDIV2_Div14 ((uint32_t)0x000000D0)
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218 #define RCC_PREDIV2_Div15 ((uint32_t)0x000000E0)
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219 #define RCC_PREDIV2_Div16 ((uint32_t)0x000000F0)
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221 #define IS_RCC_PREDIV2(PREDIV2) (((PREDIV2) == RCC_PREDIV2_Div1) || ((PREDIV2) == RCC_PREDIV2_Div2) || \
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222 ((PREDIV2) == RCC_PREDIV2_Div3) || ((PREDIV2) == RCC_PREDIV2_Div4) || \
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223 ((PREDIV2) == RCC_PREDIV2_Div5) || ((PREDIV2) == RCC_PREDIV2_Div6) || \
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224 ((PREDIV2) == RCC_PREDIV2_Div7) || ((PREDIV2) == RCC_PREDIV2_Div8) || \
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225 ((PREDIV2) == RCC_PREDIV2_Div9) || ((PREDIV2) == RCC_PREDIV2_Div10) || \
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226 ((PREDIV2) == RCC_PREDIV2_Div11) || ((PREDIV2) == RCC_PREDIV2_Div12) || \
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227 ((PREDIV2) == RCC_PREDIV2_Div13) || ((PREDIV2) == RCC_PREDIV2_Div14) || \
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228 ((PREDIV2) == RCC_PREDIV2_Div15) || ((PREDIV2) == RCC_PREDIV2_Div16))
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234 /** @defgroup PLL2_multiplication_factor
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238 #define RCC_PLL2Mul_8 ((uint32_t)0x00000600)
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239 #define RCC_PLL2Mul_9 ((uint32_t)0x00000700)
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240 #define RCC_PLL2Mul_10 ((uint32_t)0x00000800)
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241 #define RCC_PLL2Mul_11 ((uint32_t)0x00000900)
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242 #define RCC_PLL2Mul_12 ((uint32_t)0x00000A00)
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243 #define RCC_PLL2Mul_13 ((uint32_t)0x00000B00)
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244 #define RCC_PLL2Mul_14 ((uint32_t)0x00000C00)
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245 #define RCC_PLL2Mul_16 ((uint32_t)0x00000E00)
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246 #define RCC_PLL2Mul_20 ((uint32_t)0x00000F00)
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248 #define IS_RCC_PLL2_MUL(MUL) (((MUL) == RCC_PLL2Mul_8) || ((MUL) == RCC_PLL2Mul_9) || \
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249 ((MUL) == RCC_PLL2Mul_10) || ((MUL) == RCC_PLL2Mul_11) || \
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250 ((MUL) == RCC_PLL2Mul_12) || ((MUL) == RCC_PLL2Mul_13) || \
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251 ((MUL) == RCC_PLL2Mul_14) || ((MUL) == RCC_PLL2Mul_16) || \
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252 ((MUL) == RCC_PLL2Mul_20))
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258 /** @defgroup PLL3_multiplication_factor
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262 #define RCC_PLL3Mul_8 ((uint32_t)0x00006000)
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263 #define RCC_PLL3Mul_9 ((uint32_t)0x00007000)
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264 #define RCC_PLL3Mul_10 ((uint32_t)0x00008000)
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265 #define RCC_PLL3Mul_11 ((uint32_t)0x00009000)
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266 #define RCC_PLL3Mul_12 ((uint32_t)0x0000A000)
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267 #define RCC_PLL3Mul_13 ((uint32_t)0x0000B000)
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268 #define RCC_PLL3Mul_14 ((uint32_t)0x0000C000)
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269 #define RCC_PLL3Mul_16 ((uint32_t)0x0000E000)
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270 #define RCC_PLL3Mul_20 ((uint32_t)0x0000F000)
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272 #define IS_RCC_PLL3_MUL(MUL) (((MUL) == RCC_PLL3Mul_8) || ((MUL) == RCC_PLL3Mul_9) || \
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273 ((MUL) == RCC_PLL3Mul_10) || ((MUL) == RCC_PLL3Mul_11) || \
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274 ((MUL) == RCC_PLL3Mul_12) || ((MUL) == RCC_PLL3Mul_13) || \
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275 ((MUL) == RCC_PLL3Mul_14) || ((MUL) == RCC_PLL3Mul_16) || \
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276 ((MUL) == RCC_PLL3Mul_20))
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281 #endif /* STM32F10X_CL */
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284 /** @defgroup System_clock_source
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288 #define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)
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289 #define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)
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290 #define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002)
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291 #define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
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292 ((SOURCE) == RCC_SYSCLKSource_HSE) || \
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293 ((SOURCE) == RCC_SYSCLKSource_PLLCLK))
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298 /** @defgroup AHB_clock_source
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302 #define RCC_SYSCLK_Div1 ((uint32_t)0x00000000)
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303 #define RCC_SYSCLK_Div2 ((uint32_t)0x00000080)
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304 #define RCC_SYSCLK_Div4 ((uint32_t)0x00000090)
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305 #define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0)
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306 #define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0)
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307 #define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0)
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308 #define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0)
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309 #define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0)
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310 #define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0)
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311 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
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312 ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
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313 ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
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314 ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
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315 ((HCLK) == RCC_SYSCLK_Div512))
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320 /** @defgroup APB1_APB2_clock_source
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324 #define RCC_HCLK_Div1 ((uint32_t)0x00000000)
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325 #define RCC_HCLK_Div2 ((uint32_t)0x00000400)
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326 #define RCC_HCLK_Div4 ((uint32_t)0x00000500)
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327 #define RCC_HCLK_Div8 ((uint32_t)0x00000600)
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328 #define RCC_HCLK_Div16 ((uint32_t)0x00000700)
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329 #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
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330 ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
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331 ((PCLK) == RCC_HCLK_Div16))
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336 /** @defgroup RCC_Interrupt_source
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340 #define RCC_IT_LSIRDY ((uint8_t)0x01)
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341 #define RCC_IT_LSERDY ((uint8_t)0x02)
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342 #define RCC_IT_HSIRDY ((uint8_t)0x04)
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343 #define RCC_IT_HSERDY ((uint8_t)0x08)
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344 #define RCC_IT_PLLRDY ((uint8_t)0x10)
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345 #define RCC_IT_CSS ((uint8_t)0x80)
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347 #ifndef STM32F10X_CL
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348 #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xE0) == 0x00) && ((IT) != 0x00))
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349 #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
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350 ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
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351 ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS))
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352 #define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x60) == 0x00) && ((IT) != 0x00))
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354 #define RCC_IT_PLL2RDY ((uint8_t)0x20)
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355 #define RCC_IT_PLL3RDY ((uint8_t)0x40)
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356 #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00))
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357 #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
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358 ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
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359 ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \
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360 ((IT) == RCC_IT_PLL2RDY) || ((IT) == RCC_IT_PLL3RDY))
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361 #define IS_RCC_CLEAR_IT(IT) ((IT) != 0x00)
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362 #endif /* STM32F10X_CL */
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369 #ifndef STM32F10X_CL
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370 /** @defgroup USB_Device_clock_source
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374 #define RCC_USBCLKSource_PLLCLK_1Div5 ((uint8_t)0x00)
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375 #define RCC_USBCLKSource_PLLCLK_Div1 ((uint8_t)0x01)
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377 #define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \
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378 ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1))
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383 /** @defgroup USB_OTG_FS_clock_source
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386 #define RCC_OTGFSCLKSource_PLLVCO_Div3 ((uint8_t)0x00)
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387 #define RCC_OTGFSCLKSource_PLLVCO_Div2 ((uint8_t)0x01)
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389 #define IS_RCC_OTGFSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div3) || \
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390 ((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div2))
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394 #endif /* STM32F10X_CL */
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397 #ifdef STM32F10X_CL
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398 /** @defgroup I2S2_clock_source
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401 #define RCC_I2S2CLKSource_SYSCLK ((uint8_t)0x00)
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402 #define RCC_I2S2CLKSource_PLL3_VCO ((uint8_t)0x01)
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404 #define IS_RCC_I2S2CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_SYSCLK) || \
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405 ((SOURCE) == RCC_I2S2CLKSource_PLL3_VCO))
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410 /** @defgroup I2S3_clock_source
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413 #define RCC_I2S3CLKSource_SYSCLK ((uint8_t)0x00)
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414 #define RCC_I2S3CLKSource_PLL3_VCO ((uint8_t)0x01)
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416 #define IS_RCC_I2S3CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S3CLKSource_SYSCLK) || \
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417 ((SOURCE) == RCC_I2S3CLKSource_PLL3_VCO))
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421 #endif /* STM32F10X_CL */
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424 /** @defgroup ADC_clock_source
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428 #define RCC_PCLK2_Div2 ((uint32_t)0x00000000)
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429 #define RCC_PCLK2_Div4 ((uint32_t)0x00004000)
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430 #define RCC_PCLK2_Div6 ((uint32_t)0x00008000)
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431 #define RCC_PCLK2_Div8 ((uint32_t)0x0000C000)
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432 #define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_PCLK2_Div2) || ((ADCCLK) == RCC_PCLK2_Div4) || \
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433 ((ADCCLK) == RCC_PCLK2_Div6) || ((ADCCLK) == RCC_PCLK2_Div8))
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438 /** @defgroup LSE_configuration
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442 #define RCC_LSE_OFF ((uint8_t)0x00)
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443 #define RCC_LSE_ON ((uint8_t)0x01)
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444 #define RCC_LSE_Bypass ((uint8_t)0x04)
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445 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
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446 ((LSE) == RCC_LSE_Bypass))
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451 /** @defgroup RTC_clock_source
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455 #define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100)
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456 #define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200)
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457 #define RCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300)
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458 #define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
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459 ((SOURCE) == RCC_RTCCLKSource_LSI) || \
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460 ((SOURCE) == RCC_RTCCLKSource_HSE_Div128))
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465 /** @defgroup AHB_peripheral
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469 #define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001)
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470 #define RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002)
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471 #define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004)
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472 #define RCC_AHBPeriph_FLITF ((uint32_t)0x00000010)
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473 #define RCC_AHBPeriph_CRC ((uint32_t)0x00000040)
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475 #ifndef STM32F10X_CL
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476 #define RCC_AHBPeriph_FSMC ((uint32_t)0x00000100)
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477 #define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400)
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478 #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFAA8) == 0x00) && ((PERIPH) != 0x00))
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480 #define RCC_AHBPeriph_OTG_FS ((uint32_t)0x00001000)
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481 #define RCC_AHBPeriph_ETH_MAC ((uint32_t)0x00004000)
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482 #define RCC_AHBPeriph_ETH_MAC_Tx ((uint32_t)0x00008000)
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483 #define RCC_AHBPeriph_ETH_MAC_Rx ((uint32_t)0x00010000)
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485 #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFE2FA8) == 0x00) && ((PERIPH) != 0x00))
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486 #define IS_RCC_AHB_PERIPH_RESET(PERIPH) ((((PERIPH) & 0xFFFFAFFF) == 0x00) && ((PERIPH) != 0x00))
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487 #endif /* STM32F10X_CL */
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492 /** @defgroup APB2_peripheral
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496 #define RCC_APB2Periph_AFIO ((uint32_t)0x00000001)
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497 #define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004)
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498 #define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008)
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499 #define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010)
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500 #define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020)
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501 #define RCC_APB2Periph_GPIOE ((uint32_t)0x00000040)
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502 #define RCC_APB2Periph_GPIOF ((uint32_t)0x00000080)
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503 #define RCC_APB2Periph_GPIOG ((uint32_t)0x00000100)
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504 #define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200)
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505 #define RCC_APB2Periph_ADC2 ((uint32_t)0x00000400)
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506 #define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800)
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507 #define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000)
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508 #define RCC_APB2Periph_TIM8 ((uint32_t)0x00002000)
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509 #define RCC_APB2Periph_USART1 ((uint32_t)0x00004000)
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510 #define RCC_APB2Periph_ADC3 ((uint32_t)0x00008000)
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511 #define RCC_APB2Periph_TIM15 ((uint32_t)0x00010000)
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512 #define RCC_APB2Periph_TIM16 ((uint32_t)0x00020000)
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513 #define RCC_APB2Periph_TIM17 ((uint32_t)0x00040000)
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514 #define RCC_APB2Periph_TIM9 ((uint32_t)0x00080000)
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515 #define RCC_APB2Periph_TIM10 ((uint32_t)0x00100000)
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516 #define RCC_APB2Periph_TIM11 ((uint32_t)0x00200000)
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518 #define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFC00002) == 0x00) && ((PERIPH) != 0x00))
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523 /** @defgroup APB1_peripheral
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527 #define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001)
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528 #define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002)
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529 #define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004)
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530 #define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008)
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531 #define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010)
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532 #define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020)
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533 #define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040)
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534 #define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080)
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535 #define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100)
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536 #define RCC_APB1Periph_WWDG ((uint32_t)0x00000800)
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537 #define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000)
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538 #define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000)
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539 #define RCC_APB1Periph_USART2 ((uint32_t)0x00020000)
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540 #define RCC_APB1Periph_USART3 ((uint32_t)0x00040000)
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541 #define RCC_APB1Periph_UART4 ((uint32_t)0x00080000)
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542 #define RCC_APB1Periph_UART5 ((uint32_t)0x00100000)
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543 #define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000)
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544 #define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000)
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545 #define RCC_APB1Periph_USB ((uint32_t)0x00800000)
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546 #define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000)
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547 #define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000)
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548 #define RCC_APB1Periph_BKP ((uint32_t)0x08000000)
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549 #define RCC_APB1Periph_PWR ((uint32_t)0x10000000)
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550 #define RCC_APB1Periph_DAC ((uint32_t)0x20000000)
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551 #define RCC_APB1Periph_CEC ((uint32_t)0x40000000)
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553 #define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x81013600) == 0x00) && ((PERIPH) != 0x00))
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559 /** @defgroup Clock_source_to_output_on_MCO_pin
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563 #define RCC_MCO_NoClock ((uint8_t)0x00)
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564 #define RCC_MCO_SYSCLK ((uint8_t)0x04)
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565 #define RCC_MCO_HSI ((uint8_t)0x05)
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566 #define RCC_MCO_HSE ((uint8_t)0x06)
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567 #define RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07)
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569 #ifndef STM32F10X_CL
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570 #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \
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571 ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \
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572 ((MCO) == RCC_MCO_PLLCLK_Div2))
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574 #define RCC_MCO_PLL2CLK ((uint8_t)0x08)
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575 #define RCC_MCO_PLL3CLK_Div2 ((uint8_t)0x09)
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576 #define RCC_MCO_XT1 ((uint8_t)0x0A)
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577 #define RCC_MCO_PLL3CLK ((uint8_t)0x0B)
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579 #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \
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580 ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \
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581 ((MCO) == RCC_MCO_PLLCLK_Div2) || ((MCO) == RCC_MCO_PLL2CLK) || \
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582 ((MCO) == RCC_MCO_PLL3CLK_Div2) || ((MCO) == RCC_MCO_XT1) || \
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583 ((MCO) == RCC_MCO_PLL3CLK))
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584 #endif /* STM32F10X_CL */
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590 /** @defgroup RCC_Flag
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594 #define RCC_FLAG_HSIRDY ((uint8_t)0x21)
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595 #define RCC_FLAG_HSERDY ((uint8_t)0x31)
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596 #define RCC_FLAG_PLLRDY ((uint8_t)0x39)
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597 #define RCC_FLAG_LSERDY ((uint8_t)0x41)
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598 #define RCC_FLAG_LSIRDY ((uint8_t)0x61)
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599 #define RCC_FLAG_PINRST ((uint8_t)0x7A)
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600 #define RCC_FLAG_PORRST ((uint8_t)0x7B)
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601 #define RCC_FLAG_SFTRST ((uint8_t)0x7C)
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602 #define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
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603 #define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
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604 #define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
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606 #ifndef STM32F10X_CL
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607 #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
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608 ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
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609 ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \
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610 ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \
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611 ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \
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612 ((FLAG) == RCC_FLAG_LPWRRST))
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614 #define RCC_FLAG_PLL2RDY ((uint8_t)0x3B)
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615 #define RCC_FLAG_PLL3RDY ((uint8_t)0x3D)
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616 #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
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617 ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
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618 ((FLAG) == RCC_FLAG_PLL2RDY) || ((FLAG) == RCC_FLAG_PLL3RDY) || \
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619 ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \
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620 ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \
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621 ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \
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622 ((FLAG) == RCC_FLAG_LPWRRST))
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623 #endif /* STM32F10X_CL */
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625 #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
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634 /** @defgroup RCC_Exported_Macros
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642 /** @defgroup RCC_Exported_Functions
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646 void RCC_DeInit(void);
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647 void RCC_HSEConfig(uint32_t RCC_HSE);
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648 ErrorStatus RCC_WaitForHSEStartUp(void);
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649 void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
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650 void RCC_HSICmd(FunctionalState NewState);
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651 void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul);
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652 void RCC_PLLCmd(FunctionalState NewState);
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654 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_CL)
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655 void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div);
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658 #ifdef STM32F10X_CL
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659 void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div);
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660 void RCC_PLL2Config(uint32_t RCC_PLL2Mul);
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661 void RCC_PLL2Cmd(FunctionalState NewState);
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662 void RCC_PLL3Config(uint32_t RCC_PLL3Mul);
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663 void RCC_PLL3Cmd(FunctionalState NewState);
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664 #endif /* STM32F10X_CL */
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666 void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
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667 uint8_t RCC_GetSYSCLKSource(void);
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668 void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
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669 void RCC_PCLK1Config(uint32_t RCC_HCLK);
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670 void RCC_PCLK2Config(uint32_t RCC_HCLK);
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671 void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
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673 #ifndef STM32F10X_CL
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674 void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource);
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676 void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource);
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677 #endif /* STM32F10X_CL */
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679 void RCC_ADCCLKConfig(uint32_t RCC_PCLK2);
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681 #ifdef STM32F10X_CL
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682 void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource);
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683 void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource);
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684 #endif /* STM32F10X_CL */
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686 void RCC_LSEConfig(uint8_t RCC_LSE);
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687 void RCC_LSICmd(FunctionalState NewState);
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688 void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
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689 void RCC_RTCCLKCmd(FunctionalState NewState);
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690 void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
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691 void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
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692 void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
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693 void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
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695 #ifdef STM32F10X_CL
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696 void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
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697 #endif /* STM32F10X_CL */
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699 void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
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700 void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
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701 void RCC_BackupResetCmd(FunctionalState NewState);
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702 void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
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703 void RCC_MCOConfig(uint8_t RCC_MCO);
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704 FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
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705 void RCC_ClearFlag(void);
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706 ITStatus RCC_GetITStatus(uint8_t RCC_IT);
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707 void RCC_ClearITPendingBit(uint8_t RCC_IT);
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713 #endif /* __STM32F10x_RCC_H */
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726 /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
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