2 ******************************************************************************
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3 * @file stm32f10x_i2c.c
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4 * @author MCD Application Team
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7 * @brief This file provides all the I2C firmware functions.
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8 ******************************************************************************
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11 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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12 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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13 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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14 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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15 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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16 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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18 * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
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21 /* Includes ------------------------------------------------------------------*/
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22 #include "stm32f10x_i2c.h"
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23 #include "stm32f10x_rcc.h"
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26 /** @addtogroup STM32F10x_StdPeriph_Driver
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31 * @brief I2C driver modules
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35 /** @defgroup I2C_Private_TypesDefinitions
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43 /** @defgroup I2C_Private_Defines
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48 #define CR1_PE_Set ((uint16_t)0x0001)
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49 #define CR1_PE_Reset ((uint16_t)0xFFFE)
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51 /* I2C START mask */
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52 #define CR1_START_Set ((uint16_t)0x0100)
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53 #define CR1_START_Reset ((uint16_t)0xFEFF)
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56 #define CR1_STOP_Set ((uint16_t)0x0200)
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57 #define CR1_STOP_Reset ((uint16_t)0xFDFF)
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60 #define CR1_ACK_Set ((uint16_t)0x0400)
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61 #define CR1_ACK_Reset ((uint16_t)0xFBFF)
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64 #define CR1_ENGC_Set ((uint16_t)0x0040)
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65 #define CR1_ENGC_Reset ((uint16_t)0xFFBF)
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67 /* I2C SWRST mask */
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68 #define CR1_SWRST_Set ((uint16_t)0x8000)
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69 #define CR1_SWRST_Reset ((uint16_t)0x7FFF)
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72 #define CR1_PEC_Set ((uint16_t)0x1000)
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73 #define CR1_PEC_Reset ((uint16_t)0xEFFF)
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75 /* I2C ENPEC mask */
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76 #define CR1_ENPEC_Set ((uint16_t)0x0020)
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77 #define CR1_ENPEC_Reset ((uint16_t)0xFFDF)
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79 /* I2C ENARP mask */
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80 #define CR1_ENARP_Set ((uint16_t)0x0010)
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81 #define CR1_ENARP_Reset ((uint16_t)0xFFEF)
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83 /* I2C NOSTRETCH mask */
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84 #define CR1_NOSTRETCH_Set ((uint16_t)0x0080)
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85 #define CR1_NOSTRETCH_Reset ((uint16_t)0xFF7F)
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87 /* I2C registers Masks */
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88 #define CR1_CLEAR_Mask ((uint16_t)0xFBF5)
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90 /* I2C DMAEN mask */
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91 #define CR2_DMAEN_Set ((uint16_t)0x0800)
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92 #define CR2_DMAEN_Reset ((uint16_t)0xF7FF)
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95 #define CR2_LAST_Set ((uint16_t)0x1000)
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96 #define CR2_LAST_Reset ((uint16_t)0xEFFF)
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99 #define CR2_FREQ_Reset ((uint16_t)0xFFC0)
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101 /* I2C ADD0 mask */
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102 #define OAR1_ADD0_Set ((uint16_t)0x0001)
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103 #define OAR1_ADD0_Reset ((uint16_t)0xFFFE)
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105 /* I2C ENDUAL mask */
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106 #define OAR2_ENDUAL_Set ((uint16_t)0x0001)
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107 #define OAR2_ENDUAL_Reset ((uint16_t)0xFFFE)
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109 /* I2C ADD2 mask */
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110 #define OAR2_ADD2_Reset ((uint16_t)0xFF01)
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113 #define CCR_FS_Set ((uint16_t)0x8000)
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116 #define CCR_CCR_Set ((uint16_t)0x0FFF)
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118 /* I2C FLAG mask */
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119 #define FLAG_Mask ((uint32_t)0x00FFFFFF)
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121 /* I2C Interrupt Enable mask */
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122 #define ITEN_Mask ((uint32_t)0x07000000)
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128 /** @defgroup I2C_Private_Macros
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136 /** @defgroup I2C_Private_Variables
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144 /** @defgroup I2C_Private_FunctionPrototypes
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152 /** @defgroup I2C_Private_Functions
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157 * @brief Deinitializes the I2Cx peripheral registers to their default reset values.
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158 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
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161 void I2C_DeInit(I2C_TypeDef* I2Cx)
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163 /* Check the parameters */
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164 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
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168 /* Enable I2C1 reset state */
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169 RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE);
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170 /* Release I2C1 from reset state */
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171 RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE);
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175 /* Enable I2C2 reset state */
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176 RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE);
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177 /* Release I2C2 from reset state */
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178 RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE);
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183 * @brief Initializes the I2Cx peripheral according to the specified
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184 * parameters in the I2C_InitStruct.
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185 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
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186 * @param I2C_InitStruct: pointer to a I2C_InitTypeDef structure that
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187 * contains the configuration information for the specified I2C peripheral.
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190 void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct)
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192 uint16_t tmpreg = 0, freqrange = 0;
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193 uint16_t result = 0x04;
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194 uint32_t pclk1 = 8000000;
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195 RCC_ClocksTypeDef rcc_clocks;
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196 /* Check the parameters */
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197 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
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198 assert_param(IS_I2C_CLOCK_SPEED(I2C_InitStruct->I2C_ClockSpeed));
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199 assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode));
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200 assert_param(IS_I2C_DUTY_CYCLE(I2C_InitStruct->I2C_DutyCycle));
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201 assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1));
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202 assert_param(IS_I2C_ACK_STATE(I2C_InitStruct->I2C_Ack));
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203 assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress));
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205 /*---------------------------- I2Cx CR2 Configuration ------------------------*/
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206 /* Get the I2Cx CR2 value */
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207 tmpreg = I2Cx->CR2;
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208 /* Clear frequency FREQ[5:0] bits */
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209 tmpreg &= CR2_FREQ_Reset;
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210 /* Get pclk1 frequency value */
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211 RCC_GetClocksFreq(&rcc_clocks);
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212 pclk1 = rcc_clocks.PCLK1_Frequency;
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213 /* Set frequency bits depending on pclk1 value */
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214 freqrange = (uint16_t)(pclk1 / 1000000);
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215 tmpreg |= freqrange;
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216 /* Write to I2Cx CR2 */
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217 I2Cx->CR2 = tmpreg;
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219 /*---------------------------- I2Cx CCR Configuration ------------------------*/
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220 /* Disable the selected I2C peripheral to configure TRISE */
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221 I2Cx->CR1 &= CR1_PE_Reset;
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222 /* Reset tmpreg value */
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223 /* Clear F/S, DUTY and CCR[11:0] bits */
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226 /* Configure speed in standard mode */
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227 if (I2C_InitStruct->I2C_ClockSpeed <= 100000)
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229 /* Standard mode speed calculate */
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230 result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1));
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231 /* Test if CCR value is under 0x4*/
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234 /* Set minimum allowed value */
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237 /* Set speed value for standard mode */
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239 /* Set Maximum Rise Time for standard mode */
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240 I2Cx->TRISE = freqrange + 1;
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242 /* Configure speed in fast mode */
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243 else /*(I2C_InitStruct->I2C_ClockSpeed <= 400000)*/
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245 if (I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2)
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247 /* Fast mode speed calculate: Tlow/Thigh = 2 */
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248 result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3));
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250 else /*I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_16_9*/
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252 /* Fast mode speed calculate: Tlow/Thigh = 16/9 */
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253 result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25));
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255 result |= I2C_DutyCycle_16_9;
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258 /* Test if CCR value is under 0x1*/
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259 if ((result & CCR_CCR_Set) == 0)
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261 /* Set minimum allowed value */
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262 result |= (uint16_t)0x0001;
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264 /* Set speed value and set F/S bit for fast mode */
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265 tmpreg |= (uint16_t)(result | CCR_FS_Set);
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266 /* Set Maximum Rise Time for fast mode */
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267 I2Cx->TRISE = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1);
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270 /* Write to I2Cx CCR */
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271 I2Cx->CCR = tmpreg;
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272 /* Enable the selected I2C peripheral */
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273 I2Cx->CR1 |= CR1_PE_Set;
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275 /*---------------------------- I2Cx CR1 Configuration ------------------------*/
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276 /* Get the I2Cx CR1 value */
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277 tmpreg = I2Cx->CR1;
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278 /* Clear ACK, SMBTYPE and SMBUS bits */
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279 tmpreg &= CR1_CLEAR_Mask;
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280 /* Configure I2Cx: mode and acknowledgement */
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281 /* Set SMBTYPE and SMBUS bits according to I2C_Mode value */
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282 /* Set ACK bit according to I2C_Ack value */
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283 tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack);
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284 /* Write to I2Cx CR1 */
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285 I2Cx->CR1 = tmpreg;
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287 /*---------------------------- I2Cx OAR1 Configuration -----------------------*/
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288 /* Set I2Cx Own Address1 and acknowledged address */
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289 I2Cx->OAR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1);
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293 * @brief Fills each I2C_InitStruct member with its default value.
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294 * @param I2C_InitStruct: pointer to an I2C_InitTypeDef structure which will be initialized.
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297 void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct)
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299 /*---------------- Reset I2C init structure parameters values ----------------*/
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300 /* initialize the I2C_ClockSpeed member */
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301 I2C_InitStruct->I2C_ClockSpeed = 5000;
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302 /* Initialize the I2C_Mode member */
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303 I2C_InitStruct->I2C_Mode = I2C_Mode_I2C;
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304 /* Initialize the I2C_DutyCycle member */
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305 I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2;
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306 /* Initialize the I2C_OwnAddress1 member */
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307 I2C_InitStruct->I2C_OwnAddress1 = 0;
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308 /* Initialize the I2C_Ack member */
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309 I2C_InitStruct->I2C_Ack = I2C_Ack_Disable;
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310 /* Initialize the I2C_AcknowledgedAddress member */
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311 I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
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315 * @brief Enables or disables the specified I2C peripheral.
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316 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
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317 * @param NewState: new state of the I2Cx peripheral.
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318 * This parameter can be: ENABLE or DISABLE.
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321 void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
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323 /* Check the parameters */
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324 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
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325 assert_param(IS_FUNCTIONAL_STATE(NewState));
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326 if (NewState != DISABLE)
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328 /* Enable the selected I2C peripheral */
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329 I2Cx->CR1 |= CR1_PE_Set;
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333 /* Disable the selected I2C peripheral */
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334 I2Cx->CR1 &= CR1_PE_Reset;
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339 * @brief Enables or disables the specified I2C DMA requests.
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340 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
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341 * @param NewState: new state of the I2C DMA transfer.
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342 * This parameter can be: ENABLE or DISABLE.
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345 void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
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347 /* Check the parameters */
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348 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
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349 assert_param(IS_FUNCTIONAL_STATE(NewState));
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350 if (NewState != DISABLE)
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352 /* Enable the selected I2C DMA requests */
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353 I2Cx->CR2 |= CR2_DMAEN_Set;
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357 /* Disable the selected I2C DMA requests */
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358 I2Cx->CR2 &= CR2_DMAEN_Reset;
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363 * @brief Specifies if the next DMA transfer will be the last one.
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364 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
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365 * @param NewState: new state of the I2C DMA last transfer.
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366 * This parameter can be: ENABLE or DISABLE.
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369 void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
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371 /* Check the parameters */
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372 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
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373 assert_param(IS_FUNCTIONAL_STATE(NewState));
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374 if (NewState != DISABLE)
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376 /* Next DMA transfer is the last transfer */
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377 I2Cx->CR2 |= CR2_LAST_Set;
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381 /* Next DMA transfer is not the last transfer */
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382 I2Cx->CR2 &= CR2_LAST_Reset;
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387 * @brief Generates I2Cx communication START condition.
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388 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
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389 * @param NewState: new state of the I2C START condition generation.
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390 * This parameter can be: ENABLE or DISABLE.
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393 void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState)
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395 /* Check the parameters */
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396 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
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397 assert_param(IS_FUNCTIONAL_STATE(NewState));
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398 if (NewState != DISABLE)
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400 /* Generate a START condition */
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401 I2Cx->CR1 |= CR1_START_Set;
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405 /* Disable the START condition generation */
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406 I2Cx->CR1 &= CR1_START_Reset;
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411 * @brief Generates I2Cx communication STOP condition.
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412 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
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413 * @param NewState: new state of the I2C STOP condition generation.
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414 * This parameter can be: ENABLE or DISABLE.
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417 void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState)
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419 /* Check the parameters */
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420 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
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421 assert_param(IS_FUNCTIONAL_STATE(NewState));
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422 if (NewState != DISABLE)
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424 /* Generate a STOP condition */
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425 I2Cx->CR1 |= CR1_STOP_Set;
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429 /* Disable the STOP condition generation */
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430 I2Cx->CR1 &= CR1_STOP_Reset;
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435 * @brief Enables or disables the specified I2C acknowledge feature.
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436 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
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437 * @param NewState: new state of the I2C Acknowledgement.
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438 * This parameter can be: ENABLE or DISABLE.
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441 void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState)
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443 /* Check the parameters */
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444 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
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445 assert_param(IS_FUNCTIONAL_STATE(NewState));
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446 if (NewState != DISABLE)
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448 /* Enable the acknowledgement */
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449 I2Cx->CR1 |= CR1_ACK_Set;
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453 /* Disable the acknowledgement */
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454 I2Cx->CR1 &= CR1_ACK_Reset;
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459 * @brief Configures the specified I2C own address2.
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460 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
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461 * @param Address: specifies the 7bit I2C own address2.
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464 void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address)
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466 uint16_t tmpreg = 0;
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468 /* Check the parameters */
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469 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
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471 /* Get the old register value */
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472 tmpreg = I2Cx->OAR2;
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474 /* Reset I2Cx Own address2 bit [7:1] */
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475 tmpreg &= OAR2_ADD2_Reset;
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477 /* Set I2Cx Own address2 */
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478 tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE);
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480 /* Store the new register value */
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481 I2Cx->OAR2 = tmpreg;
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485 * @brief Enables or disables the specified I2C dual addressing mode.
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486 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
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487 * @param NewState: new state of the I2C dual addressing mode.
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488 * This parameter can be: ENABLE or DISABLE.
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491 void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
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493 /* Check the parameters */
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494 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
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495 assert_param(IS_FUNCTIONAL_STATE(NewState));
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496 if (NewState != DISABLE)
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498 /* Enable dual addressing mode */
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499 I2Cx->OAR2 |= OAR2_ENDUAL_Set;
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503 /* Disable dual addressing mode */
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504 I2Cx->OAR2 &= OAR2_ENDUAL_Reset;
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509 * @brief Enables or disables the specified I2C general call feature.
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510 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
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511 * @param NewState: new state of the I2C General call.
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512 * This parameter can be: ENABLE or DISABLE.
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515 void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
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517 /* Check the parameters */
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518 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
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519 assert_param(IS_FUNCTIONAL_STATE(NewState));
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520 if (NewState != DISABLE)
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522 /* Enable generall call */
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523 I2Cx->CR1 |= CR1_ENGC_Set;
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527 /* Disable generall call */
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528 I2Cx->CR1 &= CR1_ENGC_Reset;
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533 * @brief Enables or disables the specified I2C interrupts.
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534 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
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535 * @param I2C_IT: specifies the I2C interrupts sources to be enabled or disabled.
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536 * This parameter can be any combination of the following values:
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537 * @arg I2C_IT_BUF: Buffer interrupt mask
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538 * @arg I2C_IT_EVT: Event interrupt mask
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539 * @arg I2C_IT_ERR: Error interrupt mask
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540 * @param NewState: new state of the specified I2C interrupts.
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541 * This parameter can be: ENABLE or DISABLE.
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544 void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState)
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546 /* Check the parameters */
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547 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
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548 assert_param(IS_FUNCTIONAL_STATE(NewState));
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549 assert_param(IS_I2C_CONFIG_IT(I2C_IT));
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551 if (NewState != DISABLE)
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553 /* Enable the selected I2C interrupts */
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554 I2Cx->CR2 |= I2C_IT;
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558 /* Disable the selected I2C interrupts */
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559 I2Cx->CR2 &= (uint16_t)~I2C_IT;
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564 * @brief Sends a data byte through the I2Cx peripheral.
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565 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
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566 * @param Data: Byte to be transmitted..
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569 void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data)
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571 /* Check the parameters */
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572 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
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573 /* Write in the DR register the data to be sent */
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578 * @brief Returns the most recent received data by the I2Cx peripheral.
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579 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
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580 * @retval The value of the received data.
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582 uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx)
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584 /* Check the parameters */
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585 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
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586 /* Return the data in the DR register */
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587 return (uint8_t)I2Cx->DR;
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591 * @brief Transmits the address byte to select the slave device.
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592 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
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593 * @param Address: specifies the slave address which will be transmitted
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594 * @param I2C_Direction: specifies whether the I2C device will be a
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595 * Transmitter or a Receiver. This parameter can be one of the following values
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596 * @arg I2C_Direction_Transmitter: Transmitter mode
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597 * @arg I2C_Direction_Receiver: Receiver mode
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600 void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction)
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602 /* Check the parameters */
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603 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
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604 assert_param(IS_I2C_DIRECTION(I2C_Direction));
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605 /* Test on the direction to set/reset the read/write bit */
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606 if (I2C_Direction != I2C_Direction_Transmitter)
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608 /* Set the address bit0 for read */
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609 Address |= OAR1_ADD0_Set;
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613 /* Reset the address bit0 for write */
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614 Address &= OAR1_ADD0_Reset;
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616 /* Send the address */
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617 I2Cx->DR = Address;
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621 * @brief Reads the specified I2C register and returns its value.
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622 * @param I2C_Register: specifies the register to read.
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623 * This parameter can be one of the following values:
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624 * @arg I2C_Register_CR1: CR1 register.
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625 * @arg I2C_Register_CR2: CR2 register.
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626 * @arg I2C_Register_OAR1: OAR1 register.
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627 * @arg I2C_Register_OAR2: OAR2 register.
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628 * @arg I2C_Register_DR: DR register.
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629 * @arg I2C_Register_SR1: SR1 register.
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630 * @arg I2C_Register_SR2: SR2 register.
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631 * @arg I2C_Register_CCR: CCR register.
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632 * @arg I2C_Register_TRISE: TRISE register.
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633 * @retval The value of the read register.
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635 uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register)
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637 __IO uint32_t tmp = 0;
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639 /* Check the parameters */
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640 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
\r
641 assert_param(IS_I2C_REGISTER(I2C_Register));
\r
643 tmp = (uint32_t) I2Cx;
\r
644 tmp += I2C_Register;
\r
646 /* Return the selected register value */
\r
647 return (*(__IO uint16_t *) tmp);
\r
651 * @brief Enables or disables the specified I2C software reset.
\r
652 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
\r
653 * @param NewState: new state of the I2C software reset.
\r
654 * This parameter can be: ENABLE or DISABLE.
\r
657 void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
\r
659 /* Check the parameters */
\r
660 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
\r
661 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
662 if (NewState != DISABLE)
\r
664 /* Peripheral under reset */
\r
665 I2Cx->CR1 |= CR1_SWRST_Set;
\r
669 /* Peripheral not under reset */
\r
670 I2Cx->CR1 &= CR1_SWRST_Reset;
\r
675 * @brief Drives the SMBusAlert pin high or low for the specified I2C.
\r
676 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
\r
677 * @param I2C_SMBusAlert: specifies SMBAlert pin level.
\r
678 * This parameter can be one of the following values:
\r
679 * @arg I2C_SMBusAlert_Low: SMBAlert pin driven low
\r
680 * @arg I2C_SMBusAlert_High: SMBAlert pin driven high
\r
683 void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert)
\r
685 /* Check the parameters */
\r
686 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
\r
687 assert_param(IS_I2C_SMBUS_ALERT(I2C_SMBusAlert));
\r
688 if (I2C_SMBusAlert == I2C_SMBusAlert_Low)
\r
690 /* Drive the SMBusAlert pin Low */
\r
691 I2Cx->CR1 |= I2C_SMBusAlert_Low;
\r
695 /* Drive the SMBusAlert pin High */
\r
696 I2Cx->CR1 &= I2C_SMBusAlert_High;
\r
701 * @brief Enables or disables the specified I2C PEC transfer.
\r
702 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
\r
703 * @param NewState: new state of the I2C PEC transmission.
\r
704 * This parameter can be: ENABLE or DISABLE.
\r
707 void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState)
\r
709 /* Check the parameters */
\r
710 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
\r
711 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
712 if (NewState != DISABLE)
\r
714 /* Enable the selected I2C PEC transmission */
\r
715 I2Cx->CR1 |= CR1_PEC_Set;
\r
719 /* Disable the selected I2C PEC transmission */
\r
720 I2Cx->CR1 &= CR1_PEC_Reset;
\r
725 * @brief Selects the specified I2C PEC position.
\r
726 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
\r
727 * @param I2C_PECPosition: specifies the PEC position.
\r
728 * This parameter can be one of the following values:
\r
729 * @arg I2C_PECPosition_Next: indicates that the next byte is PEC
\r
730 * @arg I2C_PECPosition_Current: indicates that current byte is PEC
\r
733 void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition)
\r
735 /* Check the parameters */
\r
736 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
\r
737 assert_param(IS_I2C_PEC_POSITION(I2C_PECPosition));
\r
738 if (I2C_PECPosition == I2C_PECPosition_Next)
\r
740 /* Next byte in shift register is PEC */
\r
741 I2Cx->CR1 |= I2C_PECPosition_Next;
\r
745 /* Current byte in shift register is PEC */
\r
746 I2Cx->CR1 &= I2C_PECPosition_Current;
\r
751 * @brief Enables or disables the PEC value calculation of the transfered bytes.
\r
752 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
\r
753 * @param NewState: new state of the I2Cx PEC value calculation.
\r
754 * This parameter can be: ENABLE or DISABLE.
\r
757 void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState)
\r
759 /* Check the parameters */
\r
760 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
\r
761 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
762 if (NewState != DISABLE)
\r
764 /* Enable the selected I2C PEC calculation */
\r
765 I2Cx->CR1 |= CR1_ENPEC_Set;
\r
769 /* Disable the selected I2C PEC calculation */
\r
770 I2Cx->CR1 &= CR1_ENPEC_Reset;
\r
775 * @brief Returns the PEC value for the specified I2C.
\r
776 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
\r
777 * @retval The PEC value.
\r
779 uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx)
\r
781 /* Check the parameters */
\r
782 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
\r
783 /* Return the selected I2C PEC value */
\r
784 return ((I2Cx->SR2) >> 8);
\r
788 * @brief Enables or disables the specified I2C ARP.
\r
789 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
\r
790 * @param NewState: new state of the I2Cx ARP.
\r
791 * This parameter can be: ENABLE or DISABLE.
\r
794 void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
\r
796 /* Check the parameters */
\r
797 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
\r
798 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
799 if (NewState != DISABLE)
\r
801 /* Enable the selected I2C ARP */
\r
802 I2Cx->CR1 |= CR1_ENARP_Set;
\r
806 /* Disable the selected I2C ARP */
\r
807 I2Cx->CR1 &= CR1_ENARP_Reset;
\r
812 * @brief Enables or disables the specified I2C Clock stretching.
\r
813 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
\r
814 * @param NewState: new state of the I2Cx Clock stretching.
\r
815 * This parameter can be: ENABLE or DISABLE.
\r
818 void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
\r
820 /* Check the parameters */
\r
821 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
\r
822 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
823 if (NewState == DISABLE)
\r
825 /* Enable the selected I2C Clock stretching */
\r
826 I2Cx->CR1 |= CR1_NOSTRETCH_Set;
\r
830 /* Disable the selected I2C Clock stretching */
\r
831 I2Cx->CR1 &= CR1_NOSTRETCH_Reset;
\r
836 * @brief Selects the specified I2C fast mode duty cycle.
\r
837 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
\r
838 * @param I2C_DutyCycle: specifies the fast mode duty cycle.
\r
839 * This parameter can be one of the following values:
\r
840 * @arg I2C_DutyCycle_2: I2C fast mode Tlow/Thigh = 2
\r
841 * @arg I2C_DutyCycle_16_9: I2C fast mode Tlow/Thigh = 16/9
\r
844 void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle)
\r
846 /* Check the parameters */
\r
847 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
\r
848 assert_param(IS_I2C_DUTY_CYCLE(I2C_DutyCycle));
\r
849 if (I2C_DutyCycle != I2C_DutyCycle_16_9)
\r
851 /* I2C fast mode Tlow/Thigh=2 */
\r
852 I2Cx->CCR &= I2C_DutyCycle_2;
\r
856 /* I2C fast mode Tlow/Thigh=16/9 */
\r
857 I2Cx->CCR |= I2C_DutyCycle_16_9;
\r
865 ****************************************************************************************
\r
867 * I2C State Monitoring Functions
\r
869 ****************************************************************************************
\r
870 * This I2C driver provides three different ways for I2C state monitoring
\r
871 * depending on the application requirements and constraints:
\r
874 * 1) Basic state monitoring:
\r
875 * Using I2C_CheckEvent() function:
\r
876 * It compares the status registers (SR1 and SR2) content to a given event
\r
877 * (can be the combination of one or more flags).
\r
878 * It returns SUCCESS if the current status includes the given flags
\r
879 * and returns ERROR if one or more flags are missing in the current status.
\r
881 * - This function is suitable for most applciations as well as for startup
\r
882 * activity since the events are fully described in the product reference manual
\r
884 * - It is also suitable for users who need to define their own events.
\r
886 * - If an error occurs (ie. error flags are set besides to the monitored flags),
\r
887 * the I2C_CheckEvent() function may return SUCCESS despite the communication
\r
888 * hold or corrupted real state.
\r
889 * In this case, it is advised to use error interrupts to monitor the error
\r
890 * events and handle them in the interrupt IRQ handler.
\r
893 * For error management, it is advised to use the following functions:
\r
894 * - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
\r
895 * - I2Cx_ER_IRQHandler() which is called when the error interurpt occurs.
\r
896 * Where x is the peripheral instance (I2C1, I2C2 ...)
\r
897 * - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into I2Cx_ER_IRQHandler()
\r
898 * in order to determine which error occured.
\r
899 * - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd()
\r
900 * and/or I2C_GenerateStop() in order to clear the error flag and source,
\r
901 * and return to correct communication status.
\r
904 * 2) Advanced state monitoring:
\r
905 * Using the function I2C_GetLastEvent() which returns the image of both status
\r
906 * registers in a single word (uint32_t) (Status Register 2 value is shifted left
\r
907 * by 16 bits and concatenated to Status Register 1).
\r
909 * - This function is suitable for the same applications above but it allows to
\r
910 * overcome the mentionned limitation of I2C_GetFlagStatus() function.
\r
911 * The returned value could be compared to events already defined in the
\r
912 * library (stm32f10x_i2c.h) or to custom values defiend by user.
\r
913 * - This function is suitable when multiple flags are monitored at the same time.
\r
914 * - At the opposite of I2C_CheckEvent() function, this function allows user to
\r
915 * choose when an event is accepted (when all events flags are set and no
\r
916 * other flags are set or just when the needed flags are set like
\r
917 * I2C_CheckEvent() function).
\r
919 * - User may need to define his own events.
\r
920 * - Same remark concerning the error management is applicable for this
\r
921 * function if user decides to check only regular communication flags (and
\r
922 * ignores error flags).
\r
925 * 3) Flag-based state monitoring:
\r
926 * Using the function I2C_GetFlagStatus() which simply returns the status of
\r
927 * one single flag (ie. I2C_FLAG_RXNE ...).
\r
929 * - This function could be used for specific applications or in debug phase.
\r
930 * - It is suitable when only one flag checking is needed (most I2C events
\r
931 * are monitored through multiple flags).
\r
933 * - When calling this function, the Status register is accessed. Some flags are
\r
934 * cleared when the status register is accessed. So checking the status
\r
935 * of one Flag, may clear other ones.
\r
936 * - Function may need to be called twice or more in order to monitor one
\r
939 * For detailed description of Events, please refer to section I2C_Events in
\r
940 * stm32f10x_i2c.h file.
\r
946 * 1) Basic state monitoring
\r
947 *******************************************************************************
\r
951 * @brief Checks whether the last I2Cx Event is equal to the one passed
\r
953 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
\r
954 * @param I2C_EVENT: specifies the event to be checked.
\r
955 * This parameter can be one of the following values:
\r
956 * @arg I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED : EV1
\r
957 * @arg I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED : EV1
\r
958 * @arg I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED : EV1
\r
959 * @arg I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED : EV1
\r
960 * @arg I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED : EV1
\r
961 * @arg I2C_EVENT_SLAVE_BYTE_RECEIVED : EV2
\r
962 * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF) : EV2
\r
963 * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL) : EV2
\r
964 * @arg I2C_EVENT_SLAVE_BYTE_TRANSMITTED : EV3
\r
965 * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF) : EV3
\r
966 * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL) : EV3
\r
967 * @arg I2C_EVENT_SLAVE_ACK_FAILURE : EV3_2
\r
968 * @arg I2C_EVENT_SLAVE_STOP_DETECTED : EV4
\r
969 * @arg I2C_EVENT_MASTER_MODE_SELECT : EV5
\r
970 * @arg I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED : EV6
\r
971 * @arg I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED : EV6
\r
972 * @arg I2C_EVENT_MASTER_BYTE_RECEIVED : EV7
\r
973 * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTING : EV8
\r
974 * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTED : EV8_2
\r
975 * @arg I2C_EVENT_MASTER_MODE_ADDRESS10 : EV9
\r
977 * @note: For detailed description of Events, please refer to section
\r
978 * I2C_Events in stm32f10x_i2c.h file.
\r
980 * @retval An ErrorStatus enumuration value:
\r
981 * - SUCCESS: Last event is equal to the I2C_EVENT
\r
982 * - ERROR: Last event is different from the I2C_EVENT
\r
984 ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT)
\r
986 uint32_t lastevent = 0;
\r
987 uint32_t flag1 = 0, flag2 = 0;
\r
988 ErrorStatus status = ERROR;
\r
990 /* Check the parameters */
\r
991 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
\r
992 assert_param(IS_I2C_EVENT(I2C_EVENT));
\r
994 /* Read the I2Cx status register */
\r
997 flag2 = flag2 << 16;
\r
999 /* Get the last event value from I2C status register */
\r
1000 lastevent = (flag1 | flag2) & FLAG_Mask;
\r
1002 /* Check whether the last event contains the I2C_EVENT */
\r
1003 if ((lastevent & I2C_EVENT) == I2C_EVENT)
\r
1005 /* SUCCESS: last event is equal to I2C_EVENT */
\r
1010 /* ERROR: last event is different from I2C_EVENT */
\r
1013 /* Return status */
\r
1019 * 2) Advanced state monitoring
\r
1020 *******************************************************************************
\r
1024 * @brief Returns the last I2Cx Event.
\r
1025 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
\r
1027 * @note: For detailed description of Events, please refer to section
\r
1028 * I2C_Events in stm32f10x_i2c.h file.
\r
1030 * @retval The last event
\r
1032 uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx)
\r
1034 uint32_t lastevent = 0;
\r
1035 uint32_t flag1 = 0, flag2 = 0;
\r
1037 /* Check the parameters */
\r
1038 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
\r
1040 /* Read the I2Cx status register */
\r
1041 flag1 = I2Cx->SR1;
\r
1042 flag2 = I2Cx->SR2;
\r
1043 flag2 = flag2 << 16;
\r
1045 /* Get the last event value from I2C status register */
\r
1046 lastevent = (flag1 | flag2) & FLAG_Mask;
\r
1048 /* Return status */
\r
1054 * 3) Flag-based state monitoring
\r
1055 *******************************************************************************
\r
1059 * @brief Checks whether the specified I2C flag is set or not.
\r
1060 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
\r
1061 * @param I2C_FLAG: specifies the flag to check.
\r
1062 * This parameter can be one of the following values:
\r
1063 * @arg I2C_FLAG_DUALF: Dual flag (Slave mode)
\r
1064 * @arg I2C_FLAG_SMBHOST: SMBus host header (Slave mode)
\r
1065 * @arg I2C_FLAG_SMBDEFAULT: SMBus default header (Slave mode)
\r
1066 * @arg I2C_FLAG_GENCALL: General call header flag (Slave mode)
\r
1067 * @arg I2C_FLAG_TRA: Transmitter/Receiver flag
\r
1068 * @arg I2C_FLAG_BUSY: Bus busy flag
\r
1069 * @arg I2C_FLAG_MSL: Master/Slave flag
\r
1070 * @arg I2C_FLAG_SMBALERT: SMBus Alert flag
\r
1071 * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
\r
1072 * @arg I2C_FLAG_PECERR: PEC error in reception flag
\r
1073 * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
\r
1074 * @arg I2C_FLAG_AF: Acknowledge failure flag
\r
1075 * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
\r
1076 * @arg I2C_FLAG_BERR: Bus error flag
\r
1077 * @arg I2C_FLAG_TXE: Data register empty flag (Transmitter)
\r
1078 * @arg I2C_FLAG_RXNE: Data register not empty (Receiver) flag
\r
1079 * @arg I2C_FLAG_STOPF: Stop detection flag (Slave mode)
\r
1080 * @arg I2C_FLAG_ADD10: 10-bit header sent flag (Master mode)
\r
1081 * @arg I2C_FLAG_BTF: Byte transfer finished flag
\r
1082 * @arg I2C_FLAG_ADDR: Address sent flag (Master mode)
\93ADSL
\94\r
1083 * Address matched flag (Slave mode)
\94ENDAD
\94\r
1084 * @arg I2C_FLAG_SB: Start bit flag (Master mode)
\r
1085 * @retval The new state of I2C_FLAG (SET or RESET).
\r
1087 FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
\r
1089 FlagStatus bitstatus = RESET;
\r
1090 __IO uint32_t i2creg = 0, i2cxbase = 0;
\r
1092 /* Check the parameters */
\r
1093 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
\r
1094 assert_param(IS_I2C_GET_FLAG(I2C_FLAG));
\r
1096 /* Get the I2Cx peripheral base address */
\r
1097 i2cxbase = (uint32_t)I2Cx;
\r
1099 /* Read flag register index */
\r
1100 i2creg = I2C_FLAG >> 28;
\r
1102 /* Get bit[23:0] of the flag */
\r
1103 I2C_FLAG &= FLAG_Mask;
\r
1107 /* Get the I2Cx SR1 register address */
\r
1112 /* Flag in I2Cx SR2 Register */
\r
1113 I2C_FLAG = (uint32_t)(I2C_FLAG >> 16);
\r
1114 /* Get the I2Cx SR2 register address */
\r
1118 if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET)
\r
1120 /* I2C_FLAG is set */
\r
1125 /* I2C_FLAG is reset */
\r
1126 bitstatus = RESET;
\r
1129 /* Return the I2C_FLAG status */
\r
1136 * @brief Clears the I2Cx's pending flags.
\r
1137 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
\r
1138 * @param I2C_FLAG: specifies the flag to clear.
\r
1139 * This parameter can be any combination of the following values:
\r
1140 * @arg I2C_FLAG_SMBALERT: SMBus Alert flag
\r
1141 * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
\r
1142 * @arg I2C_FLAG_PECERR: PEC error in reception flag
\r
1143 * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
\r
1144 * @arg I2C_FLAG_AF: Acknowledge failure flag
\r
1145 * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
\r
1146 * @arg I2C_FLAG_BERR: Bus error flag
\r
1149 * - STOPF (STOP detection) is cleared by software sequence: a read operation
\r
1150 * to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation
\r
1151 * to I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral).
\r
1152 * - ADD10 (10-bit header sent) is cleared by software sequence: a read
\r
1153 * operation to I2C_SR1 (I2C_GetFlagStatus()) followed by writing the
\r
1154 * second byte of the address in DR register.
\r
1155 * - BTF (Byte Transfer Finished) is cleared by software sequence: a read
\r
1156 * operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a
\r
1157 * read/write to I2C_DR register (I2C_SendData()).
\r
1158 * - ADDR (Address sent) is cleared by software sequence: a read operation to
\r
1159 * I2C_SR1 register (I2C_GetFlagStatus()) followed by a read operation to
\r
1160 * I2C_SR2 register ((void)(I2Cx->SR2)).
\r
1161 * - SB (Start Bit) is cleared software sequence: a read operation to I2C_SR1
\r
1162 * register (I2C_GetFlagStatus()) followed by a write operation to I2C_DR
\r
1163 * register (I2C_SendData()).
\r
1166 void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
\r
1168 uint32_t flagpos = 0;
\r
1169 /* Check the parameters */
\r
1170 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
\r
1171 assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG));
\r
1172 /* Get the I2C flag position */
\r
1173 flagpos = I2C_FLAG & FLAG_Mask;
\r
1174 /* Clear the selected I2C flag */
\r
1175 I2Cx->SR1 = (uint16_t)~flagpos;
\r
1179 * @brief Checks whether the specified I2C interrupt has occurred or not.
\r
1180 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
\r
1181 * @param I2C_IT: specifies the interrupt source to check.
\r
1182 * This parameter can be one of the following values:
\r
1183 * @arg I2C_IT_SMBALERT: SMBus Alert flag
\r
1184 * @arg I2C_IT_TIMEOUT: Timeout or Tlow error flag
\r
1185 * @arg I2C_IT_PECERR: PEC error in reception flag
\r
1186 * @arg I2C_IT_OVR: Overrun/Underrun flag (Slave mode)
\r
1187 * @arg I2C_IT_AF: Acknowledge failure flag
\r
1188 * @arg I2C_IT_ARLO: Arbitration lost flag (Master mode)
\r
1189 * @arg I2C_IT_BERR: Bus error flag
\r
1190 * @arg I2C_IT_TXE: Data register empty flag (Transmitter)
\r
1191 * @arg I2C_IT_RXNE: Data register not empty (Receiver) flag
\r
1192 * @arg I2C_IT_STOPF: Stop detection flag (Slave mode)
\r
1193 * @arg I2C_IT_ADD10: 10-bit header sent flag (Master mode)
\r
1194 * @arg I2C_IT_BTF: Byte transfer finished flag
\r
1195 * @arg I2C_IT_ADDR: Address sent flag (Master mode)
\93ADSL
\94\r
1196 * Address matched flag (Slave mode)
\94ENDAD
\94\r
1197 * @arg I2C_IT_SB: Start bit flag (Master mode)
\r
1198 * @retval The new state of I2C_IT (SET or RESET).
\r
1200 ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
\r
1202 ITStatus bitstatus = RESET;
\r
1203 uint32_t enablestatus = 0;
\r
1205 /* Check the parameters */
\r
1206 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
\r
1207 assert_param(IS_I2C_GET_IT(I2C_IT));
\r
1209 /* Check if the interrupt source is enabled or not */
\r
1210 enablestatus = (uint32_t)(((I2C_IT & ITEN_Mask) >> 16) & (I2Cx->CR2)) ;
\r
1212 /* Get bit[23:0] of the flag */
\r
1213 I2C_IT &= FLAG_Mask;
\r
1215 /* Check the status of the specified I2C flag */
\r
1216 if (((I2Cx->SR1 & I2C_IT) != (uint32_t)RESET) && enablestatus)
\r
1218 /* I2C_IT is set */
\r
1223 /* I2C_IT is reset */
\r
1224 bitstatus = RESET;
\r
1226 /* Return the I2C_IT status */
\r
1231 * @brief Clears the I2Cx
\92s interrupt pending bits.
\r
1232 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
\r
1233 * @param I2C_IT: specifies the interrupt pending bit to clear.
\r
1234 * This parameter can be any combination of the following values:
\r
1235 * @arg I2C_IT_SMBALERT: SMBus Alert interrupt
\r
1236 * @arg I2C_IT_TIMEOUT: Timeout or Tlow error interrupt
\r
1237 * @arg I2C_IT_PECERR: PEC error in reception interrupt
\r
1238 * @arg I2C_IT_OVR: Overrun/Underrun interrupt (Slave mode)
\r
1239 * @arg I2C_IT_AF: Acknowledge failure interrupt
\r
1240 * @arg I2C_IT_ARLO: Arbitration lost interrupt (Master mode)
\r
1241 * @arg I2C_IT_BERR: Bus error interrupt
\r
1244 * - STOPF (STOP detection) is cleared by software sequence: a read operation
\r
1245 * to I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to
\r
1246 * I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral).
\r
1247 * - ADD10 (10-bit header sent) is cleared by software sequence: a read
\r
1248 * operation to I2C_SR1 (I2C_GetITStatus()) followed by writing the second
\r
1249 * byte of the address in I2C_DR register.
\r
1250 * - BTF (Byte Transfer Finished) is cleared by software sequence: a read
\r
1251 * operation to I2C_SR1 register (I2C_GetITStatus()) followed by a
\r
1252 * read/write to I2C_DR register (I2C_SendData()).
\r
1253 * - ADDR (Address sent) is cleared by software sequence: a read operation to
\r
1254 * I2C_SR1 register (I2C_GetITStatus()) followed by a read operation to
\r
1255 * I2C_SR2 register ((void)(I2Cx->SR2)).
\r
1256 * - SB (Start Bit) is cleared by software sequence: a read operation to
\r
1257 * I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to
\r
1258 * I2C_DR register (I2C_SendData()).
\r
1261 void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
\r
1263 uint32_t flagpos = 0;
\r
1264 /* Check the parameters */
\r
1265 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
\r
1266 assert_param(IS_I2C_CLEAR_IT(I2C_IT));
\r
1267 /* Get the I2C flag position */
\r
1268 flagpos = I2C_IT & FLAG_Mask;
\r
1269 /* Clear the selected I2C flag */
\r
1270 I2Cx->SR1 = (uint16_t)~flagpos;
\r
1285 /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
\r