2 ******************************************************************************
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3 * @file stm32f10x_pwr.c
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4 * @author MCD Application Team
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7 * @brief This file provides all the PWR firmware functions.
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8 ******************************************************************************
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11 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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12 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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13 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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14 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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15 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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16 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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18 * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
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21 /* Includes ------------------------------------------------------------------*/
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22 #include "stm32f10x_pwr.h"
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23 #include "stm32f10x_rcc.h"
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25 /** @addtogroup STM32F10x_StdPeriph_Driver
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30 * @brief PWR driver modules
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34 /** @defgroup PWR_Private_TypesDefinitions
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42 /** @defgroup PWR_Private_Defines
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46 /* --------- PWR registers bit address in the alias region ---------- */
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47 #define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
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49 /* --- CR Register ---*/
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51 /* Alias word address of DBP bit */
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52 #define CR_OFFSET (PWR_OFFSET + 0x00)
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53 #define DBP_BitNumber 0x08
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54 #define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
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56 /* Alias word address of PVDE bit */
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57 #define PVDE_BitNumber 0x04
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58 #define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
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60 /* --- CSR Register ---*/
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62 /* Alias word address of EWUP bit */
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63 #define CSR_OFFSET (PWR_OFFSET + 0x04)
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64 #define EWUP_BitNumber 0x08
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65 #define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
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67 /* ------------------ PWR registers bit mask ------------------------ */
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69 /* CR register bit mask */
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70 #define CR_PDDS_Set ((uint32_t)0x00000002)
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71 #define CR_DS_Mask ((uint32_t)0xFFFFFFFC)
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72 #define CR_CWUF_Set ((uint32_t)0x00000004)
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73 #define CR_PLS_Mask ((uint32_t)0xFFFFFF1F)
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75 /* --------- Cortex System Control register bit mask ---------------- */
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77 /* Cortex System Control register address */
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78 #define SCB_SysCtrl ((uint32_t)0xE000ED10)
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80 /* SLEEPDEEP bit mask */
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81 #define SysCtrl_SLEEPDEEP_Set ((uint32_t)0x00000004)
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82 #define SysCtrl_SLEEPDEEP_Reset ((uint32_t)0xFFFFFFFB)
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88 /** @defgroup PWR_Private_Macros
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96 /** @defgroup PWR_Private_Variables
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104 /** @defgroup PWR_Private_FunctionPrototypes
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112 /** @defgroup PWR_Private_Functions
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117 * @brief Deinitializes the PWR peripheral registers to their default reset values.
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121 void PWR_DeInit(void)
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123 RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
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124 RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
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128 * @brief Enables or disables access to the RTC and backup registers.
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129 * @param NewState: new state of the access to the RTC and backup registers.
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130 * This parameter can be: ENABLE or DISABLE.
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133 void PWR_BackupAccessCmd(FunctionalState NewState)
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135 /* Check the parameters */
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136 assert_param(IS_FUNCTIONAL_STATE(NewState));
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137 *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState;
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141 * @brief Enables or disables the Power Voltage Detector(PVD).
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142 * @param NewState: new state of the PVD.
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143 * This parameter can be: ENABLE or DISABLE.
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146 void PWR_PVDCmd(FunctionalState NewState)
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148 /* Check the parameters */
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149 assert_param(IS_FUNCTIONAL_STATE(NewState));
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150 *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState;
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154 * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
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155 * @param PWR_PVDLevel: specifies the PVD detection level
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156 * This parameter can be one of the following values:
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157 * @arg PWR_PVDLevel_2V2: PVD detection level set to 2.2V
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158 * @arg PWR_PVDLevel_2V3: PVD detection level set to 2.3V
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159 * @arg PWR_PVDLevel_2V4: PVD detection level set to 2.4V
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160 * @arg PWR_PVDLevel_2V5: PVD detection level set to 2.5V
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161 * @arg PWR_PVDLevel_2V6: PVD detection level set to 2.6V
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162 * @arg PWR_PVDLevel_2V7: PVD detection level set to 2.7V
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163 * @arg PWR_PVDLevel_2V8: PVD detection level set to 2.8V
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164 * @arg PWR_PVDLevel_2V9: PVD detection level set to 2.9V
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167 void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
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169 uint32_t tmpreg = 0;
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170 /* Check the parameters */
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171 assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
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173 /* Clear PLS[7:5] bits */
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174 tmpreg &= CR_PLS_Mask;
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175 /* Set PLS[7:5] bits according to PWR_PVDLevel value */
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176 tmpreg |= PWR_PVDLevel;
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177 /* Store the new value */
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182 * @brief Enables or disables the WakeUp Pin functionality.
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183 * @param NewState: new state of the WakeUp Pin functionality.
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184 * This parameter can be: ENABLE or DISABLE.
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187 void PWR_WakeUpPinCmd(FunctionalState NewState)
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189 /* Check the parameters */
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190 assert_param(IS_FUNCTIONAL_STATE(NewState));
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191 *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState;
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195 * @brief Enters STOP mode.
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196 * @param PWR_Regulator: specifies the regulator state in STOP mode.
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197 * This parameter can be one of the following values:
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198 * @arg PWR_Regulator_ON: STOP mode with regulator ON
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199 * @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode
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200 * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
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201 * This parameter can be one of the following values:
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202 * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
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203 * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
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206 void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
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208 uint32_t tmpreg = 0;
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209 /* Check the parameters */
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210 assert_param(IS_PWR_REGULATOR(PWR_Regulator));
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211 assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
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213 /* Select the regulator state in STOP mode ---------------------------------*/
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215 /* Clear PDDS and LPDS bits */
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216 tmpreg &= CR_DS_Mask;
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217 /* Set LPDS bit according to PWR_Regulator value */
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218 tmpreg |= PWR_Regulator;
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219 /* Store the new value */
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221 /* Set SLEEPDEEP bit of Cortex System Control Register */
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222 *(__IO uint32_t *) SCB_SysCtrl |= SysCtrl_SLEEPDEEP_Set;
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224 /* Select STOP mode entry --------------------------------------------------*/
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225 if(PWR_STOPEntry == PWR_STOPEntry_WFI)
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227 /* Request Wait For Interrupt */
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232 /* Request Wait For Event */
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236 /* Reset SLEEPDEEP bit of Cortex System Control Register */
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237 *(__IO uint32_t *) SCB_SysCtrl &= SysCtrl_SLEEPDEEP_Reset;
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241 * @brief Enters STANDBY mode.
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245 void PWR_EnterSTANDBYMode(void)
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247 /* Clear Wake-up flag */
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248 PWR->CR |= CR_CWUF_Set;
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249 /* Select STANDBY mode */
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250 PWR->CR |= CR_PDDS_Set;
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251 /* Set SLEEPDEEP bit of Cortex System Control Register */
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252 *(__IO uint32_t *) SCB_SysCtrl |= SysCtrl_SLEEPDEEP_Set;
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253 /* This option is used to ensure that store operations are completed */
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254 #if defined ( __CC_ARM )
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257 /* Request Wait For Interrupt */
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262 * @brief Checks whether the specified PWR flag is set or not.
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263 * @param PWR_FLAG: specifies the flag to check.
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264 * This parameter can be one of the following values:
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265 * @arg PWR_FLAG_WU: Wake Up flag
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266 * @arg PWR_FLAG_SB: StandBy flag
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267 * @arg PWR_FLAG_PVDO: PVD Output
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268 * @retval The new state of PWR_FLAG (SET or RESET).
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270 FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
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272 FlagStatus bitstatus = RESET;
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273 /* Check the parameters */
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274 assert_param(IS_PWR_GET_FLAG(PWR_FLAG));
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276 if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
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284 /* Return the flag status */
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289 * @brief Clears the PWR's pending flags.
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290 * @param PWR_FLAG: specifies the flag to clear.
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291 * This parameter can be one of the following values:
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292 * @arg PWR_FLAG_WU: Wake Up flag
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293 * @arg PWR_FLAG_SB: StandBy flag
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296 void PWR_ClearFlag(uint32_t PWR_FLAG)
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298 /* Check the parameters */
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299 assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
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301 PWR->CR |= PWR_FLAG << 2;
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316 /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
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