3 Copyright 2004 Broadcom Corp. All Rights Reserved.
5 This program is free software; you can distribute it and/or modify it
6 under the terms of the GNU General Public License (Version 2) as
7 published by the Free Software Foundation.
9 This program is distributed in the hope it will be useful, but WITHOUT
10 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 You should have received a copy of the GNU General Public License along
15 with this program; if not, write to the Free Software Foundation, Inc.,
16 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
20 #ifndef __BCM6338_MAP_H
21 #define __BCM6338_MAP_H
29 #define PERF_BASE 0xfffe0000
30 #define UART_BASE 0xfffe0300
31 #define GPIO_BASE 0xfffe0400
33 typedef struct PerfControl {
37 #define USBH_CLK_EN 0x0100
40 #define SOFT_RESET 0x00000001
46 #define EI_SENSE_SHFT 0
47 #define EI_STATUS_SHFT 5
48 #define EI_CLEAR_SHFT 10
49 #define EI_MASK_SHFT 15
50 #define EI_INSENS_SHFT 20
51 #define EI_LEVEL_SHFT 25
53 uint32 unused[4]; /* (18) */
54 uint32 BlockSoftReset; /* (28) */
55 #define BSR_SPI 0x00000001
56 #define BSR_EMAC 0x00000004
57 #define BSR_USBH 0x00000008
58 #define BSR_USBS 0x00000010
59 #define BSR_ADSL 0x00000020
60 #define BSR_DMAMEM 0x00000040
61 #define BSR_SAR 0x00000080
62 #define BSR_ACLC 0x00000100
63 #define BSR_ADSL_MIPS_PLL 0x00000400
64 #define BSR_ALL_BLOCKS \
65 (BSR_SPI | BSR_EMAC | BSR_USBH | BSR_USBS | BSR_ADSL | BSR_DMAMEM | \
66 BSR_SAR | BSR_ACLC | BSR_ADSL_MIPS_PLL)
69 #define PERF ((volatile PerfControl * const) PERF_BASE)
71 typedef struct UartChannel {
74 #define BRGEN 0x80 /* Control register bit defs */
78 #define TXPARITYEN 0x08
79 #define TXPARITYEVEN 0x04
80 #define RXPARITYEN 0x02
81 #define RXPARITYEVEN 0x01
84 #define XMITBREAK 0x40
91 /* 4-LSBS represent STOP bits/char
92 * in 1/8 bit-time intervals. Zero
93 * represents 1/8 stop bit interval.
94 * Fifteen represents 2 stop bits.
97 #define RSTTXFIFOS 0x80
98 #define RSTRXFIFOS 0x40
99 /* 5-bit TimeoutCnt is in low bits of this register.
100 * This count represents the number of characters
101 * idle times before setting receive Irq when below threshold
104 /* When divide SysClk/2/(1+baudword) we should get 32*bit-rate
107 byte txf_levl; /* Read-only fifo depth */
108 byte rxf_levl; /* Read-only fifo depth */
109 byte fifocfg; /* Upper 4-bits are TxThresh, Lower are
110 * RxThreshold. Irq can be asserted
111 * when rx fifo> thresh, txfifo<thresh
113 byte prog_out; /* Set value of DTR (Bit0), RTS (Bit1)
114 * if these bits are also enabled to GPIO_o
120 byte DeltaIPEdgeNoSense; /* Low 4-bits, set corr bit to 1 to
121 * detect irq on rising AND falling
122 * edges for corresponding GPIO_i
123 * if enabled (edge insensitive)
125 byte DeltaIPConfig_Mask; /* Upper 4 bits: 1 for posedge sense
126 * 0 for negedge sense if
127 * not configured for edge
128 * insensitive (see above)
129 * Lower 4 bits: Mask to enable change
130 * detection IRQ for corresponding
133 byte DeltaIP_SyncIP; /* Upper 4 bits show which bits
134 * have changed (may set IRQ).
135 * read automatically clears bit
136 * Lower 4 bits are actual status
139 uint16 intMask; /* Same Bit defs for Mask and status */
141 #define DELTAIP 0x0001
142 #define TXUNDERR 0x0002
143 #define TXOVFERR 0x0004
144 #define TXFIFOTHOLD 0x0008
145 #define TXREADLATCH 0x0010
146 #define TXFIFOEMT 0x0020
147 #define RXUNDERR 0x0040
148 #define RXOVFERR 0x0080
149 #define RXTIMEOUT 0x0100
150 #define RXFIFOFULL 0x0200
151 #define RXFIFOTHOLD 0x0400
152 #define RXFIFONE 0x0800
153 #define RXFRAMERR 0x1000
154 #define RXPARERR 0x2000
158 uint16 Data; /* Write to TX, Read from RX */
159 /* bits 11:8 are BRK,PAR,FRM errors */
165 #define UART ((volatile Uart * const) UART_BASE)
167 typedef struct GpioControl {
169 uint32 GPIODir; /* bits 7:0 */
171 uint32 GPIOio; /* bits 7:0 */
173 #define LED3_STROBE 0x08000000
174 #define LED2_STROBE 0x04000000
175 #define LED1_STROBE 0x02000000
176 #define LED0_STROBE 0x01000000
177 #define LED_TEST 0x00010000
178 #define LED3_DISABLE_LINK_ACT 0x00008000
179 #define LED2_DISABLE_LINK_ACT 0x00004000
180 #define LED1_DISABLE_LINK_ACT 0x00002000
181 #define LED0_DISABLE_LINK_ACT 0x00001000
182 #define LED_INTERVAL_SET_MASK 0x00000f00
183 #define LED_INTERVAL_SET_320MS 0x00000500
184 #define LED_INTERVAL_SET_160MS 0x00000400
185 #define LED_INTERVAL_SET_80MS 0x00000300
186 #define LED_INTERVAL_SET_40MS 0x00000200
187 #define LED_INTERVAL_SET_20MS 0x00000100
188 #define LED3_ON 0x00000080
189 #define LED2_ON 0x00000040
190 #define LED1_ON 0x00000020
191 #define LED0_ON 0x00000010
192 #define LED3_ENABLE 0x00000008
193 #define LED2_ENABLE 0x00000004
194 #define LED1_ENABLE 0x00000002
195 #define LED0_ENABLE 0x00000001
197 #define SPI_SLAVE_RESET 0x00010000
198 #define SPI_RESTRICT 0x00000400
199 #define SPI_DELAY_DISABLE 0x00000200
200 #define SPI_PROBE_MUX_SEL_MASK 0x000001e0
201 #define SPI_SER_ADDR_CFG_MASK 0x0000000c
202 #define SPI_MODE 0x00000001
206 #define GPIO ((volatile GpioControl * const) GPIO_BASE)
208 /* Number to mask conversion macro used for GPIODir and GPIOio */
209 #define GPIO_NUM_MAX_BITS_MASK 0x0f
210 #define GPIO_NUM_TO_MASK(X) (1 << ((X) & GPIO_NUM_MAX_BITS_MASK))
213 ** External Bus Interface
215 typedef struct EbiChipSelect {
216 uint32 base; /* base address in upper 24 bits */
217 #define EBI_SIZE_8K 0
218 #define EBI_SIZE_16K 1
219 #define EBI_SIZE_32K 2
220 #define EBI_SIZE_64K 3
221 #define EBI_SIZE_128K 4
222 #define EBI_SIZE_256K 5
223 #define EBI_SIZE_512K 6
224 #define EBI_SIZE_1M 7
225 #define EBI_SIZE_2M 8
226 #define EBI_SIZE_4M 9
227 #define EBI_SIZE_8M 10
228 #define EBI_SIZE_16M 11
229 #define EBI_SIZE_32M 12
230 #define EBI_SIZE_64M 13
231 #define EBI_SIZE_128M 14
232 #define EBI_SIZE_256M 15
234 #define EBI_ENABLE 0x00000001 /* .. enable this range */
235 #define EBI_WAIT_STATES 0x0000000e /* .. mask for wait states */
236 #define EBI_WTST_SHIFT 1 /* .. for shifting wait states */
237 #define EBI_WORD_WIDE 0x00000010 /* .. 16-bit peripheral, else 8 */
238 #define EBI_WREN 0x00000020 /* enable posted writes */
239 #define EBI_POLARITY 0x00000040 /* .. set to invert something,
240 ** don't know what yet */
241 #define EBI_TS_TA_MODE 0x00000080 /* .. use TS/TA mode */
242 #define EBI_TS_SEL 0x00000100 /* .. drive tsize, not bs_b */
243 #define EBI_FIFO 0x00000200 /* .. use fifo */
244 #define EBI_RE 0x00000400 /* .. Reverse Endian */
247 typedef struct MpiRegisters {
248 EbiChipSelect cs[1]; /* size chip select configuration */
251 #define MPI ((volatile MpiRegisters * const) MPI_BASE)