1 /*****************************************************************************/
4 * crt0_ram.S -- startup code for Motorola M5249C3 eval board.
6 * (C) Copyright 1999-2002, Greg Ungerer (gerg@snapgear.com).
9 /*****************************************************************************/
11 #include "linux/autoconf.h"
12 #include "asm/coldfire.h"
13 #include "asm/mcfsim.h"
15 /*****************************************************************************/
18 * Motorola M5249C3 ColdFire eval board, chip select and memory setup.
20 #define MEM_BASE 0x00000000 /* Memory base at address 0 */
21 #define MEM_SIZE 0x00800000 /* Memory size 8MB */
22 #define VBR_BASE MEM_BASE /* Vector address */
24 /*****************************************************************************/
32 /*****************************************************************************/
37 * Set up the usable of RAM stuff. Size of RAM is determined then
38 * an initial stack set up at the end.
49 /*****************************************************************************/
54 * This is the codes first entry point. This is where it all
60 move.w #0x2700, %sr /* No interrupts */
63 * Set MBAR1 and MBAR2, just incase they are not set.
65 move.l #0x10000001, %a0
66 movec %a0, %MBAR /* Map MBAR region */
67 subq.l #1, %a0 /* Get MBAR address in a0 */
69 move.l #0x80000001, %a1
70 movec %a1, #3086 /* Map MBAR2 region */
71 subq.l #1, %a1 /* Get MBAR2 address in a1 */
74 * Move secondary interrupts to base at 128.
77 move.b %d0, 0x16b(%a1) /* Interrupt base register */
81 * Work around broken CSMR0/DRAM vector problem.
83 move.l #0x001F0021, %d0 /* Disable C/I bit */
84 move.l %d0, 0x84(%a0) /* Set CSMR0 */
88 * Disable the PLL firstly. (Who knows what state it is
91 move.l 0x180(%a1), %d0 /* Get current PLL value */
92 and.l #0xfffffffe, %d0 /* PLL bypass first */
93 move.l %d0, 0x180(%a1) /* Set PLL register */
96 #ifdef CONFIG_CLOCK_140MHz
98 * Set initial clock frequency. This assumes M5249C3 board
99 * is fitted with 11.2896MHz crystal. It will program the
100 * PLL for 140MHz. Lets go fast :-)
102 move.l #0x125a40f0, %d0 /* Set for 140MHz */
103 move.l %d0, 0x180(%a1) /* Set PLL register */
105 move.l %d0, 0x180(%a1) /* Set PLL register */
109 * Setup CS1 for ethernet controller.
110 * (Setup as per M5249C3 doco).
112 move.l #0xe0000000, %d0 /* CS1 mapped at 0xe0000000 */
113 move.l %d0, 0x8c(%a0)
114 move.l #0x001f0021, %d0 /* CS1 size of 1Mb */
115 move.l %d0, 0x90(%a0)
116 move.w #0x0080, %d0 /* CS1 = 16bit port, AA */
117 move.w %d0, 0x96(%a0)
120 * Setup CS2 for IDE interface.
122 move.l #0x50000000, %d0 /* CS2 mapped at 0x50000000 */
123 move.l %d0, 0x98(%a0)
124 move.l #0x001f0001, %d0 /* CS2 size of 1MB */
125 move.l %d0, 0x9c(%a0)
126 move.w #0x0080, %d0 /* CS2 = 16bit, TA */
127 move.w %d0, 0xa2(%a0)
129 move.l #0x00107000, %d0 /* IDEconfig1 */
130 move.l %d0, 0x18c(%a1)
131 move.l #0x000c0400, %d0 /* IDEconfig2 */
132 move.l %d0, 0x190(%a1)
134 move.l #0x00080000, %d0 /* GPIO19, IDE reset bit */
135 or.l %d0, 0xc(%a1) /* Function GPIO19 */
136 or.l %d0, 0x8(%a1) /* Enable GPIO19 as output */
137 or.l %d0, 0x4(%a1) /* De-assert IDE reset */
141 * Setup VBR as per eval board (really dBUG does this).
142 * These settings must match it.
144 move.l #VBR_BASE, %a0 /* Note VBR can't be read */
146 move.l %a0, _ramvec /* Set up vector addr */
147 move.l %a0, _rambase /* Set up base RAM addr */
151 * Set the memory size, and then set a temporary stack.
153 move.l #MEM_SIZE, %a0
155 move.l %a0, %d0 /* Mem end addr is in a0 */
156 move.l %d0, %sp /* Set up initial stack ptr */
157 move.l %d0, _ramend /* Set end ram addr */
161 * Enable CPU internal cache.
163 move.l #0x01000000, %d0 /* Invalidate whole cache */
167 move.l #0x0000c000, %d0 /* Set SDRAM cached only */
169 move.l #0x00000000, %d0 /* No other regions cached */
172 move.l #0xa0000200, %d0 /* Enable cache... */
177 #ifdef CONFIG_ROMFS_FS
179 * Move ROM filesystem above bss :-)
181 lea.l _sbss, %a0 /* Get start of bss */
182 lea.l _ebss, %a1 /* Set up destination */
183 move.l %a0, %a2 /* Copy of bss start */
185 move.l 8(%a0), %d0 /* Get size of ROMFS */
186 addq.l #8, %d0 /* Allow for rounding */
187 and.l #0xfffffffc, %d0 /* Whole words */
189 add.l %d0, %a0 /* Copy from end */
190 add.l %d0, %a1 /* Copy from end */
191 move.l %a1, _ramstart /* Set start of ram */
194 move.l -(%a0), %d0 /* Copy dword */
196 cmp.l %a0, %a2 /* Check if at end */
199 #else /* CONFIG_ROMFS_FS */
201 move.l %a1, _ramstart
202 #endif /* CONFIG_ROMFS_FS */
206 * Zero out the bss region.
208 lea.l _sbss, %a0 /* Get start of bss */
209 lea.l _ebss, %a1 /* Get end of bss */
210 clr.l %d0 /* Set value */
212 move.l %d0, (%a0)+ /* Clear each word */
213 cmp.l %a0, %a1 /* Check if at end */
217 * Load the current thread pointer and stack.
219 lea init_thread_union, %a0
223 * Assember start up done, start code proper.
225 jsr start_kernel /* Start Linux kernel */
228 jmp _exit /* Should never get here */
230 /*****************************************************************************/