kernel/linux/arch/ppc/platforms/pcore.c

   1 /*
   2  * arch/ppc/platforms/pcore_setup.c
   3  *
   4  * Setup routines for Force PCORE boards
   5  *
   6  * Author: Matt Porter <mporter@mvista.com>
   7  *
   8  * 2001 (c) MontaVista, Software, Inc.  This file is licensed under
   9  * the terms of the GNU General Public License version 2.  This program
  10  * is licensed "as is" without any warranty of any kind, whether express
  11  * or implied.
  12  */
  13
  14 #include <linux/config.h>
  15 #include <linux/stddef.h>
  16 #include <linux/kernel.h>
  17 #include <linux/init.h>
  18 #include <linux/errno.h>
  19 #include <linux/reboot.h>
  20 #include <linux/pci.h>
  21 #include <linux/kdev_t.h>
  22 #include <linux/types.h>
  23 #include <linux/major.h>
  24 #include <linux/initrd.h>
  25 #include <linux/console.h>
  26 #include <linux/irq.h>
  27 #include <linux/seq_file.h>
  28 #include <linux/root_dev.h>
  29
  30 #include <asm/io.h>
  31 #include <asm/machdep.h>
  32 #include <asm/time.h>
  33 #include <asm/i8259.h>
  34 #include <asm/mpc10x.h>
  35 #include <asm/todc.h>
  36 #include <asm/bootinfo.h>
  37 #include <asm/kgdb.h>
  38
  39 #include "pcore.h"
  40
  41 extern unsigned long loops_per_jiffy;
  42
  43 static int board_type;
  44
  45 static inline int __init
  46 pcore_6750_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
  47 {
  48         static char pci_irq_table[][4] =
  49         /*
  50          *      PCI IDSEL/INTPIN->INTLINE
  51          *      A       B       C       D
  52          */
  53         {
  54                 {9,     10,     11,     12},    /* IDSEL 24 - DEC 21554 */
  55                 {10,    0,      0,      0},     /* IDSEL 25 - DEC 21143 */
  56                 {11,    12,     9,      10},    /* IDSEL 26 - PMC I */
  57                 {12,    9,      10,     11},    /* IDSEL 27 - PMC II */
  58                 {0,     0,      0,      0},     /* IDSEL 28 - unused */
  59                 {0,     0,      9,      0},     /* IDSEL 29 - unused */
  60                 {0,     0,      0,      0},     /* IDSEL 30 - Winbond */
  61                 };
  62         const long min_idsel = 24, max_idsel = 30, irqs_per_slot = 4;
  63         return PCI_IRQ_TABLE_LOOKUP;
  64 };
  65
  66 static inline int __init
  67 pcore_680_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
  68 {
  69         static char pci_irq_table[][4] =
  70         /*
  71          *      PCI IDSEL/INTPIN->INTLINE
  72          *      A       B       C       D
  73          */
  74         {
  75                 {9,     10,     11,     12},    /* IDSEL 24 - Sentinel */
  76                 {10,    0,      0,      0},     /* IDSEL 25 - i82559 #1 */
  77                 {11,    12,     9,      10},    /* IDSEL 26 - PMC I */
  78                 {12,    9,      10,     11},    /* IDSEL 27 - PMC II */
  79                 {9,     0,      0,      0},     /* IDSEL 28 - i82559 #2 */
  80                 {0,     0,      0,      0},     /* IDSEL 29 - unused */
  81                 {0,     0,      0,      0},     /* IDSEL 30 - Winbond */
  82                 };
  83         const long min_idsel = 24, max_idsel = 30, irqs_per_slot = 4;
  84         return PCI_IRQ_TABLE_LOOKUP;
  85 };
  86
  87 void __init
  88 pcore_pcibios_fixup(void)
  89 {
  90         struct pci_dev *dev;
  91
  92         if ((dev = pci_find_device(PCI_VENDOR_ID_WINBOND,
  93                                 PCI_DEVICE_ID_WINBOND_83C553,
  94                                 0)))
  95         {
  96                 /* Reroute interrupts both IDE channels to 15 */
  97                 pci_write_config_byte(dev,
  98                                 PCORE_WINBOND_IDE_INT,
  99                                 0xff);
 100
 101                 /* Route INTA-D to IRQ9-12, respectively */
 102                 pci_write_config_word(dev,
 103                                 PCORE_WINBOND_PCI_INT,
 104                                 0x9abc);
 105
 106                 /*
 107                  * Set up 8259 edge/level triggering
 108                  */
 109                 outb(0x00, PCORE_WINBOND_PRI_EDG_LVL);
 110                 outb(0x1e, PCORE_WINBOND_SEC_EDG_LVL);
 111         }
 112 }
 113
 114 int __init
 115 pcore_find_bridges(void)
 116 {
 117         struct pci_controller* hose;
 118         int host_bridge, board_type;
 119
 120         hose = pcibios_alloc_controller();
 121         if (!hose)
 122                 return 0;
 123
 124         mpc10x_bridge_init(hose,
 125                         MPC10X_MEM_MAP_B,
 126                         MPC10X_MEM_MAP_B,
 127                         MPC10X_MAPB_EUMB_BASE);
 128
 129         /* Determine board type */
 130         early_read_config_dword(hose,
 131                         0,
 132                         PCI_DEVFN(0,0),
 133                         PCI_VENDOR_ID,
 134                         &host_bridge);
 135         if (host_bridge == MPC10X_BRIDGE_106)
 136                 board_type = PCORE_TYPE_6750;
 137         else /* MPC10X_BRIDGE_107 */
 138                 board_type = PCORE_TYPE_680;
 139
 140         hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
 141
 142         ppc_md.pcibios_fixup = pcore_pcibios_fixup;
 143         ppc_md.pci_swizzle = common_swizzle;
 144
 145         if (board_type == PCORE_TYPE_6750)
 146                 ppc_md.pci_map_irq = pcore_6750_map_irq;
 147         else /* PCORE_TYPE_680 */
 148                 ppc_md.pci_map_irq = pcore_680_map_irq;
 149
 150         return board_type;
 151 }
 152
 153 /* Dummy variable to satisfy mpc10x_common.o */
 154 void *OpenPIC_Addr;
 155
 156 static int
 157 pcore_show_cpuinfo(struct seq_file *m)
 158 {
 159         seq_printf(m, "vendor\t\t: Force Computers\n");
 160
 161         if (board_type == PCORE_TYPE_6750)
 162                 seq_printf(m, "machine\t\t: PowerCore 6750\n");
 163         else /* PCORE_TYPE_680 */
 164                 seq_printf(m, "machine\t\t: PowerCore 680\n");
 165
 166         seq_printf(m, "L2\t\t: " );
 167         if (board_type == PCORE_TYPE_6750)
 168                 switch (readb(PCORE_DCCR_REG) & PCORE_DCCR_L2_MASK)
 169                 {
 170                         case PCORE_DCCR_L2_0KB:
 171                                 seq_printf(m, "nocache");
 172                                 break;
 173                         case PCORE_DCCR_L2_256KB:
 174                                 seq_printf(m, "256KB");
 175                                 break;
 176                         case PCORE_DCCR_L2_1MB:
 177                                 seq_printf(m, "1MB");
 178                                 break;
 179                         case PCORE_DCCR_L2_512KB:
 180                                 seq_printf(m, "512KB");
 181                                 break;
 182                         default:
 183                                 seq_printf(m, "error");
 184                                 break;
 185                 }
 186         else /* PCORE_TYPE_680 */
 187                 switch (readb(PCORE_DCCR_REG) & PCORE_DCCR_L2_MASK)
 188                 {
 189                         case PCORE_DCCR_L2_2MB:
 190                                 seq_printf(m, "2MB");
 191                                 break;
 192                         case PCORE_DCCR_L2_256KB:
 193                                 seq_printf(m, "reserved");
 194                                 break;
 195                         case PCORE_DCCR_L2_1MB:
 196                                 seq_printf(m, "1MB");
 197                                 break;
 198                         case PCORE_DCCR_L2_512KB:
 199                                 seq_printf(m, "512KB");
 200                                 break;
 201                         default:
 202                                 seq_printf(m, "error");
 203                                 break;
 204                 }
 205
 206         seq_printf(m, "\n");
 207
 208         return 0;
 209 }
 210
 211 static void __init
 212 pcore_setup_arch(void)
 213 {
 214         /* init to some ~sane value until calibrate_delay() runs */
 215         loops_per_jiffy = 50000000/HZ;
 216
 217         /* Lookup PCI host bridges */
 218         board_type = pcore_find_bridges();
 219
 220 #ifdef CONFIG_BLK_DEV_INITRD
 221         if (initrd_start)
 222                 ROOT_DEV = Root_RAM0;
 223         else
 224 #endif
 225 #ifdef CONFIG_ROOT_NFS
 226                 ROOT_DEV = Root_NFS;
 227 #else
 228                 ROOT_DEV = Root_SDA2;
 229 #endif
 230
 231 #ifdef CONFIG_DUMMY_CONSOLE
 232         conswitchp = &dummy_con;
 233 #endif
 234
 235         printk(KERN_INFO "Force PowerCore ");
 236         if (board_type == PCORE_TYPE_6750)
 237                 printk("6750\n");
 238         else
 239                 printk("680\n");
 240         printk(KERN_INFO "Port by MontaVista Software, Inc. (source@mvista.com)\n");
 241         _set_L2CR(L2CR_L2E | _get_L2CR());
 242
 243 }
 244
 245 static void
 246 pcore_restart(char *cmd)
 247 {
 248         local_irq_disable();
 249         /* Hard reset */
 250         writeb(0x11, 0xfe000332);
 251         while(1);
 252 }
 253
 254 static void
 255 pcore_halt(void)
 256 {
 257         local_irq_disable();
 258         /* Turn off user LEDs */
 259         writeb(0x00, 0xfe000300);
 260         while (1);
 261 }
 262
 263 static void
 264 pcore_power_off(void)
 265 {
 266         pcore_halt();
 267 }
 268
 269
 270 static void __init
 271 pcore_init_IRQ(void)
 272 {
 273         int i;
 274
 275         for ( i = 0 ; i < 16 ; i++ )
 276                 irq_desc[i].handler = &i8259_pic;
 277
 278         i8259_init(0);
 279 }
 280
 281 /*
 282  * Set BAT 3 to map 0xf0000000 to end of physical memory space.
 283  */
 284 static __inline__ void
 285 pcore_set_bat(void)
 286 {
 287         mb();
 288         mtspr(DBAT3U, 0xf0001ffe);
 289         mtspr(DBAT3L, 0xfe80002a);
 290         mb();
 291
 292 }
 293
 294 static unsigned long __init
 295 pcore_find_end_of_memory(void)
 296 {
 297
 298         return mpc10x_get_mem_size(MPC10X_MEM_MAP_B);
 299 }
 300
 301 static void __init
 302 pcore_map_io(void)
 303 {
 304         io_block_mapping(0xfe000000, 0xfe000000, 0x02000000, _PAGE_IO);
 305 }
 306
 307 TODC_ALLOC();
 308
 309 void __init
 310 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
 311                 unsigned long r6, unsigned long r7)
 312 {
 313         parse_bootinfo(find_bootinfo());
 314
 315         /* Cover I/O space with a BAT */
 316         /* yuck, better hope your ram size is a power of 2  -- paulus */
 317         pcore_set_bat();
 318
 319         isa_io_base = MPC10X_MAPB_ISA_IO_BASE;
 320         isa_mem_base = MPC10X_MAPB_ISA_MEM_BASE;
 321         pci_dram_offset = MPC10X_MAPB_DRAM_OFFSET;
 322
 323         ppc_md.setup_arch       = pcore_setup_arch;
 324         ppc_md.show_cpuinfo     = pcore_show_cpuinfo;
 325         ppc_md.init_IRQ         = pcore_init_IRQ;
 326         ppc_md.get_irq          = i8259_irq;
 327
 328         ppc_md.find_end_of_memory = pcore_find_end_of_memory;
 329         ppc_md.setup_io_mappings = pcore_map_io;
 330
 331         ppc_md.restart          = pcore_restart;
 332         ppc_md.power_off        = pcore_power_off;
 333         ppc_md.halt             = pcore_halt;
 334
 335         TODC_INIT(TODC_TYPE_MK48T59,
 336                   PCORE_NVRAM_AS0,
 337                   PCORE_NVRAM_AS1,
 338                   PCORE_NVRAM_DATA,
 339                   8);
 340
 341         ppc_md.time_init        = todc_time_init;
 342         ppc_md.get_rtc_time     = todc_get_rtc_time;
 343         ppc_md.set_rtc_time     = todc_set_rtc_time;
 344         ppc_md.calibrate_decr   = todc_calibrate_decr;
 345
 346         ppc_md.nvram_read_val   = todc_m48txx_read_val;
 347         ppc_md.nvram_write_val  = todc_m48txx_write_val;
 348
 349 #ifdef CONFIG_SERIAL_TEXT_DEBUG
 350         ppc_md.progress = gen550_progress;
 351 #endif
 352 #ifdef CONFIG_KGDB
 353         ppc_md.kgdb_map_scc = gen550_kgdb_map_scc;
 354 #endif
 355 }