version 4.2.0

[fx2fw-sdcc] / fx2 / syncdelay.h

diff --git a/fx2/syncdelay.h b/fx2/syncdelay.h
index 178f316..3293fd9 100644 (file)
--- a/fx2/syncdelay.h
+++ b/fx2/syncdelay.h
@@ -1,128 +1,64 @@
 /* -*- c++ -*- */\r
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 /*-----------------------------------------------------------------------------\r
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  * Synchronization delay for FX2 access to specific registers\r
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  *-----------------------------------------------------------------------------\r
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  * Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2,\r
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  * Copyright 2003 Free Software Foundation, Inc.\r
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  *-----------------------------------------------------------------------------\r
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  * This code is part of usbjtag. usbjtag is free software; you can redistribute\r
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  * it and/or modify it under the terms of the GNU General Public License as\r
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  * published by the Free Software Foundation; either version 2 of the License,\r
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  * or (at your option) any later version. usbjtag is distributed in the hope\r
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  * that it will be useful, but WITHOUT ANY WARRANTY; without even the implied\r
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  * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r
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  * GNU General Public License for more details.  You should have received a\r
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  * copy of the GNU General Public License along with this program in the file\r
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  * COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin\r
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  * St, Fifth Floor, Boston, MA  02110-1301  USA\r
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  *-----------------------------------------------------------------------------\r
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  */\r
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 #ifndef _SYNCDELAY_H_\r
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 #define _SYNCDELAY_H_\r
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 /*\r
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  * Magic delay required between access to certain xdata registers (TRM page 15-106).\r
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  * For our configuration, 48 MHz FX2 / 48 MHz IFCLK, we need three cycles.  Each\r
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  * NOP is a single cycle....\r
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  *\r
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  * From TRM page 15-105:\r
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  *\r
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  * Under certain conditions, some read and write access to the FX2 registers must\r
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  * be separated by a "synchronization delay".  The delay is necessary only under the\r
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  * following conditions:\r
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  *\r
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  *   - between a write to any register in the 0xE600 - 0xE6FF range and a write to one\r
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  *     of the registers listed below.\r
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  *\r
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  *   - between a write to one of the registers listed below and a read from any register\r
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  *     in the 0xE600 - 0xE6FF range.\r
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  *\r
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  *   Registers which require a synchronization delay:\r
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  *\r
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  *     FIFORESET                       FIFOPINPOLAR\r
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  *     INPKTEND                        EPxBCH:L\r
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  *     EPxFIFOPFH:L                    EPxAUTOINLENH:L\r
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  *     EPxFIFOCFG                      EPxGPIFFLGSEL\r
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  *     PINFLAGSAB                      PINFLAGSCD\r
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  *     EPxFIFOIE                       EPxFIFOIRQ\r
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  *     GPIFIE                          GPIFIRQ\r
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  *     UDMACRCH:L                      GPIFADRH:L\r
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  *     GPIFTRIG                        EPxGPIFTRIG\r
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  *     OUTPKTEND                       REVCTL\r
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  *     GPIFTCB3                        GPIFTCB2\r
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  *     GPIFTCB1                        GPIFTCB0\r
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  */\r
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 /*\r
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  * FIXME ensure that the peep hole optimizer isn't screwing us\r
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  */\r
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 #define        SYNCDELAY       _asm nop; nop; nop; _endasm\r
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 #define        NOP             _asm nop; _endasm\r
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 #endif /* _SYNCDELAY_H_ */\r
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