MSP430 test cases, stable poking of RAM.

Test cases pass with GoodFET12 and BadFET20!

git-svn-id: https://svn.code.sf.net/p/goodfet/code/trunk@168 12e2690d-a6be-4b82-a7b7-67c4a43b65c8

diff --git a/client/GoodFETMSP430.py b/client/GoodFETMSP430.py
index 7ad26d2..43612fa 100644 (file)
--- a/client/GoodFETMSP430.py
+++ b/client/GoodFETMSP430.py
@@ -139,18 +139,39 @@ class GoodFETMSP430(GoodFET):
         """Test MSP430 JTAG.  Requires that a chip be attached."""
         if self.MSP430ident()==0xffff:
             print "Is anything connected?";
-        print "Testing RAM from 1c00 to 1d00.";
-        for a in range(0x1c00,0x1d00):
+        print "Testing RAM from 200 to 210.";
+        for a in range(0x200,0x210):
             self.MSP430poke(a,0);
             if(self.MSP430peek(a)!=0):
                 print "Fault at %06x" % a;
             self.MSP430poke(a,0xffff);
             if(self.MSP430peek(a)!=0xffff):
                 print "Fault at %06x" % a;
-        print "RAM Test Complete."
-        for a in range(1,5):
-            print "Identity %04x" % self.MSP430ident();
-            
+                
+        print "Testing identity consistency."
+        ident=self.MSP430ident();
+        for a in range(1,20):
+            ident2=self.MSP430ident();
+            if ident!=ident2:
+                print "Identity %04x!=%04x" % (ident,ident2);
+        
+        print "Testing flash erase."
+        self.MSP430masserase();
+        for a in range(0xffe0, 0xffff):
+            if self.MSP430peek(a)!=0xffff:
+                print "%04x unerased, equals %04x" % (
+                    a, self.MSP430peek(a));
+
+        print "Testing flash write."
+        for a in range(0xffe0, 0xffff):
+            self.MSP430pokeflash(a,0xbeef);
+            if self.MSP430peek(a)!=0xbeef:
+                print "%04x unset, equals %04x" % (
+                    a, self.MSP430peek(a));
+        
+        print "Tests complete, erasing."
+        self.MSP430masserase();
+        
     def MSP430flashtest(self):
         self.MSP430masserase();
         i=0x2500;

diff --git a/firmware/apps/jtag/jtag430.c b/firmware/apps/jtag/jtag430.c
index ce4e7b6..6913626 100644 (file)
--- a/firmware/apps/jtag/jtag430.c
+++ b/firmware/apps/jtag/jtag430.c
@@ -54,7 +54,6 @@ unsigned int jtag430_readmem(unsigned int adr){
   unsigned int toret;
   jtag430_haltcpu();
   
-  
   CLRTCLK;
   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
   
@@ -339,6 +338,7 @@ void jtag430handle(unsigned char app,
     break;
   case JTAG430_WRITEMEM:
   case POKE:
+    jtag430_haltcpu();
     jtag430_writemem(cmddataword[0],cmddataword[2]);
     cmddataword[0]=jtag430_readmem(cmddataword[0]);
     txdata(app,verb,2);
@@ -356,6 +356,7 @@ void jtag430handle(unsigned char app,
     txdata(app,verb,0);
     break;
   case JTAG430_SETPC:
+    jtag430_haltcpu();
     jtag430_setpc(cmddataword[0]);
     txdata(app,verb,0);
     break;

diff --git a/firmware/apps/jtag/jtag430asm.S b/firmware/apps/jtag/jtag430asm.S
index e9fa6f5..39dcb8f 100644 (file)
--- a/firmware/apps/jtag/jtag430asm.S
+++ b/firmware/apps/jtag/jtag430asm.S
@@ -1,16 +1,48 @@
 .globl jtag430_tclk_flashpulses
 .type jtag430_tclk_flashpulses,@function //for linking
 
-
-//! At 3.68MHz, 7 to 14 cycles/loop are allowed for 257 to 475kHz
+//This detects model, chooses appropriate timing.
 jtag430_tclk_flashpulses:
+       mov &0x0ff0, r14
+       cmp  #0x6cf1, r14       ;Is the chip an MSP430F1xx?
+       jz jtag430_tclk_flashpulses_3mhz
+       jmp jtag430_tclk_flashpulses_16mhz
+       
+// At 3.68MHz, 7 to 14 cycles/loop are allowed for 257 to 475kHz.
+// At 16MHz, 33 to 62 cycles/loop are allowed.
+jtag430_tclk_flashpulses_3mhz:
        mov #0x0031, r14
-pulseloop:     
+pulseloop3:    
        bis.b #2, @r14          ;SETTCLK, 3 cycles
        sub #1, r15             ; 1 cycle
        ;;  1+3+3+1+2=10, within limits
        bic.b #2, @r14          ;CLRTCLK, 3 cycles
        tst r15                 ; 1 cycle
-       jnz pulseloop           ; 2 cycles
+       jnz pulseloop3          ; 2 cycles
+       ret
+
+jtag430_tclk_flashpulses_16mhz:
+       mov #0x0031, r14
+pulseloop16:   
+       bis.b #2, @r14          ;SETTCLK, 3 cycles
+       sub #1, r15             ; 1 cycle
+       ;;  1+3+3+1+2=10, beneath limits,
+
+       ;; +3+2=5, repeat 5 times to get 10+25=35, within limits
+       push r11                ; 3 cycles
+       pop r11                 ; 2 cycles
+       push r11                ; 3 cycles
+       pop r11                 ; 2 cycles
+       push r11                ; 3 cycles
+       pop r11                 ; 2 cycles
+       push r11                ; 3 cycles
+       pop r11                 ; 2 cycles
+       push r11                ; 3 cycles
+       pop r11                 ; 2 cycles
+       
+       
+       bic.b #2, @r14          ;CLRTCLK, 3 cycles
+       tst r15                 ; 1 cycle
+       jnz pulseloop16         ; 2 cycles
        ret