1 Documentation for arch/ppc/kernel/*_common.c
2 ============================================
4 Author: Mark A. Greer (mgreer@mvista.com)
9 To make board ports easier and less error prone, some common host bridge files
10 have been developed. So far, these files have been developed:
17 The routines in this file are for the Motorola MCG PowerPlus architecture
18 boards which have a Falcon/Raven or Hawk memory controller/host bridge.
20 - 'pplus_init()' completely reconfigures the PCI and MPIC physical mappings
21 and maps the MPIC registers into virtual memory.
22 - 'pplus_mpic_init()' simply maps the MPIC registers into virtual memory from
23 where they are currently mapped in the physical address space.
24 - 'pplus_get_mem_size()' reads the memory controller's registers to determine
25 the amount of main memory in the system. This assumes that the firmware has
26 correctly initialized the memory controller.
28 For examples, look at arch/ppc/kernel/mcpn765_*.c and prpmc750_setup.c.
34 The routines in this file are board using the Motorola SPS MPC106/107/8240
35 host bridges (the MPC8240 is a 603e processor core with a MPC170-like host
38 - 'mpc10x_bridge_init()' allows you to switch memory maps (e.g, switch from MAP
39 A to MAP B), automatically initializes many variables with the proper values,
40 moves the EUMB to a reasonable place in physical memory (assuming that
41 'ioremap_base' is correct), and maps the EPIC registers into virtual memory.
42 - 'mpc10x_get_mem_size(()' reads the memory controller's registers to determine
43 the amount of main memory in the system. This assumes that the firmware has
44 correctly initialized the memory controller.
46 For examples, look at arch/ppc/kernel/sandpoint_*.c and menf1_*.c.
49 Before calling any of the routines listed above, you must ensure that there is
50 a 1-to-1 BAT mapping for the areas of physical memory that will be accessed.
52 If you encounter problems, please email me at mgreer@mvista.com