drivers/i2c/i2c-algo-8xx.c

   1 /*
   2  * i2c-algo-8xx.c i2x driver algorithms for MPC8XX CPM
   3  * Copyright (c) 1999 Dan Malek (dmalek@jlc.net).
   4  *
   5     This program is free software; you can redistribute it and/or modify
   6     it under the terms of the GNU General Public License as published by
   7     the Free Software Foundation; either version 2 of the License, or
   8     (at your option) any later version.
   9
  10     This program is distributed in the hope that it will be useful,
  11     but WITHOUT ANY WARRANTY; without even the implied warranty of
  12     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13     GNU General Public License for more details.
  14
  15     You should have received a copy of the GNU General Public License
  16     along with this program; if not, write to the Free Software
  17     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18  *
  19  * moved into proper i2c interface; separated out platform specific
  20  * parts into i2c-rpx.c
  21  * Brad Parker (brad@heeltoe.com)
  22  */
  23
  24 // XXX todo
  25 // timeout sleep?
  26
  27 /* $Id: i2c-algo-8xx.c,v 1.1.1.1 2005/04/11 02:50:21 jack Exp $ */
  28
  29 #include <linux/kernel.h>
  30 #include <linux/module.h>
  31 #include <linux/delay.h>
  32 #include <linux/slab.h>
  33 #include <linux/version.h>
  34 #include <linux/init.h>
  35 #include <asm/uaccess.h>
  36 #include <linux/ioport.h>
  37 #include <linux/errno.h>
  38 #include <linux/sched.h>
  39
  40 #include <asm/mpc8xx.h>
  41 #include <asm/commproc.h>
  42
  43 #include <linux/i2c.h>
  44 #include <linux/i2c-algo-8xx.h>
  45
  46 #define CPM_MAX_READ    513
  47 /* #define I2C_CHIP_ERRATA */ /* Try uncomment this if you have an older CPU(earlier than rev D4) */
  48 static wait_queue_head_t iic_wait;
  49 static ushort r_tbase, r_rbase;
  50
  51 int cpm_scan = 0;
  52 int cpm_debug = 0;
  53
  54 static  void
  55 cpm_iic_interrupt(void *dev_id, struct pt_regs *regs)
  56 {
  57         volatile i2c8xx_t *i2c = (i2c8xx_t *)dev_id;
  58         if (cpm_debug > 1)
  59                 printk("cpm_iic_interrupt(dev_id=%p)\n", dev_id);
  60 #if 0
  61         /* Chip errata, clear enable. This is not needed on rev D4 CPUs */
  62         /* This should probably be removed and replaced by I2C_CHIP_ERRATA stuff */
  63         /* Someone with a buggy CPU needs to confirm that */
  64         i2c->i2c_i2mod &= ~1;
  65 #endif
  66         /* Clear interrupt.
  67         */
  68         i2c->i2c_i2cer = 0xff;
  69
  70         /* Get 'me going again.
  71         */
  72         wake_up_interruptible(&iic_wait);
  73 }
  74
  75 static void
  76 cpm_iic_init(struct i2c_algo_8xx_data *cpm_adap)
  77 {
  78         volatile iic_t          *iip = cpm_adap->iip;
  79         volatile i2c8xx_t       *i2c = cpm_adap->i2c;
  80         unsigned char brg;
  81         bd_t *bd = (bd_t *)__res;
  82
  83         if (cpm_debug) printk(KERN_DEBUG "cpm_iic_init()\n");
  84
  85         /* Initialize the parameter ram.
  86          * We need to make sure many things are initialized to zero,
  87          * especially in the case of a microcode patch.
  88          */
  89         iip->iic_rstate = 0;
  90         iip->iic_rdp = 0;
  91         iip->iic_rbptr = 0;
  92         iip->iic_rbc = 0;
  93         iip->iic_rxtmp = 0;
  94         iip->iic_tstate = 0;
  95         iip->iic_tdp = 0;
  96         iip->iic_tbptr = 0;
  97         iip->iic_tbc = 0;
  98         iip->iic_txtmp = 0;
  99
 100         /* Set up the IIC parameters in the parameter ram.
 101         */
 102         iip->iic_tbase = r_tbase = cpm_adap->dp_addr;
 103         iip->iic_rbase = r_rbase = cpm_adap->dp_addr + sizeof(cbd_t)*2;
 104
 105         iip->iic_tfcr = SMC_EB;
 106         iip->iic_rfcr = SMC_EB;
 107
 108         /* Set maximum receive size.
 109         */
 110         iip->iic_mrblr = CPM_MAX_READ;
 111
 112         /* Initialize Tx/Rx parameters.
 113         */
 114         if (cpm_adap->reloc == 0) {
 115                 volatile cpm8xx_t *cp = cpm_adap->cp;
 116
 117                 cp->cp_cpcr =
 118                         mk_cr_cmd(CPM_CR_CH_I2C, CPM_CR_INIT_TRX) | CPM_CR_FLG;
 119                 while (cp->cp_cpcr & CPM_CR_FLG);
 120         } else {
 121                 iip->iic_rbptr = iip->iic_rbase;
 122                 iip->iic_tbptr = iip->iic_tbase;
 123                 iip->iic_rstate = 0;
 124                 iip->iic_tstate = 0;
 125         }
 126
 127         /* Select an arbitrary address.  Just make sure it is unique.
 128         */
 129         i2c->i2c_i2add = 0xfe;
 130
 131         /* Make clock run at 60 KHz.
 132         */
 133         brg = (unsigned char) (bd->bi_intfreq/(32*2*60000) -3);
 134         i2c->i2c_i2brg = brg;
 135
 136         i2c->i2c_i2mod = 0x00;
 137         i2c->i2c_i2com = 0x01; /* Master mode */
 138
 139         /* Disable interrupts.
 140         */
 141         i2c->i2c_i2cmr = 0;
 142         i2c->i2c_i2cer = 0xff;
 143
 144         init_waitqueue_head(&iic_wait);
 145
 146         /* Install interrupt handler.
 147         */
 148         if (cpm_debug) {
 149                 printk ("%s[%d] Install ISR for IRQ %d\n",
 150                         __func__,__LINE__, CPMVEC_I2C);
 151         }
 152         (*cpm_adap->setisr)(CPMVEC_I2C, cpm_iic_interrupt, (void *)i2c);
 153 }
 154
 155
 156 static int
 157 cpm_iic_shutdown(struct i2c_algo_8xx_data *cpm_adap)
 158 {
 159         volatile i2c8xx_t *i2c = cpm_adap->i2c;
 160
 161         /* Shut down IIC.
 162         */
 163         i2c->i2c_i2mod &= ~1;
 164         i2c->i2c_i2cmr = 0;
 165         i2c->i2c_i2cer = 0xff;
 166
 167         return(0);
 168 }
 169
 170 static void
 171 cpm_reset_iic_params(volatile iic_t *iip)
 172 {
 173         iip->iic_tbase = r_tbase;
 174         iip->iic_rbase = r_rbase;
 175
 176         iip->iic_tfcr = SMC_EB;
 177         iip->iic_rfcr = SMC_EB;
 178
 179         iip->iic_mrblr = CPM_MAX_READ;
 180
 181         iip->iic_rstate = 0;
 182         iip->iic_rdp = 0;
 183         iip->iic_rbptr = iip->iic_rbase;
 184         iip->iic_rbc = 0;
 185         iip->iic_rxtmp = 0;
 186         iip->iic_tstate = 0;
 187         iip->iic_tdp = 0;
 188         iip->iic_tbptr = iip->iic_tbase;
 189         iip->iic_tbc = 0;
 190         iip->iic_txtmp = 0;
 191 }
 192
 193 #define BD_SC_NAK               ((ushort)0x0004) /* NAK - did not respond */
 194 #define BD_SC_OV                ((ushort)0x0002) /* OV - receive overrun */
 195 #define CPM_CR_CLOSE_RXBD       ((ushort)0x0007)
 196
 197 static void force_close(struct i2c_algo_8xx_data *cpm)
 198 {
 199         volatile i2c8xx_t *i2c = cpm->i2c;
 200         if (cpm->reloc == 0) { /* micro code disabled */
 201                 volatile cpm8xx_t *cp = cpm->cp;
 202
 203                 if (cpm_debug) printk("force_close()\n");
 204                 cp->cp_cpcr =
 205                         mk_cr_cmd(CPM_CR_CH_I2C, CPM_CR_CLOSE_RXBD) |
 206                         CPM_CR_FLG;
 207
 208                 while (cp->cp_cpcr & CPM_CR_FLG);
 209         }
 210         i2c->i2c_i2cmr = 0x00;  /* Disable all interrupts */
 211         i2c->i2c_i2cer = 0xff;
 212 }
 213
 214
 215 /* Read from IIC...
 216  * abyte = address byte, with r/w flag already set
 217  */
 218 static int
 219 cpm_iic_read(struct i2c_algo_8xx_data *cpm, u_char abyte, char *buf, int count)
 220 {
 221         volatile iic_t *iip = cpm->iip;
 222         volatile i2c8xx_t *i2c = cpm->i2c;
 223         volatile cpm8xx_t *cp = cpm->cp;
 224         volatile cbd_t  *tbdf, *rbdf;
 225         u_char *tb;
 226         unsigned long flags, tmo;
 227
 228         if (count >= CPM_MAX_READ)
 229                 return -EINVAL;
 230
 231         /* check for and use a microcode relocation patch */
 232         if (cpm->reloc) {
 233                 cpm_reset_iic_params(iip);
 234         }
 235
 236         tbdf = (cbd_t *)&cp->cp_dpmem[iip->iic_tbase];
 237         rbdf = (cbd_t *)&cp->cp_dpmem[iip->iic_rbase];
 238
 239         /* To read, we need an empty buffer of the proper length.
 240          * All that is used is the first byte for address, the remainder
 241          * is just used for timing (and doesn't really have to exist).
 242          */
 243         tb = cpm->temp;
 244         tb = (u_char *)(((uint)tb + 15) & ~15);
 245         tb[0] = abyte;          /* Device address byte w/rw flag */
 246
 247         flush_dcache_range((unsigned long) tb, (unsigned long) (tb+1));
 248
 249         if (cpm_debug) printk("cpm_iic_read(abyte=0x%x)\n", abyte);
 250
 251         tbdf->cbd_bufaddr = __pa(tb);
 252         tbdf->cbd_datlen = count + 1;
 253         tbdf->cbd_sc =
 254                 BD_SC_READY | BD_SC_LAST |
 255                 BD_SC_WRAP | BD_IIC_START;
 256
 257         iip->iic_mrblr = count +1; /* prevent excessive read, +1
 258                                       is needed otherwise will the
 259                                       RXB interrupt come too early */
 260
 261         /* flush will invalidate too. */
 262         flush_dcache_range((unsigned long) buf, (unsigned long) (buf+count));
 263
 264         rbdf->cbd_datlen = 0;
 265         rbdf->cbd_bufaddr = __pa(buf);
 266         rbdf->cbd_sc = BD_SC_EMPTY | BD_SC_WRAP| BD_SC_INTRPT;
 267         if(count > 16){
 268                 /* Chip bug, set enable here */
 269                 local_irq_save(flags);
 270                 i2c->i2c_i2cmr = 0x13;  /* Enable some interupts */
 271                 i2c->i2c_i2cer = 0xff;
 272                 i2c->i2c_i2mod |= 1;    /* Enable */
 273                 i2c->i2c_i2com |= 0x80; /* Begin transmission */
 274
 275                 /* Wait for IIC transfer */
 276                 tmo = interruptible_sleep_on_timeout(&iic_wait,1*HZ);
 277                 local_irq_restore(flags);
 278         } else { /* busy wait for small transfers, its faster */
 279                 i2c->i2c_i2cmr = 0x00;  /* Disable I2C interupts */
 280                 i2c->i2c_i2cer = 0xff;
 281                 i2c->i2c_i2mod |= 1;    /* Enable */
 282                 i2c->i2c_i2com |= 0x80; /* Begin transmission */
 283                 tmo = jiffies + 1*HZ;
 284                 while(!(i2c->i2c_i2cer & 0x11 || time_after(jiffies, tmo))); /* Busy wait, with a timeout */
 285         }
 286
 287         if (signal_pending(current) || !tmo){
 288                 force_close(cpm);
 289                 if(cpm_debug)
 290                         printk("IIC read: timeout!\n");
 291                 return -EIO;
 292         }
 293 #ifdef I2C_CHIP_ERRATA
 294         /* Chip errata, clear enable. This is not needed on rev D4 CPUs.
 295          Disabling I2C too early may cause too short stop condition */
 296         udelay(4);
 297         i2c->i2c_i2mod &= ~1;
 298 #endif
 299         if (cpm_debug) {
 300                 printk("tx sc %04x, rx sc %04x\n",
 301                        tbdf->cbd_sc, rbdf->cbd_sc);
 302         }
 303
 304         if (tbdf->cbd_sc & BD_SC_READY) {
 305                 printk("IIC read; complete but tbuf ready\n");
 306                 force_close(cpm);
 307                 printk("tx sc %04x, rx sc %04x\n",
 308                        tbdf->cbd_sc, rbdf->cbd_sc);
 309         }
 310
 311         if (tbdf->cbd_sc & BD_SC_NAK) {
 312                 if (cpm_debug)
 313                         printk("IIC read; no ack\n");
 314                 return -EREMOTEIO;
 315         }
 316
 317         if (rbdf->cbd_sc & BD_SC_EMPTY) {
 318                 /* force_close(cpm); */
 319                 if (cpm_debug){
 320                         printk("IIC read; complete but rbuf empty\n");
 321                         printk("tx sc %04x, rx sc %04x\n",
 322                                tbdf->cbd_sc, rbdf->cbd_sc);
 323                 }
 324                 return -EREMOTEIO;
 325         }
 326
 327         if (rbdf->cbd_sc & BD_SC_OV) {
 328                 if (cpm_debug)
 329                         printk("IIC read; Overrun\n");
 330                 return -EREMOTEIO;;
 331         }
 332
 333         if (cpm_debug) printk("read %d bytes\n", rbdf->cbd_datlen);
 334
 335         if (rbdf->cbd_datlen < count) {
 336                 if (cpm_debug)
 337                         printk("IIC read; short, wanted %d got %d\n",
 338                                count, rbdf->cbd_datlen);
 339                 return 0;
 340         }
 341
 342         return count;
 343 }
 344
 345 /* Write to IIC...
 346  * addr = address byte, with r/w flag already set
 347  */
 348 static int
 349 cpm_iic_write(struct i2c_algo_8xx_data *cpm, u_char abyte, char *buf,int count)
 350 {
 351         volatile iic_t *iip = cpm->iip;
 352         volatile i2c8xx_t *i2c = cpm->i2c;
 353         volatile cpm8xx_t *cp = cpm->cp;
 354         volatile cbd_t  *tbdf;
 355         u_char *tb;
 356         unsigned long flags, tmo;
 357
 358         /* check for and use a microcode relocation patch */
 359         if (cpm->reloc) {
 360                 cpm_reset_iic_params(iip);
 361         }
 362         tb = cpm->temp;
 363         tb = (u_char *)(((uint)tb + 15) & ~15);
 364         *tb = abyte;            /* Device address byte w/rw flag */
 365
 366         flush_dcache_range((unsigned long) tb, (unsigned long) (tb+1));
 367         flush_dcache_range((unsigned long) buf, (unsigned long) (buf+count));
 368
 369         if (cpm_debug) printk("cpm_iic_write(abyte=0x%x)\n", abyte);
 370
 371         /* set up 2 descriptors */
 372         tbdf = (cbd_t *)&cp->cp_dpmem[iip->iic_tbase];
 373
 374         tbdf[0].cbd_bufaddr = __pa(tb);
 375         tbdf[0].cbd_datlen = 1;
 376         tbdf[0].cbd_sc = BD_SC_READY | BD_IIC_START;
 377
 378         tbdf[1].cbd_bufaddr = __pa(buf);
 379         tbdf[1].cbd_datlen = count;
 380         tbdf[1].cbd_sc = BD_SC_READY | BD_SC_INTRPT | BD_SC_LAST | BD_SC_WRAP;
 381
 382         if(count > 16){
 383                 /* Chip bug, set enable here */
 384                 local_irq_save(flags);
 385                 i2c->i2c_i2cmr = 0x13;  /* Enable some interupts */
 386                 i2c->i2c_i2cer = 0xff;
 387                 i2c->i2c_i2mod |= 1;    /* Enable */
 388                 i2c->i2c_i2com |= 0x80; /* Begin transmission */
 389
 390                 /* Wait for IIC transfer */
 391                 tmo = interruptible_sleep_on_timeout(&iic_wait,1*HZ);
 392                 local_irq_restore(flags);
 393         } else {  /* busy wait for small transfers, its faster */
 394                 i2c->i2c_i2cmr = 0x00;  /* Disable I2C interupts */
 395                 i2c->i2c_i2cer = 0xff;
 396                 i2c->i2c_i2mod |= 1;    /* Enable */
 397                 i2c->i2c_i2com |= 0x80; /* Begin transmission */
 398                 tmo = jiffies + 1*HZ;
 399                 while(!(i2c->i2c_i2cer & 0x12 || time_after(jiffies, tmo))); /* Busy wait, with a timeout */
 400         }
 401
 402         if (signal_pending(current) || !tmo){
 403                 force_close(cpm);
 404                 if(cpm_debug && !tmo)
 405                         printk("IIC write: timeout!\n");
 406                 return -EIO;
 407         }
 408
 409 #if I2C_CHIP_ERRATA
 410         /* Chip errata, clear enable. This is not needed on rev D4 CPUs.
 411          Disabling I2C too early may cause too short stop condition */
 412         udelay(4);
 413         i2c->i2c_i2mod &= ~1;
 414 #endif
 415         if (cpm_debug) {
 416                 printk("tx0 sc %04x, tx1 sc %04x\n",
 417                        tbdf[0].cbd_sc, tbdf[1].cbd_sc);
 418         }
 419
 420         if (tbdf->cbd_sc & BD_SC_NAK) {
 421                 if (cpm_debug)
 422                         printk("IIC write; no ack\n");
 423                 return 0;
 424         }
 425
 426         if (tbdf->cbd_sc & BD_SC_READY) {
 427                 if (cpm_debug)
 428                         printk("IIC write; complete but tbuf ready\n");
 429                 return 0;
 430         }
 431
 432         return count;
 433 }
 434
 435 /* See if an IIC address exists..
 436  * addr = 7 bit address, unshifted
 437  */
 438 static int
 439 cpm_iic_tryaddress(struct i2c_algo_8xx_data *cpm, int addr)
 440 {
 441         volatile iic_t *iip = cpm->iip;
 442         volatile i2c8xx_t *i2c = cpm->i2c;
 443         volatile cpm8xx_t *cp = cpm->cp;
 444         volatile cbd_t *tbdf, *rbdf;
 445         u_char *tb;
 446         unsigned long flags, len, tmo;
 447
 448         if (cpm_debug > 1)
 449                 printk("cpm_iic_tryaddress(cpm=%p,addr=%d)\n", cpm, addr);
 450
 451         /* check for and use a microcode relocation patch */
 452         if (cpm->reloc) {
 453                 cpm_reset_iic_params(iip);
 454         }
 455
 456         if (cpm_debug && addr == 0) {
 457                 printk("iip %p, dp_addr 0x%x\n", cpm->iip, cpm->dp_addr);
 458                 printk("iic_tbase %d, r_tbase %d\n", iip->iic_tbase, r_tbase);
 459         }
 460
 461         tbdf = (cbd_t *)&cp->cp_dpmem[iip->iic_tbase];
 462         rbdf = (cbd_t *)&cp->cp_dpmem[iip->iic_rbase];
 463
 464         tb = cpm->temp;
 465         tb = (u_char *)(((uint)tb + 15) & ~15);
 466
 467         /* do a simple read */
 468         tb[0] = (addr << 1) | 1;        /* device address (+ read) */
 469         len = 2;
 470
 471         flush_dcache_range((unsigned long) tb, (unsigned long) (tb+2));
 472
 473         tbdf->cbd_bufaddr = __pa(tb);
 474         tbdf->cbd_datlen = len;
 475         tbdf->cbd_sc =
 476                 BD_SC_READY | BD_SC_LAST |
 477                 BD_SC_WRAP | BD_IIC_START;
 478
 479         rbdf->cbd_datlen = 0;
 480         rbdf->cbd_bufaddr = __pa(tb+2);
 481         rbdf->cbd_sc = BD_SC_EMPTY | BD_SC_WRAP | BD_SC_INTRPT;
 482
 483         local_irq_save(flags);
 484         i2c->i2c_i2cmr = 0x13;  /* Enable some interupts */
 485         i2c->i2c_i2cer = 0xff;
 486         i2c->i2c_i2mod |= 1;    /* Enable */
 487         i2c->i2c_i2com |= 0x80; /* Begin transmission */
 488
 489         if (cpm_debug > 1) printk("about to sleep\n");
 490
 491         /* wait for IIC transfer */
 492         tmo = interruptible_sleep_on_timeout(&iic_wait,1*HZ);
 493         local_irq_restore(flags);
 494
 495 #ifdef I2C_CHIP_ERRATA
 496         /* Chip errata, clear enable. This is not needed on rev D4 CPUs.
 497          Disabling I2C too early may cause too short stop condition */
 498         udelay(4);
 499         i2c->i2c_i2mod &= ~1;
 500 #endif
 501
 502         if (signal_pending(current) || !tmo){
 503                 force_close(cpm);
 504                 if(cpm_debug && !tmo)
 505                         printk("IIC tryaddress: timeout!\n");
 506                 return -EIO;
 507         }
 508
 509         if (cpm_debug > 1) printk("back from sleep\n");
 510
 511         if (tbdf->cbd_sc & BD_SC_NAK) {
 512                 if (cpm_debug > 1) printk("IIC try; no ack\n");
 513                 return 0;
 514         }
 515
 516         if (tbdf->cbd_sc & BD_SC_READY) {
 517                 printk("IIC try; complete but tbuf ready\n");
 518         }
 519
 520         return 1;
 521 }
 522
 523 static int cpm_xfer(struct i2c_adapter *i2c_adap,
 524                     struct i2c_msg msgs[],
 525                     int num)
 526 {
 527         struct i2c_algo_8xx_data *adap = i2c_adap->algo_data;
 528         struct i2c_msg *pmsg;
 529         int i, ret;
 530         u_char addr;
 531
 532         for (i = 0; i < num; i++) {
 533                 pmsg = &msgs[i];
 534
 535                 if (cpm_debug)
 536                         printk("i2c-algo-8xx.o: "
 537                                "#%d addr=0x%x flags=0x%x len=%d\n buf=%lx\n",
 538                                i, pmsg->addr, pmsg->flags, pmsg->len, (unsigned long)pmsg->buf);
 539
 540                 addr = pmsg->addr << 1;
 541                 if (pmsg->flags & I2C_M_RD )
 542                         addr |= 1;
 543                 if (pmsg->flags & I2C_M_REV_DIR_ADDR )
 544                         addr ^= 1;
 545
 546                 if (!(pmsg->flags & I2C_M_NOSTART)) {
 547                 }
 548                 if (pmsg->flags & I2C_M_RD ) {
 549                         /* read bytes into buffer*/
 550                         ret = cpm_iic_read(adap, addr, pmsg->buf, pmsg->len);
 551                         if (cpm_debug)
 552                                 printk("i2c-algo-8xx.o: read %d bytes\n", ret);
 553                         if (ret < pmsg->len ) {
 554                                 return (ret<0)? ret : -EREMOTEIO;
 555                         }
 556                 } else {
 557                         /* write bytes from buffer */
 558                         ret = cpm_iic_write(adap, addr, pmsg->buf, pmsg->len);
 559                         if (cpm_debug)
 560                                 printk("i2c-algo-8xx.o: wrote %d\n", ret);
 561                         if (ret < pmsg->len ) {
 562                                 return (ret<0) ? ret : -EREMOTEIO;
 563                         }
 564                 }
 565         }
 566         return (num);
 567 }
 568
 569 static int algo_control(struct i2c_adapter *adapter,
 570         unsigned int cmd, unsigned long arg)
 571 {
 572         return 0;
 573 }
 574
 575 static u32 cpm_func(struct i2c_adapter *adap)
 576 {
 577         return I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR |
 578                I2C_FUNC_PROTOCOL_MANGLING;
 579 }
 580
 581 /* -----exported algorithm data: -------------------------------------  */
 582
 583 static struct i2c_algorithm cpm_algo = {
 584         "MPC8xx CPM algorithm",
 585         I2C_ALGO_MPC8XX,
 586         cpm_xfer,
 587         NULL,
 588         NULL,                           /* slave_xmit           */
 589         NULL,                           /* slave_recv           */
 590         algo_control,                   /* ioctl                */
 591         cpm_func,                       /* functionality        */
 592 };
 593
 594 /*
 595  * registering functions to load algorithms at runtime
 596  */
 597 int i2c_8xx_add_bus(struct i2c_adapter *adap)
 598 {
 599         int i;
 600         struct i2c_algo_8xx_data *cpm_adap = adap->algo_data;
 601
 602         if (cpm_debug)
 603                 printk("i2c-algo-8xx.o: hw routines for %s registered.\n",
 604                        adap->name);
 605
 606         /* register new adapter to i2c module... */
 607
 608         adap->id |= cpm_algo.id;
 609         adap->algo = &cpm_algo;
 610
 611 #ifdef MODULE
 612         MOD_INC_USE_COUNT;
 613 #endif
 614
 615         i2c_add_adapter(adap);
 616         cpm_iic_init(cpm_adap);
 617
 618         /* scan bus */
 619         if (cpm_scan) {
 620                 printk(KERN_INFO " i2c-algo-8xx.o: scanning bus %s...\n",
 621                        adap->name);
 622                 for (i = 0; i < 128; i++) {
 623                         if (cpm_iic_tryaddress(cpm_adap, i)) {
 624                                 printk("(%02x)",i<<1);
 625                         }
 626                 }
 627                 printk("\n");
 628         }
 629         return 0;
 630 }
 631
 632
 633 int i2c_8xx_del_bus(struct i2c_adapter *adap)
 634 {
 635         int res;
 636         struct i2c_algo_8xx_data *cpm_adap = adap->algo_data;
 637
 638         cpm_iic_shutdown(cpm_adap);
 639
 640         if ((res = i2c_del_adapter(adap)) < 0)
 641                 return res;
 642
 643         printk("i2c-algo-8xx.o: adapter unregistered: %s\n",adap->name);
 644
 645 #ifdef MODULE
 646         MOD_DEC_USE_COUNT;
 647 #endif
 648         return 0;
 649 }
 650
 651 EXPORT_SYMBOL(i2c_8xx_add_bus);
 652 EXPORT_SYMBOL(i2c_8xx_del_bus);
 653
 654 int __init i2c_algo_8xx_init (void)
 655 {
 656         printk("i2c-algo-8xx.o: i2c mpc8xx algorithm module version %s (%s)\n", I2C_VERSION, I2C_DATE);
 657         return 0;
 658 }
 659
 660
 661 #ifdef MODULE
 662 MODULE_AUTHOR("Brad Parker <brad@heeltoe.com>");
 663 MODULE_DESCRIPTION("I2C-Bus MPC8XX algorithm");
 664 #ifdef MODULE_LICENSE
 665 MODULE_LICENSE("GPL");
 666 #endif
 667
 668 int init_module(void)
 669 {
 670         return i2c_algo_8xx_init();
 671 }
 672
 673 void cleanup_module(void)
 674 {
 675 }
 676 #endif